COMBINATIONAL CIRCUITS

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 Subtopics
• Combinational logic and building blocks
• Delays
• Binary arithmetic
• Arithmetic circuits
• Decoders and Encoders
• Multiplexers and Demultiplexers
• ROMs, PALs and PLAs.

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 COMBINATIONAL LOGIC
• Combinational logic is a type of digital logic
which is implemented by Boolean circuits, where
the output is a pure function of the present input
only
• It is memoryless
• Three main ways of specifying the function of a
combinational logic circuits are:
❖Boolean Algebra
❖Truth table
❖Logic diagram
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 IMPLEMENTING COMBINATIONAL
CIRCUITS
STEPS
1.Statement of the problem
2.Identification of the input and output
variables
3.Expressing the relationship between the
input and output variables
4.Construction of truth table to meet input
output requirements
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5. Writing Boolean expression for
various output variables in
terms of input variables
6. Minimization of Boolean
expression
7. Implementation of minimized
Boolean expression

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 PROBLEM
A ‘majority function’ circuit has three
inputs (X,Y, Z) and one output, F. each
input has a value of 1 or 0. for this circuit,
the output F will take the value of the
majority of the inputs. For example, if the
inputs XYZ = 101, the output F will be 1
since the majority of the inputs are 1.
Design the circuit
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 ARITHMETIC CIRCUIT
• Binary adder: a circuit which performs the
addition of two binary numbers is known as
Binary adder, which performs the addition of
two bits
• Half adder: it adds two binary numbers A and
B are of single bit. It produces two outputs
sum S and carry, C

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 Half adder truth table and circuit
A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

S = A XOR B
C=A+B
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 Full adder
• Is a combinational circuit, which performs the addition
of three bits A, B, Cin where, A and B are the two
parallel significant bits and Cin is the carry bit, which is
generated from previous stage
• It also produces two outputs sum S, and carry, Cout ,
which are similar to half adder.
• It is called a Full adder because for implementing one
full adder, we require two half adders and one OR gate.
If Cin
• is zero, then Full adder becomes half adder.
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 Full adder truth table and circuit
A B Cin Cout S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

S = A XOR B XOR Cin

Cout = AB + (A XOR B) Cin
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 Half subtractor
• Is a combinational circuit that can be
used to subtract one binary digit from
another to produce a DIFFERENCE output
and a BORROW output.
• The BORROW output here specifies
whether a ‘1’ has been borrowed to
perform the subtraction.

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Half subtractor circuit and truth table

A B D B0

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Borrow = A.B
DIFFERENCE = A XOR B

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 Full subtractor
• It subtracts two bits, a minuend and subtrahend,
and also takes into consideration whether ‘1’ has
already been borrowed by the previous adjacent
lower minuend bit or not.
• As a result there are three bits to be handled at the
input of a full subtractor, namely two bits to be
subtracted and a borrow bit designated as B0 then
are two outputs, namely the DIFFERENCE D and the
borrow output B0 . The BORROW output bit tells
whether, the minuend bit needs to borrow a ‘1’
from the next possible higher minuend bit
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 full subtractor circuit and truth table
A B Bin D Bout

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

• Borrow = A'.B + (A ⊕ B)’

• difference is (A XOR B) XOR
'Borrowin' which is also represented
as:
(A ⊕ B) ⊕ 'Borrowin'
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 DECODER
• Is a combinational circuit that has 'n' input
lines . One these outputs will be active High
based on the combination of inputs present,
when the decoder is enabled. That means
decoder detects a particular code.
• The outputs of the decoder are nothing but
the min terms of 'n' input variable lines,
when it is enabled
 2 to 4 decoder block diagram and truth
table

• only one of four outputs could be '1 for each

combination of inputs
 Boolean functions

• Y3 = E.A1.A0
• Y2 = E1.A1.A0'
• Y1 = E.A1'.A0
• Y0=E.A1'.A0'
• Question: draw the circuit diagram
for 3 to 8 decoder
Circuit diagram for 2x4 decoder
 Implementation of Higher-order Decoders

• The required number of lower order decoders =

m2/m1 where
m1 is the number of outputs of lower order
decoder
m2 is the number of outputs higher order decoder
E.G for 3 to 8 decoder m1=4 and m2 = 8
• therefore, required number of 2 to 4 decoders are
8/4 = 2
Implementing 3 to 8 decoder using two 2
to 4 decoders

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 Encoders
• An Encoder is a combinational circuit that
performs the reverse operation of Decoder.
• It has maximum of 2n input lines and ‘n’ output
lines.
• It will produce a binary code equivalent to the
input, which is active High.
• Therefore, the encoder encodes 2n input lines
with ‘n’ bits. It is optional to represent the enable
signal in encoders
• at any point in time, only one of the input is HIGH
 4 to 2 decoder block diagram and truth
table

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Boolean function and circuit diagram

Boolean functions:-
A1 = Y3+Y2
A0 = Y3+Y1
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 multiplexer
• Multiplexer is a combinational circuit that has
maximum of 2n data inputs, ‘n’ selection lines
and single output line.
• One of these data inputs will be connected to the
output based on the values of selection lines.
• Since there are ‘n’ selection lines, there will be
2n possible combinations of zeros and ones. So,
each combination will select only one data input.
• Multiplexer is also called as Mux.
 4 x 1 multiplexer
• 4x1 Multiplexer has four data inputs
I3, I2, I1 & I0, two selection lines s1 &
s0 and one output Y.
• draw its circuit diagram
• implement 8x1 multiplexer and 16x1
multiplexer
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 Y=S1ʹS0ʹI0+S1ʹS0I1+S1S0ʹI2+S1S0I3

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• Note: higher order multiplexers can
be implemented by using lower
order multiplexers
• e.g. 8x1 multiplexer can be
implemented using 4x1 multiplexers
will be used in first stage and one 2x1
multiplexer in the second
 demultiplexer
• De-Multiplexer is a combinational circuit
that performs the reverse operation of
Multiplexer. It has single input, ‘n’ selection
lines and maximum of 2n outputs. The input
will be connected to one of these outputs
based on the values of selection lines.
• De-Multiplexer is also called as De-Mux.
 1x4 De-Multiplexer
• 1x4 De-Multiplexer has one input I, two
selection lines, s1 & s0 and four outputs Y3, Y2,
Y1 &Y0.

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 Truth table and circuit

Y3=S1S0IY3=S1S0I
Y2=S1S0ʹIY2=S1S0ʹI
Y1=S1ʹS0IY1=S1ʹS0I
Y0=S1ʹS0ʹI

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 Circuit diagram

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implementation of Higher order De-Mux

• e.g. 1x8 De-Mux requires two

1x4 De-mux in the second stage
and one 1x2 De-Mux in the first
stage
• implement a 1x16 De-
Multiplexer
 PROGRAMMABLE LOGIC DEVICES (PLD)
• PLDs are the integrated circuits. They contain an array of
AND gates and another array of OR gates. There are
three types of PLDs based on the type of arrays which has
programmable feature:-
– Programmable Read Only Memory
– Programmable Array Logic
– Programmable Logic Array
• The process of entering the information into these
devices is known as programming. It is hardware and not
software programming
 Programmable Read Only
Memory (PROM)
ROM is a memory device, which stores the
binary information permanently.
If the ROM has programmable feature, then it is
called as Programmable ROM (PROM). The user
has the flexibility to program the binary
information electrically once by using PROM
programmer.
PROM is a programmable logic device that has
fixed AND array & Programmable OR array.

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 PROM building block

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 Example
• implement these Boolean functions using PROM.
• A(X,Y,Z)=∑m(5,6,7)
• B(X,Y,Z)=∑m(3,5,6,7)
• The two given functions are in sum of min terms
form and each have three variables X,Y and Z. So
we require a 3 to 8 decoder and two
programmable OR gates for producing these two
functions.

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 PROM example

The symbol 'X' is used for

programmable connections

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 Programmable Array Logic (PAL)
• PAL is a programmable logic device that
has Programmable AND array & fixed OR
array.
• The advantage of PAL is that we can
generate only the required product terms
of Boolean function instead of generating
all the min terms by using programmable
AND gates.
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 Example

• Let us implement the

following Boolean
functions using PAL.
• A=XY+XZʹ
A=XYʹ+YZʹ

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 Example
• Lets Implement the following functions using
PAL
• A=XY + XZ'
• A = XY' + YZ’
• The given two functions are in sum of products
form. there are two product terms present in
each Boolean function. so, we require four
programmable AND gates and tow fixed OR
gates for producing those two functions.
 Programmable Logic Array (PLA)
• PLA is a programmable logic device that has both
Programmable AND array & Programmable OR
array. Hence, it is the most flexible PLD
• Example
• implement the following Boolean functions using
PLA
• A= XY + XZ'
• B = XY' + YZ + XZ'
• The given two functions are in sum of
products from. the number of product
terms are 2 and 3 and one product
term, Z'X is common in each function.
• 4 programmable AND gates and 2
programmable OR gates are required
for producing those two functions
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