COMP

302 Digital Design and Computer Architecture

LEC
Decoders and Multiplexers
5 Textbook chapter 2

Fall 2024 Dr. Amr Hefny Cairo University

Decoders

•A Decoder is a combinational circuit that converts

binary information from 𝑛 input lines to a maximum of
2𝑛 unique output lines
•If the 𝑛 −bit coded information has unused
combinations, the decoder may have fewer than 2𝑛
outputs
•Consider a vending machine that takes 3
bits as input and releases a single
product, out of the available 8 product
sorts
Output
Input pad Vending select
Machine line
Decoders

•It is required to design a combinational circuit with

two inputs (𝑎, 𝑏) and four outputs (𝐷0, 𝐷1, 𝐷2, 𝐷3),
such that:

• 𝐷0 = 1 when 𝑎 = 0 and 𝑏 = 0
• 𝐷1 = 1 when 𝑎 = 0 and 𝑏 = 1
• 𝐷2 = 1 when 𝑎 = 1 and 𝑏 = 0
• 𝐷3 = 1 when 𝑎 = 1 and 𝑏 = 1
Decoders

2. Derive the truth table that defines the required

relationship between the inputs and outputs

Inputs Outputs

𝑎 𝑏 𝐷0 𝐷1 𝐷2 𝐷3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Decoders

3. Obtain the simplified Boolean functions for each

output as a function of the input variables
𝐷0 = 𝑎′𝑏′
𝑏
𝐷1 = 𝑎′𝑏 𝐷0

𝐷2 = 𝑎𝑏′
𝐷1
𝐷3 = 𝑎𝑏
4. Sketch the logic diagram
𝐷2
𝑎
𝐷3
 3 x 8 Decoders
𝑧

•A 3 × 8 line decoder decodes 3

input bits into one of 8 possible
outputs
•Each output represents one
of the minterms of the 3
input variables
2 x 4 Decoders

•A decoder could include an Enable input to

control the circuit operation

•A decoder could be implemented 𝐷0

with NAND gates and thus
produces the minterms in their
𝐷1
complemented form
𝐴
𝐷2
𝐵

𝐷3
𝐸
Implementing functions using decoders

•Any combinational circuit can be constructed using

decoders and OR gates (the decoder generates the
minterms and the OR gate performs the summation)
•Example: Implement a full adder circuit with a decoder
and two OR gates
• Full adder equations:
𝑆 (𝑥, 𝑦, 𝑧) = Σ(1,2,4,7) and
𝐶 (𝑥, 𝑦, 𝑧) = Σ(3,5,6,7)
• Since there are 3 inputs, we need a 3 × 8 decoder
Implementing functions using decoders

𝑆 (𝑥, 𝑦, 𝑧) = Σ(1,2,4,7) and Inputs Outputs

𝐶 (𝑥, 𝑦, 𝑧) = Σ(3,5,6,7)
𝑥 𝑦 𝑧 𝐶 𝑆
0 0 0 0 0
0 0 1 0 1

𝑆 0 1 0 0 1
𝑥 0 1 1 1 0
𝑦 1 0 0 0 1
1 0 1 1 0
𝑧 𝐶
1 1 0 1 0
1 1 1 1 1
Using a decoder and external gates, design the
combinational circuit defined by the following Boolean
functions:

(a) 𝐹 = 𝑥ҧ + 𝑥𝑧

(b) 𝐹2 = 𝑥 + 𝑦ത 𝑧ҧ
Decoder expansions
•Larger decoders can be constructed using a number of smaller
ones
•For example, a 3 × 8 decoder can be built using a couple of 2 ×
4 decoders and a 4 × 16 decoder can be built using a couple of
3 × 8 decoders
𝑥
𝐷0 to 𝐷7
𝑦
𝑧

𝐷8 to 𝐷15

4 × 16 Decoder
EXERCISE

• Can you sketch a 4 × 16 decoder using a number of

2×4
decoders?
• I am now giving you 5 minutes to attempt it
• After these 5 minutes, the lecture will continue
4 × 16 decoder using enabled 2 × 4 decoders

15
 Encoders

•An encoder is a digital circuit that performs the

inverse operation of a decoder
• An encoder has 2𝑛 input lines and 𝑛 output lines
•The output lines generate the binary equivalent
of the input line whose value is 1

16
8×3 octal-to-binary encoder

What happens if more than one input is

𝑥= 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7 active (set to HIGH) at the same time?
𝑦= 𝐷2 + 𝐷3+ 𝐷6 + 𝐷7 For example, 𝐷3and 𝐷6?
𝑧= 𝐷1 + 𝐷3+ 𝐷5 + 𝐷7
What happens if all inputs are equal to 0?

17
 Making connections

• Direct point-to-point connections between gates are

made up
of wires
•Routing one of many inputs to a single output is
carried out using a multiplexer
•Routing a single input to one of many outputs is
carried out using a demultiplexer
Control Control

Multiplexer Demultiplexer 21
Multiplexers

• A multiplexer is used to connect 2𝑛 𝑰𝟏 𝑰𝟎 𝑨 𝒁

points to a single point
• The control signal pattern forms the 0 0 0 0
binary index of the input to be 0 0 1 0
connected to the output 0 1 0 1
0 1 1 0
1 0 0 0
𝑍 = 𝐴′𝐼0 + 𝐴𝐼1 1 0 1 1
𝑨 𝒁
1 1 0 1
0 𝐼𝟎 𝐼𝟎 2×1
𝑍 1 1 1 1
1 𝐼𝟏 𝐼𝟏 MUX

Functional Logical
𝐴
form form
1
8
Multiplexers

𝐼𝟎
𝐼𝟎 𝐼𝟏
𝐼𝟎 2×1 𝐼𝟏 4×1 𝐼𝟐
𝑍 𝑍 8×1 𝑍
𝐼𝟏 MUX 𝐼𝟐 MUX
𝐼𝟑 MUX
𝐼𝟑 𝐼𝟒
𝐴 𝐼𝟓
𝐴 𝐵 𝐼𝟔
𝐼𝟕

𝐴𝐵𝐶

1
9
2×1 line multiplexer

𝐼𝟎
𝐼𝟎
𝑍 𝑍
𝐼𝟏
𝐼𝟏

𝑆
𝑆

2
0
4×1 line multiplexer

𝐼𝟎

𝑺𝟎 𝑺𝟏 𝒁
𝐼𝟏
0 0 𝐼𝟎
𝑍
0 1 𝐼𝟏 𝐼𝟐

1 0 𝐼𝟐
𝐼𝟑
1 1 𝐼𝟑

Functional Can you sketch the logic

form diagram of an 8×1
multiplexer?
𝑆0
𝑆1 25
8×1 line multiplexer

•I am now giving you 5 minutes to attempt sketching the

logic diagram of an 8×1 line multiplexer
• After these 5 minutes, the lecture will continue

22
8×1 line multiplexer

23
Multiplexers using three-state buffers

𝐼𝟎 𝑌

𝐼𝟏

𝐴 𝑌
𝐼𝟐

𝐼𝟑
𝐵

𝑆𝑒𝑙𝑒𝑐𝑡
𝑆𝑒𝑙𝑒𝑐𝑡
𝐸𝑛𝑎𝑏𝑙𝑒

2 × 1 line MUX 4 × 1 line MUX

Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1
multiplexers.
Multiplexers as general-purpose logic

• A 2𝑛−1: 1 multiplexer can implement any function of

𝑛 variables
• Steps:
1. The Boolean function is listed in a truth table
2. The first 𝑛 − 1 variables in the table are applied to
the selection inputs of the MUX
3. For each combination of the selection variables,
evaluate the output as a function of the last
variable
4. The values are then applied to the data inputs in
the proper order
2
6
Multiplexers as general-purpose logic:
example I

𝐹 𝑥, 𝑦, 𝑧 = Σ(1,2,6,7)

𝑦
𝑥

𝑧 𝐹
𝑧′
0
1

2
7
Multiplexers as general-purpose logic:
example II
𝐹 (𝐴, 𝐵, 𝐶, 𝐷 )= Σ(1,3,4,11,12,13,14,15)

𝐶
𝐵
𝐴

𝐷
𝐹

2
8