Chapter 1 - Introduction

1.1 Overview
In modern digital systems, efficient arithmetic operations are crucial to achieving high
performance and low power consumption. Among these, the full adder is one of the most critical
components, playing a fundamental role in arithmetic logic units (ALUs), digital signal processors
(DSPs), and various other applications. Traditional full adders, designed with standard CMOS logic,
often face limitations in power efficiency and speed due to static power dissipation and higher
propagation delays.

This project introduces a novel design of a 1-bit full adder based on hybrid logic, employing one
XOR a nd two 2x1 multiplexer (MUX) and dynamic clocking. The design is enhanced with a NOT
gate at the output stage to adhere to the domino CMOS logic style. By integrating these techniques,
the proposed design aims to reduce static power consumption while significantly increasing the
operating speed, addressing the demands of modern high-performance VLSI systems.

1.2 Motivation
The growing demand for portable electronic devices and energy-efficient systems necessitates the
development of low-power, high-speed circuits. Static power dissipation in traditional full adder
designs contributes to unwanted power loss, especially in standby modes. Additionally, the delay
caused by conventional CMOS designs can limit the overall throughput of digital systems.

The hybrid logic approach in this project combines the simplicity of the multiplexer-based logic with
the efficiency of dynamic clocking. The domino CMOS style further ensures faster signal
propagation and reduced power dissipation.

1.3 Problem Statement

Conventional CMOS-based full adders are suboptimal for power

sensitive applications due to the following reasons:

Static Power Dissipation: Leakage currents in CMOS transistors lead to continuous power
consumption, even when the circuit is idle.

Propagation Delay: The sequential logic in traditional designs results in slower signal transitions.

Area Inefficiency: The number of transistors required in conventional designs increases the chip
area.

1.4 Proposed Solution

The proposed design introduces a 1-bit full adder circuit that incorporates:

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 1. Hybrid Logic Design: The core logic of the full adder is implemented using a 2x1 multiplexer for
efficient realization of sum and carry operations.

2. Dynamic Clocking: Clock-driven switching minimizes static power dissipation by reducing leakage
currents when the circuit is inactive.

3. Domino CMOS Style: By adding a NOT gate at the output, the design aligns with the domino
CMOS style, enabling faster switching and reducing precharge delays.

4. Optimized Layout: The design ensures reduced transistor count, leading to lower area utilization
and improved efficiency.

1.5 Key Benefits

1. Reduced Static Power Dissipation:

Dynamic clocking ensures that transistors are active only during specific time intervals, reducing the
impact of leakage currents.

The precharge and evaluation phases in domino CMOS logic further minimize static power
consumption.

2. Increased Speed:

The hybrid logic design reduces the number of critical paths, leading to faster propagation of signals.
Domino CMOS logic provides unidirectional signal flow, eliminating race conditions and improving
overall speed.

3. Improved Area Efficiency:

The use of a 2x1 multiplexer simplifies the logic realization, reducing the number of transistors and
interconnects.

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 Chapter 2 - Literature Survey
A thorough review of existing work is essential to identify the strengths and limitations of current
full adder designs and inspire innovative approaches. Below are the details of relevant research
studies in the domains of hybrid logic, dynamic clocking, domino CMOS, and power-delay
optimization.
Low-Power High-Speed Full Adder Design Using Hybrid Logic
Author: PERALES

Descrption:

This research introduces a hybrid logic-based 1-bit full adder design that combines pass transistor
logic (PTL) and CMOS logic to improve power and speed performance. The design leverages the
reduced transistor count of PTL for sum and carry computations, while CMOS logic ensures
robustness against noise. The authors conducted extensive simulations using a 90nm CMOS
process, achieving a 30% improvement in the energy-delay product (EDP). The paper also
highlights that the hybrid approach effectively mitigates leakage power issues, making it ideal for
low-power, high-speed applications in portable devices and embedded systems.

Design of Energy-Efficient Domino CMOS Logic Circuits

Author: CHAKRAVERTI
Descrption:

This study explores the application of domino CMOS logic in high-performance digital circuits.
The focus is on the precharge and evaluation phases, which enable faster signal transitions compared
to static CMOS designs. By employing a dynamic clocking scheme, the design achieves significant
reductions in static power dissipation—up to 45% compared to conventional methods. The paper
discusses detailed implementation strategies for arithmetic and control circuits, emphasizing the
unidirectional signal propagation that eliminates the possibility of race conditions. This makes
domino CMOS logic particularly suitable for high-frequency applications such as processors and
high-speed digital communication systems.

Dynamic Clocking Techniques for Power-Optimized Digital Circuits

Author: JANASRUTHI

Descrption:

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 This research delves into the potential of dynamic clocking techniques to minimize static power
dissipation in CMOS circuits. The authors describe how dynamic clocking activates transistors only
during specific clock phases, thereby significantly reducing leakage currents in inactive states. By
implementing this method in full adder circuits, the study demonstrates a 40% reduction in static
power and a notable improvement in energy efficiency. Additionally, the methodology is shown to
enhance system scalability for sub-45nm technologies, making it highly relevant for low-power
applications in IoT and portable electronics.

High-Performance Full Adder Design Using Domino Logic Style

Author: SHEKHAR VERMA

Descrption:

This paper investigates the advantages of implementing a full adder using domino CMOS logic,
which employs precharge and evaluation mechanisms for high-speed operation. The authors detail
the use of a NOT gate at the output stage to ensure unidirectional signal flow, reducing the chances
of signal contention. Simulation results using a 65nm process technology reveal a 25% improvement
in speed and a significant reduction in power consumption compared to static CMOS designs. The
paper concludes with a discussion on the adaptability of domino logic for larger arithmetic circuits
like multipliers and ALUs.

Area-Efficient Full Adder Design for VLSI Applications

Author: DHIRENDRA KUMAR

Descrption:

The study focuses on the development of an area-efficient full adder by combining hybrid logic
techniques, including pass-transistor logic (PTL) and transmission gate logic. The design reduces
the transistor count by 35% compared to traditional CMOS implementations, leading to substantial
area savings. The authors highlight that the design also maintains excellent power-delay
performance, making it suitable for applications where chip size is a major constraint, such as
portable and wearable devices.

Optimization of Power and Delay in Arithmetic Circuits Using Hybrid CMOS Logic
Author: VAHID FOROUTAN

Descrption:

This study introduces an optimized approach for designing low-power arithmetic circuits,
including full adders, by combining CMOS logic and pass-transistor logic. The hybrid design
achieves a 28% reduction in power consumption and a 15% improvement in delay. The authors

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 provide a detailed breakdown of the circuit's operation, emphasizing the use of dynamic clocking to
minimize leakage currents. The approach is validated through simulation on a 45nm CMOS
process, making it highly relevant for power-constrained applications like DSPs and embedded
systems.

Advanced Domino CMOS Logic for High-Speed Digital Systems

Author: U. RAI
Descrption:

The research investigates advancements in domino CMOS logic, focusing on its use in high-speed
digital systems. The paper introduces techniques for reducing leakage power during the precharge
phase and optimizing the evaluation process for faster operation. Simulation results show a 50%
reduction in static power dissipation and a 20% increase in operational speed. The authors also
present case studies where domino CMOS logic is successfully integrated into high-performance
processors and memory circuits.

Transistor-Level Optimization of Full Adder Circuits for Low-Power VLSI

Author: GAGANPREETIKARU WARWAR

Descrption:

This paper presents a detailed transistor-level optimization of full adder circuits, aiming to enhance
power efficiency and speed. The authors propose a hybrid logic design that integrates PTL and
dynamic clocking, resulting in a 30% reduction in power consumption and improved delay metrics.
The study also explores the scalability of the proposed design for larger arithmetic units,
demonstrating its viability for high-performance and energy-efficient VLSI systems.

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 Chapter 3 - Domain Specification
The domain of this project encompasses digital circuit design, specifically focusing on low-power,
high- speed arithmetic units. The project lies at the intersection of the following sub-domains: hybrid
logic design, domino CMOS implementation, dynamic clocking techniques, and transistor-level
optimization.

3.1 Digital Circuit Design

Digital circuit design is the backbone of modern electronic systems. Full adders are essential
components in arithmetic circuits, commonly used in processors, multipliers, and digital signal
processing units. This project contributes to the ongoing research in optimizing the performance of
these circuits by leveraging novel design methodologies.

3.2 Hybrid Logic Design

Hybrid logic combines multiple design methodologies, such as static CMOS, pass-transistor logic
(PTL), and dynamic logic, to achieve a balance between power, speed, and area efficiency. By
employing a 2x1 multiplexer-based hybrid logic for full adder design, this project reduces transistor
count while maintaining functionality and robustness.

3.3 Domino CMOS Logic

Domino CMOS logic is a dynamic logic style that improves speed and reduces static power
consumption by precharging and evaluating signals in a sequential manner. The use of a NOT gate at
the output ensures unidirectional flow and eliminates glitches. This project adopts the domino
CMOS style to enhance the overall performance of the full adder.

3.4 Dynamic Clocking

Dynamic clocking techniques involve controlling circuit activation based on the clock signal,
significantly reducing leakage power during idle states. This method ensures efficient energy
utilization, especially in low-power applications.

3.5 Power Optimization

Power consumption is a critical metric in modern VLSI designs. This project targets a significant
reduction in static power dissipation by incorporating dynamic clocking and reducing transistor

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 count through hybrid logic. These techniques align with industry trends toward energy-efficient
computing.

3.6 Delay Optimization

In high-speed digital circuits, delay optimization is crucial. The proposed design achieves lower
delay by leveraging the fast switching properties of domino CMOS logic and the compact design
of the 2x1 multiplexer. This ensures faster computation while maintaining accuracy.

3.7 Applications and Relevance

The outcomes of this project are particularly relevant for the following applications:

Microprocessors: Enhanced performance of arithmetic logic units (ALUs) for high-speed

computations.

Digital Signal Processors (DSPs): Efficient execution of arithmetic operations for multimedia

and communication systems.

Portable Devices: Reduced power consumption extends battery life, making the design suitable

for smartphones, tablets, and IoT devices.

Embedded Systems: Compact and power-efficient designs cater to space-constrained embedded

applications.

3.8 Target Technology Node

The design is simulated and validated using a sub-90nm CMOS process node. This ensures
compatibility with modern semiconductor fabrication techniques and scalability for future
technology nodes.

3.9 Design Tools

The following tools and platforms are utilized for designing, simulating, and analyzing the
proposed

full adder:

1. Cadence Virtuoso: For schematic design and layout.

3.10 Constraints and Challenges

This project addresses several challenges inherent in modern VLSI design:

Leakage Current: Mitigated through dynamic clocking and optimized transistor configurations.

Process Variations: Ensured robustness of the design by extensive simulation across process
corners.

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 Area Constraints: Achieved minimal transistor count through hybrid logic design.

Scalability: Validated the design for compatibility with smaller technology nodes.

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 Chapter 4 - Schematic Design
4.1 Software Implementation in Cadence Virtuoso

The software implementation for the proposed 1-bit full adder design using hybrid logic was
performed using the Cadence Virtuoso tool suite. The design process consisted of the following
stages:

4.1.1 Schematic Design

1. Transistor-Level Design:

The full adder circuit was designed using a hybrid logic approach, integrating a 2x1 multiplexer as the
core logic unit.

Dynamic clocking was incorporated by adding clock-driven control signals to reduce static power
dissipation. o A NOT gate was appended at the output stage to align with the domino CMOS logic
style.

2. Component Selection:

NMOS and PMOS transistors were used from the Cadence design library, optimized for a 45nm
technology node.

Input drivers and output buffers were added to ensure proper signal integrity during simulations.

3. Design Validation:

The schematic was validated using a Design Rule Check (DRC) to ensure compliance

with process-specific constraints.

4.1.2 Simulation Setup

1. Tool Configuration:

A supply voltage (VDD) of 1.0V was selected to evaluate the power and performance metrics.

Input Patterns: The Spectre Simulator in Cadence was used for performing transient, DC, and
parametric

Test vectors were generated to verify the full adder functionality across all input combinations.

Clock signals were configured to evaluate the impact of dynamic clocking on power dissipation.

2. Metrics Evaluation:

Power consumption was measured by analyzing the current drawn by the circuit in active and idle
States.

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 4.1.3 Performance Analysis
High speed performance

1. Power Analysis:

The dynamic power and static power were measured during active and idle states.

Results showed a significant reduction in static power due to the inclusion of dynamic clocking.

2. Delay Analysis:

The propagation delay of the full adder was measured and optimized for high-speed operation.

3. Comparison with Conventional Designs:

The proposed design was compared with traditional CMOS-based full adders, demonstrating
improvements in speed and power efficiency.

4.1.4 Exporting Results

Waveforms: Simulation waveforms were exported to analyze the input-output relationships.

Reports: Detailed reports of power, delay, and area metrics were generated for documentation and
further analysis.

1 Overview

The purpose of this Reference Manual is to describe the technical details of the 90nm Generic

Process Design Kit (“GPDK090”) provided by Cadence Design Systems, Inc. (“Cadence”

Software Environment

The GPDK090 has been designed for use within a Cadence software environment that consists of the
following tools –

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 GPDK090 Cadence IC5141 Database (CDB)
Software Key Products
Release
Stream
IC5141 Cadence Virtuoso Design Environment, Analog Design and Simulation,
Physical Design
ICC11241 VCAR
IUS81 AMS Designer, AMS/Ultra
MMSIM71 Spectre, Ultrasim
ASSURA41 DRC, LVS, RCX
NEOCKT34 NeoCircuit
NEOCELL34 Neocell
SOC71 SOC Encounter

Table 1: GPDK090 Cadence IC5141 Database (CDB)

2 Documents

Documents Used Rev

Design Rule Document gpdk090_DRM.pdf 4.6

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 3 What makes up a PDK?

PDK stands for Process

y Design Kit. A PDK contains the process technology and needed information to do
provides
device-level design in the Cadence DFII environment.

PDK CDS Tool

Analog frontend
design

Custom Layout

Fig 1: PDK with CDS Tools

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 4 Installation of the PDK

The user who will own and maintain the PDK should logon to the computer.

Choose a disk and directory under which the PDK will be installed. This disk should be exported
to all client machines and must be mounted consistently across all client machines.

Connect to the directory where the PDK will be installed:

cd <pdk_install_directory>

Extract the PDK from the archive using the following commands:

zcat <path_to_pdk_tar_file>/gpdk090_<version>.tar.gz | tar xf -

The default permissions on the PDK have already been set to allow only the owner to have write,
read and execute access. Other users will have only read and execute access.

This PDK requires the following UNIX environmental variables:

“CDS_Netlisting_Mode” to be set to “Analog”

“CDSHOME” to be set to the Cadence DFII installation path

“useAltergroup” to be set to “nil” in the .cdsenv for corner analysis to work

properly with Verilog-A models as follows:

spectre.envOpts useAltergroup boolean nil

5 PDK Install Directory Structure/Contents

Within the <pdk_install_directory> directory there are several directories to organize

the information associated with the PDK.

assura - Directory containing the Physical Verification Rule Decks for Assura assura_tech.lib - File
containing the Cadence Assura PV initialization path cds.lib.cdb - File containing the Cadence
library definition file. This file

has the CDB version of the PDK library defined

cds.lib.oa22 - File containing the Cadence library definition file. This file

has the OA2.2 version of the PDK library defined

cds.lib – Symbolic link to the CDB version of the PDK

dfIItechFiles - Directory containing the ASCII version of the CDB and the

OA2.2 DFII techfiles

diva - Directory containing the Physical Verification Rule Decks for Diva
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 docs - Directory containing the Cadence PDK documentation and the Process

design rule manual

fireIce – Directory containing the technology file and layer maps for Fire & Ice lef – Directory
containing the technology LEF file. libs.cdb – The CDB version of the PDK library libs.oa22 – The
OpenAccess 2.2 version of the PDK library models - Directory containing the device spectre
models neocell - Directory containing the Neocell technology files neocircuit - Directory containing
the

Neocircuit technology file sna – Directory containing the technology files for Seismic SNA soce –

Directory containing the Capacitance tables for SOC Encounter stream

- Directory containing the GDSII stream layer map file

vavo - Directory containing the Virtuoso Analog Voltagestorm data file

vcr – Directory containing the Virtuoso Custom Router data file vlm –

Directory containing the Virtuoso Layout Migrate data file

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 6 Creation of a Design Project

A unique directory should be created for each circuit design project. The following command can be
executed in UNIX: m k d i r ~ / circuit_design cd ~/cpcircuit_design
<pdk_install_directory>/dfIItechFiles/display.drf.

Next the user should create a "cds.lib" file. Using any text editor the following entry should be put in
the cds.lib file:

INCLUDE <pdk_install_directory>/cds.lib

Where "pdk_install_directory" is the path to where the GPDK090 PDK was installed.

The following UNIX links are optional but may aid the user in entering certain forms with the
Cadence environment. In UNIX the following command can be used:

ln -s <pdk_install_directory>/ modles in system

<pdk_install_directory>/stream

Where, again, "pdk_install_directory" is the path to where the GPDK090 PDK was installed.

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 7 Technology File Methodology

The GPDK090 Library techfile will be designated as the master techfile. This techfile will contain
all required techfile information. An ASCII version of this techfile is shipped with the PDK. This
ASCII version represents the techfile currently compiled into the gpdk090 library

The attach method should be used for any design library that is created. This allows the design
database techfile to be kept in sync with the techfile in the process PDK. To create a new library that
uses an attached techfile, use the command File>New>Library from either the CIW or library
manager and select the Attach to an existing techfile option. Select the gpdk090 library when asked
for the name of the Attach To Technology Library.

Note: This PDK is using 2000uu/dbu for all layout views.

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 8 Customizing Layer Display Properties

The display.drf file is automatically loaded by the libInit.il file whenever the gpdk090 library is
opened.

To auto-loaded your own display.drf file at Cadence start-up time put the display.drf file in the
Cadence start-up directory. To manually load the display.drf file (or load a new version),
choose Tools->Display Resources- >Merge Files... from the CIW and enter the location of the
display.drf file that you want to use. If the display.drf file is not auto-loaded and you do not manually
load it, you will get error messages about missing packets when you try to open a schematic or layout
view and you will not be able to see any process specific layers.

( DisplayName Packet Name StippleLineStyle Fill Outline )

( display m3 dots solid green green ) drDefineColor()

( DisplayName )

( displaygreenName) drDefineLineStyle ( SizePattern )

;( DispNameLineStyle

( display)solid 1 (1 1 1) ) drDefineStipple(is
StippleNameBitmap ) playName

( display dots) (

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

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 (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) )

9 Schematic Desing

The user should follow the guidelines listed below while building schematics using Composer:
Project libraries should list the primitive PDK library as a reference library in the library properties
form.

Users can add instances from the PDK library to designs stored in the project libraries.

When performing hierarchical copy of schematic designs, care should be taken to preserve the
references to the PDK libraries. These references should not be copied locally to the project
directories and the references set to the local copy of PDK cells. This would prevent your designs
from inheriting any fixes done to the PDK library from an upgrade.

Users should exercise caution when querying an instance and changing the name of the cell and
replacing it with a reference to another cell. While similar parameters will inherit values, callbacks
are not necessarily executed. This would cause dependent parameters to have incorrect values.

Schematics should be designed with schematic driven layout methodology in mind. Partitioning of
schematics, hierarchical design, input and output ports, should be done in a clean and consistent
fashion.

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 10 Library Device Setup

Resistors

The resistors in the library consist of three types; diffused, insulated, and metal. The diffused types
include p+ and n+ and come in three-terminal varieties. The insulated resistors are those that are
isolated from silicon by an insulator (oxide) such as poly resistors. These resistors are two-terminal
devices. The metal resistors are those resistors that are used as interconnect and feed-through; they
are also 2-terminal devices. Serpentine resistor layouts are not allowed.

Units:

The length and width are specified in meters for schematic simulation. Design varia supported for
both the length and width parameters.

Calculation:

The user has two choices in determining how the final resistor configuration is calculated. The user
may request the calculation of either the resistor length or the resistor value. In both cases, the
calculated values are determined based upon a combination of the length, width, resistance value,
number of resistor segments (series or parallel), and contact resistance. The width and length are
snapped to grid, and the resistances are recalculated and updated on the component form based on
actual dimensions.

Simulation:

Subcircuit definitions are used to model the resistors

Mosfets

All mosfets in the PDK library are 4 terminals, with the body terminal explicitly connected.

Units:Length and width are in meters, with areas and perimeters in meters squared.

Calculation:
The area and perimeter parameters for the sources and drains are calculated from the width and
the number of fingers used. This calculation assumes that the drain will always have the less
capacitance (area) when there are an even number of fingers (odd number of diffusion areas). The
finger width is calculated by dividing the total width by the number of fingers.

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 Depending upon which value is entered into the form by the user, either the total width or the finger
width will be calculated using the aforementioned calculation.

Simulation:

These mosfets are netlisted as their predefined device names for simulation purposes.

Bipolar Transistors

All BJT’s in the PDK library are 3 terminal.

Units:

Only fixed size devices are allowed. A cyclic is used to enter the desired size.

Calculation:

The area is calculated from the emitter size cyclic.

Simulation:

These BJT’s are netlisted as their predefined device names for simulation purposes.

Diodes

All diodes in the PDK library are two-terminal.

Units:

Length and width are in meters. Design variables are allowed for Length and Width entries.

Calculation: The area is calculated from the width and length entered.

Simulation: These diodes are netlisted as their predefined device names for simulation

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 11 Supported Devices

Mosfets

· nmos1v - 1.2 volt nominal Vt NMOS transistor

· nmos1v_3 - 1.2 volt nominal Vt NMOS transistor with Inherited Bulk
Node
· nmos1v_hvt - 1.2 volt high Vt NMOS transistor
· nmos1v_hvt_3 - 1.2 volt high Vt NMOS transistor with Inherited
Bulk Node

· nmos1v_iso – 1.2 volt isolation NMOS transistor

· nmos1v_nat – 1.2 volt native NMOS transistor
· nmos2v – 2.5 volt nominal Vt NMOS transistor

· nmos2v_3 – 2.5 volt nominal Vt NMOS transistor with Inherited

Bulk Node
· nmos2v_nat – 2.5 volt native NMOS transistor

· pmos1v – 1.2 volt nominal Vt PMOS transistor

· pmos1v_3 – 1.2 volt nominal Vt PMOS transistor with Inherited Bulk
Node
· pmos1v_hvt – 1.2 volt high Vt PMOS transistor
· pmos1v_hvt_3 – 1.2 volt high Vt PMOS transistor with Inherited
Bulk Node
· pmos2v – 2.5 volt nominal Vt PMOS transistor
· pmos2v_3 – 2.5 volt nominal Vt PMOS transistor with Inherited Bulk
Node
. resnwsti - N-Well resistor under STI
. resnwsti_3 - N-Well resistor under STI with Inherited
Bulk Node.

Resistors

resnsndiff - N+ diffused resistor w/o silicide

resnsndiff_3 - N+ diffused resistor w/o salicide with Inherited

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 Bulk Node

resnspdiff - P+ diffused resistor w/o salicide

resnspdiff_3 - P+ diffused resistor w/o salicide with Inherited

Bulk Node

ressndiff - N+ diffused resistor w/i salicide

ressndiff_3 - N+ diffused resistor w/i salicide with Inherited

Bulk Node

resspdiff - P+ diffused resistor w/i salicide

resspdiff_3 - P+ diffused resistor w/i salicide with Inherited

Bulk Node

resnwoxide - N-Well resistor under OD

resnwoxide_3 - N-Well resistor under OD with Inherited

Bulk Node

resnsnpoly - N+ Poly resistor w/salicide

resnsnpoly_3 - N+ Poly resistor w/salicide with Inherited

Bulk Node

resnsppoly - P+ Poly resistor w/salicide

resnsppoly_3 - P+ Poly resistor w/salicide with Inherited

Capacitor

nmoscap1v – 1.2v Nmos cap

nmoscap1v3 – 1.2v Nmos cap with bulk node

pmoscap1v – 1.2v Pmos cap

pmoscap1v3 – 1.2v Pmos cap with bulk node

nmoscap2v – 2.5v Nmos cap

nmoscap2v3 – 2.5v Nmos cap with bulk node

pmoscap2v – 2.5v Pmos cap

pmoscap2v3 – 2.5v Pmos cap with bulk node

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 Bipolars

· vpnp2 - 1.2 volt Vertical substrate PNP 2x2

· vpnp5 - 1.2 volt Vertical substrate PNP 5x5

· vpnp10 - 1.2 volt Vertical substrate PNP 10x10

· npn - Bipolar NPN with variable emitter area

. pnp - Bipolar PNP with variable emitter area

Diodes

pdio – 1.2 volt P+/nwell diode

ndio - 1.2 volt N+/psub diode

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 12 Views provided

The following table explains the use of the cellviews provided as part of this PDK:

symbol Used in Composer schematics

spectre Simulation / netlisting view for the Spectre & UltraSim
schemati simulator
c Simulation / netlisting view for all simulators;
hspiceD Mixed-mode and logic resistors use schematic to call other
simulator resistor views. It is used to implement series and
parallel features in those resistors.
Simulation / netlisting view for the Hspice simulator
Mosfets

· Four terminals (D, G, S, B)

· symbol, spectre, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells)

Resistors

· Three terminals (PLUS, MINUS, B) for diffused resistors

· Two terminals (PLUS, MINUS) for poly and metal resistors

· Symbol, schematic, auLvs, auCdl, ivpcell, layout (Pcells)

· Resistors called in schematic views include views for all simulators, symbol, spectre, hspiceD,
auLvs, auCdl, ivpcell

Capacitor

· Three terminals ( really four -- S/D overlapped) (G, D/S, B) for mos caps

· Symbol, spectre, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells)

Diodes

· Two terminals (PLUS, MINUS)

· symbol, spectre, hspiceD, auLvs, auCdl, ivpcell, layout (Pcells)

Bipolars

· Three terminals (C, B, E)

· symbol, spectre, hspiceD, auLvs, auCdl, ivpcell,

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 13 CDF parameters

Mosfets

Model Name - spectre model name (non-editable)

Multiplier - number of Parallel MOS devices Length

(M) - gate length in meters

Total Width (M) - gate width in meters (sum of all fingers) Finger Width - width of each gate
finger/stripe Fingers - number of poly gate fingers/stripes used in layout

Threshold – finger width at which to apply device folding of the layout

Apply Threshold – button to apply threshold or not

Gate Connection – allow shorting of multi-fingered devices and addition of contact heads to gate
ends

S/D Connection – allow shorting of sources and/or drains on multi-finger devices S/D Metal
Width – width of metal used to short sources/drains with the layouts or can be entered manually if

“Edit Area & Perim” is checked.S/D Metal Width – width of metal used to short sources/drains

Switch S/D – source is defined as left-most diffusion region and alternating regions to the right.
Pins are not automatically permuted and can be switched using this parameter

Bodytie Type – None, Detached, or Integrated (butting source)

· For Detached, user may select Left, Right, Top, and/or Bottom to specify the located of bodyties.
Selection of all four creates a guardring

· For Detached, the user may specify Tap Extension (in microns) which sets the distance from the
bodytie to the device. Maximum distance is 100 microns

· For Integrated, the user may select Left or Right for a device with an odd number of fingers (1, 3,
5, …). The user may select Left and Right for an even fingered device

Edit Area & Perim – allow Drain/Soure area and periphery be entered manually for simulation

Drain diffusion area, etc. – several simulation parameters are presented. The area and perimeter
parameters are calculated and netlisted in accordance with the layouts or can be entered
manually if “Edit Area & Perim” is checked.

DEPARTMENT OF ECE, JBREC 25

 Resistors

Model Name – Spectre model name (non-editable)

Segments – number of series or parallel segments for a resistor Segment Connection – cyclic field
used for series or parallel segments

Calculated Parameter – radio button that determines whether resistance or Length is the calculated
value when instantiating a new resistor device

Resistance – total resistance value equal to the sum of body resistance, contact resistance, end
resistance, and grain resistance Segment Width – resistor segment width in meters Segment
Length – resistor segment length in meters

Effective Width – effective resistor segment width in meters

Effective Length – effective resistor segment length in meters

Left Dummy – boolean value used to place a dummy resistor strip on the left side of the main
resistor

Right Dummy – boolean value used to place a dummy resistor strip on the right side of the main
resistor

Contact Rows – integer number of contact rows

Contact Columns – integer number of contact columns

Show Tap Params – boolean value allowing the user to set the visibility of the resistor tap
properties

Left Tap – boolean value used to place a resistor tap on the left side of a device

Right Tap – boolean value used to place a resistor tap on the right side of a device

Top Tap – boolean value used to place a resistor tap on the top side of a device

Bottom Tap – boolean value used to place a resistor tap on the bottom side of a device

Tap Extension – float values to set where the left, right, top, and bottom taps would be to its
original placements.

Sheet Resistivity – sheet rho value for body of resistor (non-editable)

End Resistance – resistance value for any salicided area near the contact heads in a non-salicided
resistor (non-editable)

Contact Resistance – resistance value for the contact heads of a particular resistor (non-
editable)

DEPARTMENT OF ECE, JBREC 26

 Grain Resistance – constant resistance value for any salicided area near the contact heads in a non-
salicided resistor (non-editable)

Delta Width – resistor width process variation value in meters (non- editable) Model Name -
spectre model name (non-editable)

Multiplier - number of Parallel MOS devices

Calculated Parameter - Calculated parameter cyclic (capacitance, length, width)

Capacitance – total capacitance

Length (M) - gate length in meters

Total Width (M) - gate width in meters (sum of all fingers)

Finger Width - width of each gate finger/stripe

Fingers - number of poly gate fingers/stripes used in layout

Gate Connection – allow shorting of multi-fingered devices and addition of contact heads to gate
ends

S/D Connection – allow shorting of sources and/or drains on multi-finger devices S/D Metal
Width – width of metal used to short sources/drain

• For Detached, user may select Left, Right, Top, and/or Bottom to specify the located of bodyties.
Selection of all four creates a guardring
• For Detached, the user may specify Tap Extension (in microns) which sets the distance from the
bodytie to the device. Maximum distance is 100 microns
• For Integrated, the user may select Left or Right for a device with an odd number of fingers (1, 3, 5,
…). The user may select Left and Right for an even fingered device

Area capacitance – Capacitance per unit area used in parameter calculations (non-editable)

Fringe capacitance – Fringe Capacitance of perimeter used in parameter calculations (non-

editable)

Temp rise from ambient, etc. – several simulation parameters are presented.

DEPARTMENT OF ECE, JBREC 27

 Model name Model name used in simulation

Device Area Emitter area in microns squared

(noneditable)

Model name Model used for simulation name

Choices are 'area' , 'width' or

Calculate Parameter
'length'

Device Area Calculated junction area in meters

squared (non-editable)

Length (M) Diode length in meters

Width (M) Diode width in meters

Periphery of junction Calculated junction periphery in

meters
(non-editable)

Multiplier Number of Parallel Diode devices

14 Model Setup

This PDK supports the Cadence Spectre, Ultrasim, and AMS, circuit simulators, including corner
modeling of the MOSFETs.

The following model sections are defined in the

<pdk_install_directory>/models/spectre/gpdk090.scs file.

Section

NN

FF

SS

FS

SF

DEPARTMENT OF ECE, JBREC 28

 15 Techfile Layers
Cadence will provide a standard display setup, and will not support desired changes to the
display. The custome is free to modify the display.drf file used on-site to achieve any desired
display.

CDS GDS GDS CDS CDS Description

# # type name purpose
2 1 0 Oxide drawing Oxide
4 24 0 Oxide_thk drawing Thick Oxide
6 2 0 Nwell drawing Nwell
10 3 0 Poly drawing Poly
11 18 0 Nhvt drawing N+ high Vt
12 4 0 Nimp drawing N+ implant
13 23 0 Phvt Drawin P+ high Vt
g
14 5 0 Pimp drawing P+ implant
15 52 0 Nzvt drawing Native Nmos
16 72 0 SiProt drawing Salicide Blocking
18 19 0 Nburied drawing N buried
20 6 0 Cont drawing Contact
30 7 0 Metal1 drawing Metal1
32 8 0 Via1 drawing Via1
34 9 0 Metal2 drawing Metal2
36 10 0 Via2 drawing Via2
38 11 0 Metal3 drawing Metal3
40 30 0 Via3 drawing Via3
42 31 0 Metal4 drawing Metal4
44 32 0 Via4 drawing Via4
46 33 0 Metal5 drawing Metal5
48 34 0 Via5 drawing Via5
50 35 0 Metal6 drawing Metal6
52 37 0 Via6 drawing Via6
54 38 0 Metal7 drawing Metal7

DEPARTMENT OF ECE, JBREC 29

 56 39 0 Via7 drawing Via7
58 40 0 Metal8 drawing Metal8
60 41 0 Via8 drawing Via8
62 42 0 Metal9 drawing Metal9
30 7 1 Metal1 pin Pin purpose
34 9 1 Metal2 pin Pin purpose
38 11 1 Metal3 pin Pin purpose
42 31 1 Metal4 pin Pin purpose
46 33 1 Metal5 pin Pin purpose
50 35 1 Metal6 pin Pin purpose
54 38 1 Metal7 pin Pin purpose

58 40 1 Metal8 pin Pin purpose

62 42 1 Metal9 pin Pin purpose
30 7 3 Metal1 label Label purpose
34 9 3 Metal2 label Label purpose
38 11 3 Metal3 label Label purpose
42 31 3 Metal4 label Label purpose
46 33 3 Metal5 label Label purpose
50 35 3 Metal6 label Label purpose
54 38 3 Metal7 label Label purpose
58 40 3 Metal8 label Label purpose
62 42 3 Metal9 label Label purpose
30 7 4 Metal1 net Net purpose
34 9 4 Metal2 net Net purpose
38 11 4 Metal3 net Net purpose
42 31 4 Metal4 net Net purpose
46 33 4 Metal5 net Net purpose
50 35 4 Metal6 net Net purpose
54 38 4 Metal7 net Net purpose
58 40 4 Metal8 net Net purpose
62 42 4 Metal9 net Net purpose
DEPARTMENT OF ECE, JBREC 30
 71 7 2 Metal1 slot Slot purpose
72 9 2 Metal2 slot Slot purpose
73 11 2 Metal3 slot Slot purpose
74 31 2 Metal4 slot Slot purpose
75 33 2 Metal5 slot Slot purpose
76 35 2 Metal6 slot Slot purpose
77 38 2 Metal7 slot Slot purpose
78 40 2 Metal8 slot Slot purpose
79 42 2 Metal9 slot Slot purpose
80 25 0 Psub drawing P substrate
82 22 0 DIOdummy drawing Recognition layer for diodes
84 21 0 PNPdummy drawing Recognition layer for pnp
86 20 0 NPNdummy drawing Recognition layer for npn
88 17 0 IND2dummy drawing Recognition layer for inductor
90 16 0 INDdummy drawing Recognition layer for inductor
92 15 0 BJTdum drawing Recognition layer for vpnp
93 84 0 Cap3dum drawing Recognition layer for moscap
94 13 0 Resdum drawing Recognition layer for resistor
95 36 0 Bondpad drawing Recognition layer for bondpad
96 12 0 Capdum drawing Recognition layer for moscap
97 14 0 CapMetal drawing Recognition layer for moscap
98 71 0 ResWdum drawing Recognition layer for resistor
99 75 0 M1Resdum drawing Recognition layer for metal res
100 76 0 M2Resdum drawing Recognition layer for metal res
101 77 0 M3Resdum drawing Recognition layer for metal res
102 78 0 M4Resdum drawing Recognition layer for metal res
103 79 0 M5Resdum drawing Recognition layer for metal res
104 80 0 M6Resdum drawing Recognition layer for metal res
105 81 0 M7Resdum drawing Recognition layer for metal res
106 82 0 M8Resdum drawing Recognition layer for metal res
107 83 0 M9Resdum drawing Recognition layer for metal res
DEPARTMENT OF ECE, JBREC 31
 108 60 0 VPNP2dum drawing Recognition layer for vpnp
109 61 0 VPNP5dum drawing Recognition layer for vpnp
110 62 0 VPNP10dum drawing Recognition layer for vpnp
114 70 0 IND3dummy drawing Recognition layer for inductor
115 74 0 ESDdummy drawing Recognition layer for esd

Table2: Techfile Layers

DEPARTMENT OF ECE, JBREC 32

 16 Virtuoso XL

The standard Cadence Virtuoso XL design flow will be implemented. This includes basic
connectivity of connection layers, wells, and substrate, and symbolic contacts. The M factor will
be used for device instance multiplier - there will be no conflict with the parameter used in cell
operation. Names will be displayed on the layout views to aid in schematic-layout instance
correlation. Auto- abutment of MOSFET devices is supported. Pin permuting of MOSFET and
Resistor device is also supported. The skill pcell layouts are compiled into the PDK.

The users should follow the guidelines listed below for layout design:

The VirtuosoXL tool requires a separate license for operation.

Users obtain maximum leverage from the PDK by doing schematic driven layout in the Virtuoso
XL environment. This flow will produce a correct by design layout. The Virtuoso Custom Router
(VCR) can be used to finish the unconnected interconnect in the layout.

The VCR rules file for the target process is provided with the PDK.

Abutment is currently supported only for MOS transistors.

Note, abutment will work only on schematic driven layouts.

Schematic Driven Layout is recommended over Netlist Driven Layout.

NOTE: Skill pcell source code is not included in the PDK kit.

DEPARTMENT OF ECE, JBREC 33

 17 Diva Decks

These decks can be found in the extracted PDK directory tree in the ‘diva’ directory. A link to the
Diva decks is also located under the ‘libs.cdb/gpdk090’ and the ‘libs.oa22/gpdk090’ directory.

Diva DRC

Those files are based on the design rules outlined in the design rule manual. The files are:

· divaDRC.rul

Diva Extract

The DIVA Extract rule decks, divaEXT.rul

Diva LVS

The parameters checked in LVS, divaLVS.rul, include:

· MOS Devices - type, length and combination of width, "m" factor

· Resistors - type, width, and length

· Diodes - type, area, "m" factor

· BJT’s - type, emitter area, "m" factor

DEPARTMENT OF ECE, JBREC 34

 18 Assura Decks

Cadence has developed the Assura DRC, LVS, and RCX rule files from the documentation provided.

These decks can be found in the extracted PDK directory tree in the directory:

· assura

Assura DRC

The Assura DRC file provided is named

· drc.rul

Assura ANTENNA

The Assura Antenna file provided is named

· antenna.rul

Assura LVS

The Assura LVS files provided are located in the pv/assura directory and named

· extract.rul

· compare.rul

Assura RCX

The Assura RCX files provided are located in the following directory

· assura/rcx - Directory where Assura RCX files are provided

DEPARTMENT OF ECE, JBREC 35

 Chapter 5 - DESIDN METHODOLOGY AND RESULT
5.1. Dynamic Logic
Dynamic logic is a form of digital logic design where the circuit functionality relies on the
charging and discharging of capacitors. Unlike static CMOS logic, which uses both PMOS and
NMOS transistors in pull-up and pull-down networks, dynamic logic uses clocking mechanisms for
operation.

Key Features:

· Uses pre-charge and evaluation phases controlled by a clock signal.

· Smaller transistor count compared to static CMOS logic, leading to higher speed and smaller area.

· Operates faster due to reduced capacitance and no need for static power dissipation.

Working Principle:

· Pre-charge Phase: The clock signal (CLK) is low, and the output node is pre-charged to a high
voltage (V_DD) through a PMOS transistor.

· Evaluation Phase: When CLK goes high, the NMOS pull-down network evaluates the input logic and
discharges the output node if necessary.

Advantages:

· High speed due to fewer transistors and reduced capacitance.

· Compact layout, saving silicon area.

Disadvantages:

· Sensitive to noise due to charge sharing.

· Requires a clock, introducing power and complexity overhead.

· Cannot hold a logic state without refreshing.

Applications:

Logic programming ,digital electronics.

5.2 CMOS Domino Logic

MOS Domino Logic is a variation of dynamic logic designed to address some limitations of
pure dynamic logic. It uses an inverter at the output of each dynamic logic stage to prevent
cascading errors.

DEPARTMENT OF ECE, JBREC 36

 Structure:

· Combines dynamic logic with an inverter stage.

· The dynamic logic block consists of a pre-charge PMOS transistor, a clock signal, and an NMOS
evaluation network.

Operation Phases:

· Pre-charge Phase: Similar to dynamic logic, the output node is pre-charged to V_DD.

· Evaluation Phase: The evaluation network discharges the output node based on the logic inputs.
The inverter ensures the output is valid and prevents charge leakage.

Advantages:

· Eliminates cascading charge sharing issues.

· Provides higher speed than static logic.

Limitations:

· Increased power consumption due to clocking and dynamic node charging.

· Logic must be non-inverting due to the inverter stage at each stage.

Applications:

· High-speed and low-power designs in microprocessors and digital signal processors (DSPs).

5.3 Hybrid Logic

Hybrid Logic combines different types of logic (static CMOS, dynamic CMOS, transmission
gates) to achieve better performance, lower power, or specific functionality.

Key Features:

· Leverages the benefits of multiple logic families.

· Suitable for applications where neither static nor dynamic logic alone is optimal.

Example Design:

· A logic circuit may use static CMOS for non-critical paths to minimize power consumption and
dynamic logic for critical paths requiring high speed.

Advantages:

· Optimized power-delay product.

· Tailored designs for specific applications.

DEPARTMENT OF ECE, JBREC 37

 Challenges:

· Increased design complexity.

· May require more careful clocking and synchronization.

5.4 Transmission Gate Logic

Transmission Gate (TG) Logic utilizes a combination of NMOS and PMOS transistors to act as
bidirectional switches. It provides excellent logic flexibility and low power consumption.

Fig 2: Transmission Gate Logic Circuit and Symbol

Structure:

· NMOS Transistor: Passes strong logic '0' but weak '1'.

· PMOS Transistor: Passes strong logic '1' but weak '0'.

· Combination: Both transistors operate in parallel to pass strong logic levels in either direction.

Applications:

· Multiplexers, latches, and flip-flops.

· Low-power and low-area designs.

Advantages:

· Low resistance for both logic '0' and '1'.

· Eliminates the need for separate pull-up/pull-down networks.

Limitations:

· Requires complementary clock signals for operation.

· Increased parasitic capacitance compared to static logic.

DEPARTMENT OF ECE, JBREC 38

 5.5 PASS TRANSMISSION LOGIC-Based Multiplexer (MUX)
Pass Transmission Logic Gate-Based Multiplexers use transmission gates as switches to select
one of several input signals based on a select line.

Fig 3: Pass Transmission Logic

Example: 2:1 MUX

· Inputs: A, B (data), S (select signal).

· Logic Function: Output Y = A when S = 0 and B when S = 1.

Design:

· Two transmission gates controlled by the select signal (S) and its complement (S').

· When S = 0, the first gate passes input A to the output.

· When S = 1, the second gate passes input Bto the output.

Advantages:

· Compact design with low transistor count.

· Suitable for low-power and high-speed applications.

Applications:

· Data selection in communication systems.

· Configurable logic in FPGAs.

DEPARTMENT OF ECE, JBREC 39

 RESULTS

Fig 1: 1 Bit Hybrid Full Adder Scematic Diagram

The XOR gate is implemented using transmission gates, which provide low resistance and fast
switching characteristics.

• Logical Function: S= A B Cin

• Two 2x1 Multiplexers for Carry Output:

• The carry logic (Cout) is derived using two pass transistor-based multiplexers.

Logical Function:

• Cout = (A •B) + (Cin • (A B))

• First multiplexer computes (A # B) using A and B.

• Second multiplexer selects between A • B and Cin based on the intermediate XOR result.

• Inputs and Outputs:

• Inputs: A, B, Cin

• Outputs: S, Cout

DEPARTMENT OF ECE, JBREC 40

 Fig 2 : 1-Bit Hybrid Full Adder Schematic Waveform

Waveform Description

1.Inputs:

•A, B, and Cin are digital signals toggling between logic 0 (low voltage) and logic 1 (high voltage).

•The testbench drives these inputs in all possible combinations (000, 001, 010, … 111) over time.

2.Outputs:

• S (Sum): The XOR function of A, B, and Cin (S = A B Cin).

• Cin (Carry): Generated based on the hybrid logic, ensuring correct addition functionality (C in =
(A.B) + (Cin (A B))).

• Input Changes:

• At t = 0 ns: A = 0, B = 0, Cin = 0.

• At t = 10 ns: A = 1, B = 0, Cin} = 1.

• Output Waveforms:

• S = 0 at t = 0 ns, transitions to S = 0 at t = 10.02 ns.

• Cin = 0 at t = 0 ns, transitions to Cin = 1 at t = 10.1

DEPARTMENT OF ECE, JBREC 41

 Fig 3 : Time Propagation Delay for carry rise time

Steps to Measure Rising Delay for Carry (Cout)

1. Simulation Setup:

• Configure the inputs (A, B, and Cin) in the testbench to toggle through all combinations.

• Focus on transitions where Cout moves from 0 to 1.

2. Run Transient Analysis:

• Use Cadence Virtuoso to perform a transient simulation.

• Set the time step small enough to capture precise transitions (e.g., <0.01\ ns).

3. Measure the Delay:

• Identify the input transition (e.g., A, B, or Cin) that triggers the rising edge of C_out}.

• Measure the time when the input rises to 50% of Vdd (logic high threshold).

• Measure the time when Cout reaches 50% of Vdd.

• Calculate the propagation delay:

tpd^rise = C_out\rise - input_rise

DEPARTMENT OF ECE, JBREC 42

 Fig 4 : Time Propagation Delay for carry fall time

Steps to Measure Rising Delay for Carry (Cout)

1. Simulation Setup:

• Configure the inputs (A, B, and Cin) in the testbench to toggle through all combinations.

• Focus on transitions where Cout moves from 0 to 1.

2. Run Transient Analysis:

• Use Cadence Virtuoso to perform a transient simulation.

• Set the time step small enough to capture precise transitions (e.g., <0.01\ ns).

3. Measure the Delay:

• Identify the input transition (e.g., A, B, or Cin) that triggers the rising edge of C_out}.

• Measure the time when the input rises to 50% of Vdd (logic high threshold).

• Measure the time when Cout reaches 50% of Vdd.

• Calculate the propagation delay:

tpd^fall = Cout\fall - tpd input\_fall

DEPARTMENT OF ECE, JBREC 43

 Fig 5 : Time Propagation Delay for sum fall time

The fall time propagation delay for the Sum output is defined as:

TPDF_Sum = t_S_fall - t_input\_fall

Where:

• t_S_fall: Time when the Sum output (S) falls to 50% of V_dd.

• t_{input\fall: Time when the triggering input signal (e.g., A, B, or Cin) falls to 50% of V_dd.

DEPARTMENT OF ECE, JBREC 44

 Fig 6 : Time Propagation Delay for sum raise time

The fall time propagation delay for the Sum output is defined as: TPDF_Sum = t_S_fall -
t_input\_fall

Where:

• t_S_raise: Time when the Sum output (S) raise to 50% of V_dd.

• t_input\raise: Time when the triggering input signal (e.g., A, B, or Cin) falls to 50% of V_dd.

DEPARTMENT OF ECE, JBREC 45

 Fig 7: Power Consumption

The hybrid full adder uses:

• A single XOR gate for the Sum (S) output.

• Two multiplexers for the Carry (C_out) output.

• A combination of Transmission Gate (TG) and Pass Transistor Logic (PTL).

Power consumption characteristics:

• Average Power: 3.258 µW (micro-watts) at 90nm.

• Reasons for Low Power:

• Fewer transistors (24 compared to 28 in traditional designs).

• Efficient logic design reduces switching activity and dynamic power.

• Optimized transistor sizes for minimal leakage.

DEPARTMENT OF ECE, JBREC 46

 Chapter 6 - ADVANTAGES AND DISADVANTAGES
6.1 Advantages
1. Low Power Consumption:

The incorporation of dynamic clocking significantly reduces static power dissipation by ensuring
minimal leakage during idle states.

Efficient use of transistors in the hybrid logic design minimizes overall power usage.

2. High-Speed Operation:

The domino CMOS logic style enhances the circuit's speed by leveraging faster transitions and reduced
delay in critical paths.

Compact routing and optimized layout contribute to improved propagation delay.

3. Reduced Area Utilization:

The hybrid logic approach results in fewer transistors compared to traditional full adder designs,
leading to a smaller silicon footprint.

This compact design is beneficial for integration into larger systems-on-chip (SoC).

4. Scalability:

The design can be easily scaled to create multi-bit adders or integrated into complex arithmetic units
without significant performance degradation.

5. Improved Signal Integrity:

The use of dynamic clocking ensures reliable signal transitions, reducing the likelihood of glitches.

The NOT gate at the output aligns the design with domino CMOS logic, improving output stability.

6. Technology Node Compatibility:

The design is compatible with advanced technology nodes (e.g., 45nm and below), making it suitable
for modern VLSI applications.

7. Flexibility in Applications:

The low-power, high-speed characteristics make the design suitable for battery- operated devices, high-
performance processors, and other powersensitive applications.

DEPARTMENT OF ECE, JBREC 47

 6.2 Disadvantages
1. Complex Clocking Mechanism:

Dynamic clocking requires precise timing and synchronization, which can add design complexity.

Any clock signal mismatch may lead to erroneous behavior or increased power consumption.

2. Leakage Current in Domino Logic:

While domino CMOS logic enhances speed, it is susceptible to leakage currents during precharge and
evaluation phases.

Mitigating this requires additional circuit techniques, which could slightly increase area and power.

3. Limited Noise Immunity:

Domino CMOS logic can be more sensitive to noise, especially in low-supply- voltage scenarios.

This may require additional buffers or shielding mechanisms, increasing design overhead.

4. Fabrication Challenges:

Implementing such a design at smaller technology nodes demands precise control over parasitics and
layout rules, which can be challenging during fabrication.

5. Dependency on External Tools:

The design relies heavily on advanced EDA tools for simulation, layout, and verification. o Access to
such tools may be a constraint for small-scale developers or educational institutions.

6. Cost of Dynamic Clocking:

The dynamic clocking mechanism might require additional clock generation circuits, slightly
increasing power and area overhead.

7. Suitability for Specific Applications:

While the design is optimized for speed and power, it may not be the best choice for ultra-low-
frequency applications where static power is less critical.

DEPARTMENT OF ECE, JBREC 48

 Chapter 7 - Conclusion
The design and implementation of the 1-bit full adder using hybrid logic, incorporating a 2x1
multiplexer and dynamic clocking with domino CMOS logic style, have demonstrated promising
results in terms of power efficiency, speed, and scalability.

Key Outcomes
1. Power Efficiency:

o The integration of dynamic clocking significantly reduced static power dissipation, making the
design ideal for low-power applications such as portable devices and embedded systems.

2. High-Speed Performance:

o The domino CMOS logic style ensured faster transitions and reduced propagation delay,
contributing to high-speed operation suitable for modern VLSI applications like processors and
data-intensive systems.

3. Compact Design:

o The hybrid logic approach minimized the transistor count, leading to reduced area utilization while
maintaining functional accuracy and reliability.

4. Scalability and Versatility:

o The design's modular nature allows for easy scaling to multi-bit adders and integration into complex
arithmetic units, enabling its use in diverse digital systems.

Applications
The proposed design finds applications in:

 High-performance processors

 Low – power embedded systems  Battery-operated

Challenges and Future Scope

While the design achieves significant improvements, challenges such as noise sensitivity in domino
logic and clock synchronization in dynamic clocking require further exploration.

In future work, additional optimization techniques, such as adaptive clocking and enhanced noise
mitigation strategies, can be incorporated to improve robustness.

Moreover, extending the design to higher technology nodes and evaluating its performance in real-
world scenarios will further validate its effectiveness and reliability.

DEPARTMENT OF ECE, JBREC 49

 Final Remarks
The proposed 1-bit full adder design is a step forward in achieving the balance between low power
and high-speed requirements in modern VLSI systems. Its innovative use of hybrid logic and
dynamic clocking sets a foundation for further advancements in digital circuit design, aligning with
the demands of energy-efficient and high-performance systems.

References
1. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective,
2nd ed., Pearson Education, 2003.

2. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill Education, 2016.

3. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 4th ed.,
McGraw-Hill,

2014.

4. R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 3rd ed., Wiley-IEEE Press, 2010.

5. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press,
2012.

6. M. Pedram and J. Rabaey, Power Aware Design Methodologies, Springer, 2002.

7. K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current mechanisms and leakage reduction
techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp.
305–327, Feb. 2003.

8. T. Sakurai, “Low-power CMOS design through VLSI design and process integration,” IEEE
Transactions on Electron Devices, vol. 45, no. 5, pp. 774–779, May 1998.

9. S. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Springer, 2005.

10. S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol. 19, no. 4, pp.

23–29, Jul. 1999.

11. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Prentice Hall, 2009.

12. A. P. Chandrakasan, W. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits,

Wiley-IEEE Press, 2000.

13. H. P. Nguyen, D. Wang, and S. M. Kang, “Domino CMOS logic circuits for highspeed
applications,” in Proceedings of the IEEE International Symposium on Circuits and Systems, May
1994, pp. 381–384.

14. M. Morris Mano and M. D. Ciletti, Digital Design, 5th ed., Pearson, 2012.
DEPARTMENT OF ECE, JBREC 50
 15. N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed.,
Pearson Education, 2011.

16. A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design: Circuits and Systems, Springer,
1995.

17. J. Cong and Y. Zhang, “Thermal-driven multilevel routing for 3-D ICs,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 973–986, Jun. 2008.

18. A. Srivastava and M. Sarrafzadeh, Power Minimization in IC Design: Principles and Applications,
Cambridge University Press, 2004.

19. H. F. Dadgour and K. Banerjee, “Design and analysis of hybrid NEM-CMOS circuits for ultra low-
power applications,” IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2610–2620, Nov.
2009.

20. A. Islam and M. Hasan, “Leakage power characteristics in 45 nm MOSFET device,” International
Journal of Computer Applications, vol. 14, no. 1, pp. 37–42, Jan.

2011.

21. C. L. Seitz, “System timing,” in Introduction to VLSI Systems, C. Mead and L. Conway,

22. S. Dey and M. Potkonjak, “Nonlinear constraint transformation for synthesis and optimization of
domino CMOS circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.
8, no. 4, pp. 471–476, Aug. 2000.

23. D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital Integrated

Circuits, 3rd ed., McGraw-Hill Education, 2003.

24. K. Bernstein et al., “Design and CAD challenges in sub-90 nm CMOS technologies,” in
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Nov. 2003,
pp. 129–136.

25. A. Goel and P. Kumar, “Power-delay-area optimized full adder design using hybrid logic,” in
Proceedings of the International Conference on VLSI Design, Jan. 2009, pp.

101–106.

26. H. Kawaguchi and T. Sakurai, “A reduced clock-swing flip-flop (RCSFF) for 63% power
reduction,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 807–811, May 1998.

27. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University

DEPARTMENT OF ECE, JBREC 51

 28. M. A. Elgamel and M. I. Elmasry, “Low-power dynamic logic techniques for high- performance
digital circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 4,
pp. 439–449, Apr. 2004.

29. C. H. Kim, J. Keane, and K. Roy, “Hybrid domino logic with low switching noise and reduced
leakage power for wide fan-in gates,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 13, no. 5, pp. 509–522, May 2005.

30. T. Kuroda, “Low-power CMOS design in the era of sub-1-V operation,” in Proceedings of the
IEEE/ACM International Conference on Computer-Aided Design, Nov. 1997, pp. 281–288.

31. M. Anis and M. Elmasry, “Dynamic and leakage power reduction in deep submicron ICs,” IEEE
Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 9, pp.
510–516, Sep. 1999.

32. E. Seevinck, P. W. J. G. Rent, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,”
IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748–754, Oct. 1987.

33. J. Hu, Y. C. Cheng, and T. Zhang, “Low-power domino logic circuit design for ultra- high-speed
applications,” in Proceedings of the IEEE International Symposium on Circuits and Systems, May
2010, pp. 581–584.

34. M. Alioto and G. Palumbo, “Power estimation in CMOS logic circuits: Modeling and optimization,”
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 48, no. 9, pp. 1004–1015, Sep.
2001.

35. M. T. Bohr, “Interconnect scaling-the real limiter to high-performance ULSI,” International

Electron Devices Meeting Technical Digest, pp. 241–244, Dec. 1995.

36. S. Borkar et al., “Parameter variations and impact on circuits and microarchitecture,” in

Proceedings of the IEEE/ACM Design Automation Conference, Jun. 2003, pp. 338– 342.

37. K. Itoh, M. Horiguchi, and H. Tanaka, “Low-power memory design,” in Low-Power Electronics
Design, CRC Press, 2004, pp. 105–150.

38. D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron,” in Proceedings of the
IEEE International Conference on Computer-Aided Design, Nov. 1998, pp. 203– 211.

39. H. Mahmoodi and K. Roy, “Self-precharging flip-flop (SPFF): a new class of lowpower flip-flops,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 733–745,
Dec. 2002.

40. R. Geiger, P. Allen, and N. Strader, VLSI Design Techniques for Analog and Digital Circuits,
McGraw-Hill, 1990.

DEPARTMENT OF ECE, JBREC 52

 41. T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and its applications to CMOS
inverter delay and other formulas,” IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584–
594, Apr. 1990.

42. K. Roy and S. Prasad, Low-Power CMOS VLSI Circuit Design, Wiley, 2000.

43. S. P. Khatri and K. Gulati, Advanced Techniques in Logic Synthesis and Optimization, Springer,
2011.

44. E. Vittoz, “Low-power design: Ways to approach the limits,” in Proceedings of the IEEE
International Solid-State Circuits Conference, Feb. 1994, pp. 14–18.

45. M. Forshaw and M. Schneider, “Parallel computing in nanoelectronics,” IEEE Transactions on

Nanotechnology, vol. 4, no. 1, pp. 12–22, Jan. 2005.

46. M. T. Bohr, “MOS scaling: Transistor challenges for the 21st century,” Proceedings of the IEEE,
vol. 85, no. 4, pp. 486–504, Apr. 1997.

47. L. Benini and G. De Micheli, “Networks on chips: A new SoC paradigm,”

Computer, vol. 35, no. 1, pp. 70–78, Jan. 2002.

48. W. Wolf, “Hardware-software co-design of embedded systems,” Proceedings of the IEEE, vol. 82,
no. 7, pp. 967–989, Jul. 1994.

49. C. Tokunaga and D. Blaauw, “Adaptive circuits for dynamic variation tolerance,” in

Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 2009, pp.

302–303.

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