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Sequential Logic 2

The document discusses the design of asynchronous and synchronous decade counters, highlighting the need for a 4-bit counter to count from 0 to 9. It explains how to implement a reset mechanism using a combinational circuit that triggers when the counter reaches the binary state 1010. Additionally, it describes the operation of synchronous counters where all flip-flops receive a common clock signal and outlines the conditions for toggling each flip-flop based on the states of others.

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6 views

Sequential Logic 2

The document discusses the design of asynchronous and synchronous decade counters, highlighting the need for a 4-bit counter to count from 0 to 9. It explains how to implement a reset mechanism using a combinational circuit that triggers when the counter reaches the binary state 1010. Additionally, it describes the operation of synchronous counters where all flip-flops receive a common clock signal and outlines the conditions for toggling each flip-flop based on the states of others.

Uploaded by

sahngwain795
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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We’ve seen the design of 3-bits and 4-bits asynchronous counters and how the operate.

A 3-bit
counter will count from 0 to 7, similarly a 4-bit counter will count from 0 to 15 but what about
designing a counter capable of only counting from 0 to 5 or from 0 to 9(decade counters), how do
we go about such?

Design of an Asynchronous Decade Counter.

To design a decade counter, let’s first come up with the state diagram and the truth table and see
if we can notice any patterns.

We can’t use 3 flipflops only to implement this system since the maximum count will be 7 but we
need a maximum count of 9, so we are going to use 4 flipflops. What we need is for the counter to
begin afresh from zero or in order words to reset after it reaches 9, for us to achieve this, we’ll
need to consider the next state after 9 and use a combinational circuit to trigger the reset when it
reaches at that state.

The next binary count after 1001 is 1010, with an AND gate, we can conveniently use 1010 to
trigger the Reset which will reset the flipflops back to its initial state, 0000.
Design of Synchronous Counters

Unlike Asynchronous counters, all the flipflops in a synchronous counter receive their clock signal
simultaneously and from a common source. You might be wondering how then will this work
since all flipflops will be activated at once, but remember, for a JK flipflop to work as a counter,
it has to be in its toggle state and that is only possible when both inputs are held at logic 1. Let’s
examine the truth table for a 4-bit synchronous counter and see if we can discover any patterns.

If you noticed, the flipflop labeled D toggles on every clock


cycle, while the flipflop labeled C only toggles when D is
HIGH, similarly the flip labeled B only changes state when
C and D are HIGH and that labeled A only changes state
when B, C and D are all HIGH as well.

With this information, we can develop a combinational


circuit that will set both JC and KC to HIGH only when QD
is high, JB and KB to HIGH only when QC and QD are HIGH
and JA and KA to HIGH only when QD, QB and QC are all
HIGH

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