EXPERIMENT – 1

Aim:-
To study and verification of the truth tables of logic gates.
Apparatus Required:-
Digital lab kit, single strand wires,

Theory:-
Logic gates are idealized or physical devices implementing a Boolean function, which it
performs a logical operation on one or more logical inputs and produce a single output.
Depending on the context, the term may refer to an ideal logic gate, one that has for instance
zero rise time and unlimited fan out or it may refer to a non-ideal physical device.
The main hierarchy is as follows:-
1. Basic Gates
2. Universal Gates
Basic Gates
1. AND gate:- Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement:-
Input Input Output
A B
1 1 1
1 0 0
0 1 0
0 0 0

2. OR gate:- Function of OR gate is to give output true when one of the either inputs
are true .In the remaining case output becomes false. Following table justify the
statement
Input Input B Outpu
A t
0 0 0
0 1 1
1 0 1
1 1 1

1. NOT gate: - Function of NOR gate is to reverse the nature of the input .It
converts true input to false and vice versa. Following table justifies the statement
Input Output
1 0
0 1
Universal Gates

1. NAND gate: - Function of NAND gate is to give true output when one of the
two provided input are false. In the remaining output is true case. Following
table justifies the statement :-
Input A Input B Output
1 1 0
1 0 1
0 1 1
0 0 1

2. NOR gate: - NOR gate gives the output true when both the two provided input
are false. In all the other cases output remains false. Following table justifies the
statement:-
Input A Input B Output
1 1 0
1 0 0
0 1 0
0 0 1

3. OR gate: - The function of XOR gate is to give output true only when both the inputs are true.
Following table explains this:-
Input A Input B Output
1 1 0
1 0 1
0 1 1
0 0 0

Result:-
All gates are verified. Observed output matches theoretical concepts.
 EXPERIMENT - 2

Aim:-Implement of the given Boolean function using logic gates in both SOP and POS forms
Two input SOP - A.B + A’.B’
Two input POS: - (A+B) (B+C) (A+C’)

Apparatus required:-Digital Lab Kit, Single Strand Wires, Connecting Wires.

Theory:-
a) SOP: - It is the Sum of product form in which the terms are taken as 1. It
is denoted in the K-map expression by sigma (∑) A.B. + AB’

Logic Circuit Of this expression:-

Truth Table for this SOP expression

A B A’ B’ A.B A.B’ F= AB + AB’

0 0 1 1 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 1 0 0 1 1 1

POS: - It is the product of the sums form in which the terms are taken as 0. It is denoted in
the K-Map expression by the Sign pie (π) (A+B) (B+ C) (A + C’)

Circuit Diagram

B OR Y

AND AND
C OR

CNOT

NOT OR
 Truth Table foe POS expression

A B C A+B B+C A+C’ Y= (A+B)(B+C)(A+C’)

0 0 0 0 0 1 0
0 0 1 0 1 0 0
0 1 0 1 1 1 1
0 1 1 1 1 0 0
1 0 0 1 0 1 0
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1

Result:-Hence, given Boolean Expression is implemented by the Logic Gates.

i.e. (i) A.B + A.B’

(ii) (A+B) (B+C) (A+C’)

 EXPERIMENT - 3

Aim: -Verification of state tables of

1 . R-S flip-flop
2. J - K flip-flop
3. T Flip-Flop
4. D Flip-Flop
Using NAND and NOR gates.
Apparatus:- IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate).

Theory: - In case of sequential circuits the effect of all previous inputs on the outputs is
represented by a state of the circuit. Thus, the output of the circuit at any time depends upon its
current state and the input .These also determine the next state of the circuit . The relationship
that exists among the inputs, outputs, present states and next states can be specified by either
the state table or the state diagram.

State Table:- The state table representation of a sequential circuit consists of three sections
labelled present state next state and output . T he present state designates the state o f f lip - f
lops before t h e occurrence of a clock pulse. The next state shows the states of flip - flops after
the clock pulse, and the output section lists the value of the output variables during the present
state.

Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop. It can store either
0or 1. Flip-flops are classifieds according to the number of inputs.

R-S Flip-Flop:-The circuit is similar to SR latch except enable signal is replaced by clock
pulse

Logic Diagram

Characteristic table for S-R flip flop

D Flip-Flop: -The modified clocked SR flip-flop is known as D-flip-flop. From the

truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable
state when the inputs are same and high. In many practical applications, these input
conditions are not required. These input conditions can be avoided by making then
complement of each other.
 Logic Diagram

Characteristic table for D flip flop

J-K Flip-Flop:- In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS
flip-flop circuit may be re-joined if both inputs are 1 than also the outputs are complement of
each other.

Logic Diagram Characteristic table for J-K flip flop

T Flip-Flop:-T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip -
flop. Both the J K inputs of the J K flip-flop are held at logic 1 and the clock signal continuous to
change
Logic Diagram Characteristic table for T flip flop

RESULT:- Study and verified truth-tables of various flip-flops.

 EXPERIMENT -4

Aim:- Implementation and verification of decoder, de-multiplexer and encoder, using logic
gates.

Apparatus: - Digital trainer kit, 7432 IC, 7404 IC, 7411 IC and Connecting wires.

Theory:-
Decoder:-A decoder is a multi- input and multi output combinational logic circuit which
converts coded input into coded outputs, where the input and output coded are different.

Logic Diagram of 2 to 4 decoder

Truth table of 2 to 4 decoder

ENCODER:-An encoder is a combinational logic circuit .It is the reverse of a decoder

function. It has 2 to the power n input and n output lines. An encoder accepts an active level
on one of its inputs representing a digit such as a decimal /octal digit and it convert to coded
output.
Encoder is used at the starting stage to encode the message into a unique code. Encoder
encodes different types of messages into various forms. In Digital Circuits it encodes a
decimal value into a binary word. The encoded binary word has number of bits associated
with it. The number of bits depends upon the decimal value which is being encoded. For
example in case of decimal values ranging from 0 to 7 the number of bits required to encode
these values is 3.
 Logic diagram of encoder

Truth table of encode

De- multiplexers:-.A demultiplexer sometimes abbreviated d-mux, is a circuit that has one input
and more than one output. It is used when a circuit wishes to send a signal to one of many devices.
This description sounds similar to the description given for a decoder, but a decoder is used to select
among many devices while a demultiplexer is used to send a signal among many devices.

Logic diagram of demultiplexer

RESULT:-Truth tables of Encoder, de-multiplexers and decoder are verified

 EXPERIMENT-5

Aim:-Implementation of 4x1 multiplexer, using logic gates.

Apparatus:- Digital trainer kit, AND-7411, OR-7432, NOT-7404 Gate IC, Connecting wires.
Theory:-
MULTIPLEXER:- A multiplexer (MUX) is a device that accepts data from one of many
input sources f or transmission over a common shared line. To achieve this MUX has several
data lines and a single output along with data-select inputs, which permit digital data on any of
the inputs to be switched to the output line. The logic symbol for a 1 to 4 data select or/
multiplexer is shown in Figure

Block diagram of multiplexer

The selection line s decide the number of inputs lines of particular multiplexer. If t he number
of n inputs lines is equal to 2m, the n m select lines are required to select one of the n input
line.Note that if a binary zero appears on the data-select lines then data on input line D0 will
appear on the output. Thus, data output Y is equal to D0 if and only if S1=0 and S0=0.

Y=D0.S1’.S0’ Similarly , the data output is equal to D1, D2 and D3 for y=C1.S1’.S0’,
Y=C2.S0’. S1 and Y=C3.S0.S1 respectively. Thus the total multiplexer logic expression,
formed from ORing terms i.

The implementation of this equation is as shown in figure

Logic diagram of multiplexer
 DATA SELECT INPUT INPUT

S1 S0 SELECTED

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Truth table of mux

Result:-Study of 4×1 multiplexer and verified its truth table.

 EXPERIMENT-6

Aim:- Design, and verify the 4-bit synchronous counter.

Apparatus:-

S.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 4 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

Theory:-
Synchronous counter: - A simple way of implementing the logic for each bit of an
ascending counter (which is what is depicted in the image to the right) is for each bit to
toggle when all of the less significant bits are at a logic high state. For example, bit 1
toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3
toggles when bit 2, bit 1 and bit 0 are all high; and so on.
Synchronous counters can also be implemented with hardware finite state machines.
Which are more complex but allow for smoother, more stable transitions?
Hardware-based counters are of this type and they can be implemented using the IC 7476
PIN DIAGRAM FOR IC 7476:
TRUTH TABLE:-

Input Present State Next State A B C

Up/Down Q A QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1
LOGIC DIAGRAM

State diagram

Result:-Study of 4 bit synchronous counters and verified its truth table.