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UART Protocol

The document provides a comprehensive overview of the UART (Universal Asynchronous Receiver and Transmitter) protocol, detailing its function as a half-duplex serial communication method that uses specific data frame formats including start, data, parity, and stop bits. It explains the communication process between the transmitter and receiver, emphasizing the importance of a baud rate generator for synchronization. Additionally, the document includes block diagrams and modules for project implementation in Verilog code related to UART functionality.

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Subhashini Reddy
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0% found this document useful (0 votes)
195 views17 pages

UART Protocol

The document provides a comprehensive overview of the UART (Universal Asynchronous Receiver and Transmitter) protocol, detailing its function as a half-duplex serial communication method that uses specific data frame formats including start, data, parity, and stop bits. It explains the communication process between the transmitter and receiver, emphasizing the importance of a baud rate generator for synchronization. Additionally, the document includes block diagrams and modules for project implementation in Verilog code related to UART functionality.

Uploaded by

Subhashini Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UART

EVERYTHING YOU NEED


TO KNOW !!

UART CONCEPTS
PROJECT IMPLEMENTATION
(VERILOG CODE)

Prasanthi Chanda
1. What is UART protocol ?
A set of rules and regulations is called a protocol.
UART stands for a Universal Asynchronous Receiver and
Transmitter.
UART Protocols is a serial communication with two wired
protocols.
The data cable signal lines are labelled as Rx and Tx.
Serial communication is commonly used for transmitting and
receiving the signal.
It transfers and receives the data serially bit by bit without
class pulses.

2. What Is the Frame Format of UART Protocol?


Packet
Start Bit Data Bits Parity Bits Stop Bits
(1 bit) (5 to 9 bits) (0 to 1 bit) (1 to 2 bits)
Data Frame

UART is a half-duplex protocol.


Half duplex means transferring and receiving the data but
not at the same time.
The transmitter receives the 8-bit data from input and stores
in some register.
The transmitter then adds some special bits like start bit,
stop bit and parity bit(if selected) to make the complete data
frame.
The data frame then sent out serially by the transmitter at
the predefined clock rate (baud rate).
The receiver is by default at high logic state which indicates idle state
of receiver and keeps looking for the high to low transition i.e. start
bit.
As soon as the start bit is detected, the receiver observe the start bit
for 50% of the receiving baud rate, if it is the receiver start sampling
other data bits at the middle of each bit otherwise receiver set flag for
framing error.
After detecting the 8 bit data, the receiver then looks for the parity
bit which is generated by the transmitter for the single bit error
detection.
If the parity bit is detected properly, the receiver looks for the stop bit
to stop the reception of data.
After the successful detection of stop bit the receiver line goes high
logic state to indicate idle state and start looking for the next start
bit.

3. How Does Communication Occur Between Transmitter and


Receiver in UART?
UART operates without a clock signal, relying on a predefined baud
rate for synchronization.
The transmitter serializes parallel data and appends a start bit,
optional parity bit, and stop bit to create a complete data frame.
The frame is transmitted bit by bit over the TX line.
The receiver detects the start bit to synchronize with the incoming
frame.
It sequentially reads the data bits, checks parity for errors (if enabled),
and identifies the stop bit.
The receiver then reconstructs the original parallel data by stripping
the additional bits.
Transmitter converts parallel data to serial.

Start bit added to signal the start of data transmission.

Data bits sent sequentially over the TX line.

Parity bit (optional) added for error checking.

Stop bit added to mark the end of the frame.

Receiver detects the start bit and synchronizes.

Receiver reads the data bits and checks the parity (if present).

Receiver removes start, parity, and stop bits.

Receiver reconstructs the original parallel data.

Fig.1 Flowchart representing Transmitter and Receiver


Communication in UART

3. What Is a Baud Rate Generator in UART and How Does It


Work?
The baud rate generator ensures that the transmitter and receiver
operate at a common communication speed.
It takes a high-frequency input clock signal and divides it by a
predefined divisor value.
The divisor value is chosen to match the desired baud rate (e.g., 9600,
115200 bps).
The resulting lower-frequency output clock synchronizes the timing for
data transmission and reception in UART.
Both devices must use the same baud rate for reliable communication.
4. Give the Block Diagrams of UART Transmitter and Receiver.

Fig.2 Block diagram of UART Transmitter

Fig.3 Block diagram of UART Transmitter State Machine


Fig.4 Block diagram of UART Receiver

Fig.5 Block diagram of UART Receiver State Machine


5. Give the Block Diagrams of UART Baud Rate Generator.

sel(1:0) clkout

clk

reset

Fig.6 Block diagram of UART Baud Rate Generator

PROJECT IMPLEMENTATION
DESIGN MODULE
MODULE TO DETECT START

MODULE SIPO

PARITY CHECKING MODULE


MODULE FOR STOP BIT

MODULE FOR TRANSMITTER MUX

MODULE FOR TRANSMITTER PARITY


MODULE FOR TRANSMITTER PISO

MODULE FOR TRANSMITTER TX


MODULE FOR TRANSMITTER FSM
MODULE FOR UART RX
MODULE FOR BRG
MODULE FOR RECEIVER FSM
TESTBENCH

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