Study material on “Digital Electronics” for I B.

Sc Electronics 1

COMBINATIONAL SWITCHING CIRCUITS

In this chapter we are going to study how word statements can be converted to a truth
table, simplify the equation using K map or the other technique and implement the
same using logic gates.
Basically there are two types of circuits
1. Sequential circuits.
2. Combinational circuits (also called as combinatorial switching circuits).
A sequential circuit is one in which the present state of the output condition depends
not only on the present states of the inputs but also on the previous states of the
outputs also.

A combinational switching circuit (combinatorial circuits) consists of input variables,

logic gates and output variables as shown in the block diagram below. The inputs and
outputs are two valued (either ‘1’ or ‘0’). The values of output variables depend only
on the present values of the inputs. The output doesn’t depend on the previous history
of inputs.
The input – output relationship of such a circuit is given in figure below.

x1
Z1
x2 Z2
COMBINATORIAL
CIRCUIT

Zm
xn

Z1 = f1 (x1, x2,……….xn)
Z2 = f2 (x1, x2,……….xn)
Z3 = f3 (x1, x2,……….xn)
. .
. .
. .
Zm = fm (x1, x2,……….xn)

COMBINATORIAL CIRCUIT DESIGN PROCEDURE: A problem statement

will be given for the designer. The aim is to design a combinatorial circuit using
minimum number of gates. For this, the designer should follow the following steps:
1. State the problem clearly.
2. Find out the input and output variables.
3. Use an appropriate coding to represent the inputs and outputs with Boolean
variables.
4. Assign letter symbols to represent input and output variables.
5. Obtain a truth table using the word statements of the problem.
6. Represent each output variable in the truth table on a Karnaugh map or
represent it in SOP form.
7. Obtain the simplified Boolean expression for each of the output variables.
8. Draw the logic circuit diagram corresponding to the Boolean expressions.

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Some of the examples for the combinational circuits are given in the following pages.

ADDITION CIRCUITS
1. A combinational circuit that perform the addition of 2 bits at a time is called as a
half adder. Design a combinational circuit for the above statement.

Solution: From the above definition, it is clear that there are two input variables and
two output variables. Let us assign the letters x and y for the two input variables, for
one output variable Sum as S and other output variable Carry as C. The truth table for
a half adder is as shown below.

x y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

We can see that the sum output S = = xy and carry C = xy.
The sum output is nothing but the XOR output of two inputs x and y and the carry
output is the output of a AND gate with two inputs x and y.
The circuit diagram is as shown below.

x
S
y

The same can be realised using NAND gates only which is left as an exercise for the
reader.

x
S
HA
y C

The block diagram symbol of a half adder is as shown in the second figure (above).

A combinational circuit that adds 3 bits at a time is called as a full adder. Design a
system that performs the above operation.
Solution: From the above statement, it is clear that the circuit has three inputs namely
x, y & z and two output variables (call the sum output as S and the carry output as
C). The truth table of a full adder is as shown below.

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FULL ADDER TRUTH TABLE

Input variables Output variables
x y z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The sum output S = = ….(1)

But we know that the sum output S (of a half adder) = and it can be seen
that = = = =

Hence
Hence in (1) we can write that S = …..(2)
We can write S as = (Sz) where S is the sum output of a half adder with two inputs
x and y. Hence S = xy.  S = xyz.
For the carry output C = =

= z.S + x.y…….. (3)

When we observe equation (2), it is clear that the sum output S is the output of a half
adder with two inputs as S and z, whereas S is the output of a half adder with x and y
as the two inputs as shown below.
For C, z.S is the carry output of the second half adder and x.y is the carry output of
the first half adder. Hence ORing these two gives the carry output C
NOTE: The reader is advised to obtain the K map simplification for both the sum and
carry output and realize the same using NAND gate only.
S
x S
HA1 HA2
y z.S
C
x.y
z
Note: - Since S & C were the sum and carry of a half adder, to differentiate the sum
and carry of a full adder, the notation of a full adder’s sum and carry are taken as S 
and C.

The block diagram symbol of a full adder is as shown below.

x S
y FA 
C
z

3. HALF SUBTRACTOR: A half Subtractor is a logic circuit that has two inputs x
and y and two outputs. One output is called as the Difference (and is denoted by D)

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and the other output as the Borrow (and is denoted by B). The truth table of a half
Subtractor is as shown below.
x y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

It can be seen that D = and B = . D is the output of a XOR gate with x

and y as the two inputs.
x x
D D
y
HS
y B
B

The block diagram symbol of a half Subtractor is as shown below.

CODE CONVERTERS: Code converter is a combinational circuit that accepts a

particular code at the input and generates an equivalent desired code at its output.

Problem: Design a combinational circuit that converts an 8421 code to its Excess-3
equivalent.
Solution: The block diagram of the 8421 to Xs-3 code is as shown below. The circuit
has four input variables A, B, C and D and 4 output variables w, x, y and z.

A w
B x
Input Variables Code Converter
y Output
C Circuit variables
D z

The truth table is as shown below.

Input variables Output variables

A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1

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0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0    
1 0 1 1    
1 1 0 0    
1 1 0 1    
1 1 1 0    
1 1 1 1    

The reader is advised to develop K map for each output variable and simplify it and
verify that the following are the simplified expression for the output variables.

w = A +B.D +B.C
x=
y=
z=

The logic circuit for the above set of expression is as shown below.
A B C D

Design a combinational circuit that converts

1. An 8421 code to 84 code.
2. Excess–3 code to 84 code.
3. 8421 to excess –3 code.
4. Binary to BCD (which were discussed in the theory class)
5. Excess 3 to binary. (which were discussed in the theory class).

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PARITY BIT: The condition of evenness or oddness of the number of 1s in a

binary code is referred as parity code.

PARITY BIT GENERATOR

3-bit parity generator (Odd parity system):
Let us consider a 3-bit information signal ABC that is send from the transmitter side.
While sending the signal bits (i.e., A, B and C) an error may take place (like 0
becoming 1 and vice versa). In order to detect this error, we incorporate an extra bit
called as parity bit denoted by P. If the number of 1’s in ABCP is even, then the
system is called as an even parity system and if ABCP is having odd number of 1’s,
then the system is called as odd parity system. Consider the truth table given below
which is an odd parity system.

Output
Input variables
variable
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

A Z
B Po
C
The expression for P0 = =

Let Z = . Hence = . Hence Z = (AB).

Therefore P0 = = =

NOTE: The reader is advised to get a simplified expression through K map and
realize the same using the basic gates.

4-BIT PARALLEL BINARY ADDER

It is a logic circuit that adds two 4-bits (with the possibility of a carry input) at a time
to produce 4-bit sum output and one carry output.

Consider the two 4-bit numbers A3A2A1A0 and B3B2B1B0 with say C0 =0. When we
add A0 and B0, there is a possibility of carry C 1 that has to be added to A1 and B1 and
so on…

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C3 C2 C1 C0
A3 A2 A1 A0
B3 B2 B1 B0
C4 S3 S2 S1 S0

We can see that each column is having 3 bits and hence we require a full adder
circuit to perform the addition of these 3 bits. Since we have four columns, we
require four full adder circuits to perform the above operation. The carry that is
generated by the previous column is the carry input to the next full adder.
The block circuit diagram of a 4-bit parallel binary adder is as shown below.
A3 B3 A2 B2 A1 B1 A0 B0

C2 C1
C3 FA FA
C4 FA FA
C0

S3 S2 S1 S0

DECODERS
Definition: A decoder is a combinational circuit that converts the binary
information from n input lines to a maximum of 2n unique output lines.
A decoder is a circuit that decodes (or breaks) the given code. For example, when we
apply a binary code 11(which is equivalent to 3 in decimal) to the decoder circuit, its
output with a label ‘3’ should glow. Remember, all the other outputs should go low.
2 TO 4 LINE DECODER
If we have two input lines, we can have a maximum of 2 n output lines. Consider the
block diagram of a 2 to 4 line decoder as shown below.

INPUTS OUTPUTS
D0 A B D0 D1 D2 D3
A
2 to 4 line D1 0 0 1 0 0 0
B
Decoder D2 0 1 0 1 0 0
D3
1 0 0 0 1 0
1
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The truth table of the 2 to 4 line decoder is as shown above.

Outputs D0 = , D1 = , D2 = and D3 = A.B. The circuit of a 2 to 4 line
Decoder is as shown below.
A A B B

D0

D1

D2

D3

BCD TO DECIMAL DECODER

It is a decoder circuit in which the fed BCD number is decoder into its decimal form.
It has 4 inputs A, B, C and D and 10 outputs. The block diagram of a BCD to
Decimal Decoder is as shown in next page.

A B C D
D0
D1
A
D2 D0
B D3
BCD TO D1
D4
C DECIMAL
DECODER D5
D6 D2
D
D7
D8 D3
D9
D4

D0 = , D1 = , D2 = , D3 = , D4 = D5 ,
D5 = , D6 = , D7 = .B.C.D, D8 = A. . , D9 = A. .D
D6

D7

D8

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D9
 Study material on “Digital Electronics” for I B.Sc Electronics 9

ENCODERS
It is a combinational circuit that is just reverse to a decoder.
Definition: (as the name indicates) An encoder is a combinational circuit that
converts an active input signal into a coded output signal.
It can have 2n input lines and n output lines.
OCTAL TO BINARY ENCODER: An octal to binary encoder codes the given octal
number (0 to 7) to its binary equivalent. Hence the circuit should have 8 input lines
(23) and hence 3 output lines. The block diagram of an octal to binary encoder is as
shown below.

D0
D1
D2 A
OCTAL TO
D3
BINARY B
D4
ENCODER
D5 C
D6
D7

The truth table of an octal to binary encoder is as shown below.

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Input variables Output variables

D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
The output 0 1 0 0 0 0 0 0 0 0 1
for A = D4 0 0 1 0 0 0 0 0 0 1 0
+D5 +D6
+D7 and for 0 0 0 1 0 0 0 0 0 1 1 B
= D2 +D3 0 0 0 0 1 0 0 0 1 0 0
+D6 +D7
and for C = 0 0 0 0 0 1 0 0 1 0 1 D1
+D3 +D5 0 0 0 0 0 0 1 0 1 1 0
+D7.
0 0 0 0 0 0 0 1 1 1 1
The circuit
diagram of octal to binary encoder is as shown below.
D0 D1 D2 D3 D4 D5 D6 D7

MULTIPLEXER (DATA SELECTOR OR MUX)

Definition: A digital multiplexer is a combinational circuit that selects binary
information from one of the many input lines and directs it to a single output line.
It is also called as MANY TO ONE circuit. In general a MUX can have 2 n input lines
and to direct any one of the 2n input lines to the output line, we require at least ‘n’
control lines.
4 TO 1 LINE MUX
The block diagram of a 4 to 1 line MUX is as shown below.

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I0
4 TO 1 LINE

Input lines
I1
MUX Y Output line
I2
I3
S0 S1

Control lines

The functional truth table of the above MUX is as shown below (Observe that the
truth table of a MUX is also called as a function table)

The output SOP equation for Y = I0 + S 1 I1 S0 S1 Output Y

+ S0I2 + S1S0I3
0 0 I0
The circuit diagram of the above equation is as
0 1 I1
realised below.
1 0 I2
1 1 I3

I1
Y

I2

I3

The reader is advised to design an 8 to 1 line MUX.

REALISATION OF BOOLEAN FUNCTION USING MUX
In this section, we are going to realise the given Boolean expression using a 4 to 1 line
MUX.
Consider the Boolean expression Y =  (0, 1, 5, 7). Draw a table as shown below.
Here B and C are selected as the two control signals and A as the input signal.
Now encircle the cells with numbers 0, 1, 5
and 7 and hence we find that I 0 = , I1 = A IO I1 I2 I3
+ = 1, I2 = 0 (since there are no
0 1 2 3
encirclements) and I3 = A
A 4 5 6 7
Inputs to the MUX 1 0 A

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DE – MULTIPLEXER (D – MUX)
A I0
1 I1
4 to 1 line
MUX Y
0 I2

I3
S1 S0

B C
Definition: A digital de-multiplexer is a combinational circuit that steers (connects)
the one and only one input information line to one of the several output lines.
It is reverse to a MUX. Here we can have only one input line and 2 n output lines. To
steer the input line to one of the 2n lines, we need to have n control signals.
1 TO 2 LINE DE – MUX

1 TO 2 X
I LINE
DE – MUX Y

S
X
S
Output X = .I and Y = I.S I
The circuit diagram for the above equation is as shown. S Y
1 TO 4 LINE DE – MUX

W
1 to 4 line
I X
DE-MUX
Y
Z W

X
S1 S0 I
Y
The outputs for W, X, Y and Z is as written below.
W = I. , X = I. S0, Y = I.S1. and Z = I.S1.S0
The above is realised as shown below. Z

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NOTE:
1. Convert 153 to its excess 3 equivalent. 153 = 0001 0101 0111.The excess 3
equivalent is found as follows:
0001 0101 0111
+ 0011 0011 0011
0100 1000 0110
2. Convert the binary 1101 to its excess 3 equivalent.
The decimal equivalent of 1011 is 13. The BCD equivalent of 13 = 0001 0011.
The excess 3 equivalent of 0001 0011 = 0100 0110.
REFERENCES:
1. Digital Computer Design - V Rajaram & T Radhakrishnan – PHI edition– 3 rd
edition.
2. Digital fundamentals – Thomas L Floyd – Pearson Edition.
3. Digital Logic & Computer Design – M Morris Mano PHI 2nd edition
4. Digital principles and applications – Albert Paul Malvino & Donald Leach 4 th
McGraw Hill edition.
5. Digital electronics – William H Gothmann PHI 2nd edition.
6. Digital Principles and design – Donald D Givone - Tata McGraw Hill
edition.
7. Digital Systems, Principles and applications – Ronald J Tocci & Neal S
Widmer – PHI – EEE 8th edition.
PREPARED BY:
K.U.KIRAN,
DEPT OF ELECTRONICS,
ST ALOYSIUS COLLEGE,
MANGALORE – 03.

Dept. of Electronics, St Aloysius College