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Flip Flops Notes

Flip flops are fundamental components in digital electronics, functioning as memory elements created using logic gates. There are four main types: S-R Flip Flop, D Flip Flop, and J-K Flip Flop, each with unique designs and applications in electronic circuits. They are crucial for implementing feedback circuits and enhancing the design of Random Access Memory (RAM).

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7 views6 pages

Flip Flops Notes

Flip flops are fundamental components in digital electronics, functioning as memory elements created using logic gates. There are four main types: S-R Flip Flop, D Flip Flop, and J-K Flip Flop, each with unique designs and applications in electronic circuits. They are crucial for implementing feedback circuits and enhancing the design of Random Access Memory (RAM).

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sarthakmhatre21m
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FLIP FLOPS 1

Basic Flip Flops in Digital Electronics

Flip flops are actually an application of logic gates. With the help of Boolean logic
you can create memory with them. Flip flops can also be considered as the most
basic idea of a Random Access Memory [RAM]. When a certain input value is
given to them, they will be remembered and executed, if the logic gates are
designed correctly. A higher application of flip flops is helpful in designing better
electronic circuits.
The most commonly used application of flip flops is in the implementation of a
feedback circuit. As a memory relies on the feedback concept, flip flops can be
used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop


2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop

1. S-R Flip Flop


The SET-RESET flip flop is designed with the help of two NOR gates and also
two NAND gates. These flip flops are also called S-R Latch.

• S-R Flip Flop using NOR Gate


The design of such a flip flop includes two inputs, called the SET [S] and RESET
[R]. There are also two outputs, Q and Q’. The diagram and truth table is shown
below.
2

• S-R Flip Flop using NAND Gate


The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

• Clocked S-R Flip Flop


3

It is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state.
This problem can be overcome by using a bistable SR flip-flop that can change
outputs when certain invalid states are met, regardless of the condition of either the
Set or the Reset inputs. For this, a clocked S-R flip flop is designed by adding two
AND gates to a basic NOR Gate flip flop. The circuit diagram and truth table is
shown below.

2. D Flip Flop
The circuit diagram and truth table is given below.
4

D flip flop is actually a slight modification of the above explained clocked


SR flip-flop. From the figure you can see that the D input is connected to the S
input and the complement of the D input is connected to the R input. The D input
is passed on to the flip flop when the value of CP is ‘1’. When CP is HIGH, the
flip flop moves to the SET state. If it is ‘0’, the flip flop switches to the CLEAR
state.
3. J-K Flip Flop
The circuit diagram and truth-table of a J-K flip flop is shown below.
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A J-K flip flop can also be defined as a modification of the S-R flip flop. The only
difference is that the intermediate state is more refined and precise than that of a
S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop.
The letter J stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the
complement state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q
= 0, it switches to Q=1.

The circuit includes two 3-input AND gates. The output Q of the flip flop is
returned back as a feedback to the input of the AND along with other inputs like K
and clock pulse [CP]. So, if the value of CP is ‘1’, the flip flop gets a CLEAR
signal and with the condition that the value of Q was earlier 1. Similarly output Q’
of the flip flop is given as a feedback to the input of the AND along with other
6

inputs like J and clock pulse [CP]. So the output becomes SET when the value of
CP is 1 only if the value of Q’ was earlier 1.
The output may be repeated in transitions once they have been complimented for
J=K=1 because of the feedback connection in the JK flip-flop. This can be avoided
by setting a time duration lesser than the propagation delay through the flip-flop.
The restriction on the pulse width can be eliminated with a master-slave or edge-
triggered construction.

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