A Novel Design Methodology to Optimize The Speed

and Power of the CNTFET Circuits

Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
Dept. of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
[email protected]

Abstract— Carbon nanotubes with their superior properties measured in current per tube reflecting the structure of the
have proved to be a potential alternative device to CMOS. In CNTFET as an array of the carbon nanotubes that have the
this paper, circuit optimization methods for high performance constant spacing and fixed diameter.
and low power CNFEFT circuit are proposed. The proposed
design methods for CNTFET circuit address how to decide the Efforts have been made in recent years on modeling and
optimum CNTFET parameters such as pitch, diameter, number simulating CNT related devices such as CNTFET [2] and
of CNTs (Carbon Nano Tube), optimum fan-out factor and CNT interconnects [3] to evaluate the potential performance
logical efforts to deliver the minimum power-delay product. The at the device level. However, the dynamic performance of a
proposed method makes it possible to accomplish 56% dynamic complete circuit system, consisting of more than one
power reduction and 22% less delay by optimizing the pitch,
number of CNTs, fan-out factor, and logical efforts compared to
CNTFETs and interconnects, differs from that of a single
the circuits that are not optimized and screening effects are device. In this paper, from physical design perspective for the
ignored. application of CNTFET, a practical and effective circuit
design method for CNTFET is proposed and its legitimacy is
proved by extensive simulations. Circuit characteristics are
I. INTRODUCTION
compared with the case that the screening effect is ignored.
The Carbon Nanotube Field Effect Transistor (CNTFET),
one of the promising new devices, avoids most of the
fundamental limitations of the traditional silicon MOSFETs.
With ultra long (~1μm) mean-free-path (MFP) for elastic
scattering, ballistic or near ballistic transport can be obtained
with intrinsic CNT under low voltage bias to achieve the
ultimate device performance [1][2][3]. A typical structure of
MOSFET-like CNTFET device is illustrated in Figure 1. The
channel region of the CNT is undoped while the other regions
Figure 1. CNTFET Structure.
are heavily doped, thus acting as the source/drain extended
region and/or interconnects between two adjacent devices.
II. ANLYSIS OF CNTFET DEVICE PARAMETERS
Carbon nanotubes are high-aspect-ratio cylinders of carbon
atoms. The electrical properties of a single wall carbon A. Channel capacitance and current vs pitch
nanotube (SWNT) offer a potential for molecular-scale
electronics. A typical semiconducting single-wall carbon
nanotube is 1.4nm in diameter with 0.6eV bandgap and
bandgap is inversely proportional to the diameter). Recent
carbon nanotube field effect transistors (CNFETs) have a
metal carbide source/drain contact [6] and a top gated
structure (Fig. 1) with thin gate dielectrics [7]. The contact
resistance and the subthreshold slope of the CNTFET are
comparable to those of silicon MOSFET. While silicon FET’s Figure 2. Three CNTs in array and electrode
current drive is typically measured in current per unitary The charges on the CNTs #2 and #3 will affect the
device width (e.g. μA/μm), the current of CNTFET is electric field and electrostatic potential profile between the

978-1-4244-4480-9/09/$25.00 ©2009 IEEE 1130

electrode #0 and the CNT #1, and the coupling capacitance gate width Wmin and the number of tubes N, the gate width can
C01 in Figure 2 is given by; be approximated as
Q1 Q1 (1) Wgate = Max(Wmin, N·pitch) (3)
Co1 = =
V1 V0 + Vadj The widths of the source and drain almost approach Wgate
and therefore, the contact resistances and capacitances are
Vadj increase as the pitch decreases, and the capacitance C01 determined by the widths.
located in the middle of CNTs decrease. Figure 3 shows the
channel capacitance of the CNTFET and the parameters that Table 1. η versus pitch (VDD= 0.6V, diameter = 2nm,
determine the gate capacitance. The Cgc_e is the capacitance channel length = 32nm) .
of the CNT located in the edge of the CNTFET device and Pitch(nm) 4 6 8 10 12 14 16 18 20
the Cgc_m is the capacitance of the CNT located in the middle η 0.59 0.73 0.82 0.88 0.91 0.93 0.95 0.96 0.96
of the CNTFET device.
C. Parameters for CNTFET Circuit Design
1) Threshold voltage
By adjusting the diameter, the threshold voltage can be
controlled and is given by [4]
Eg
3 aVπ
Vth ≈ = (4)
2e 3 eDCNT
where Vπ ( ~3.033 eV) is the carbon π-π bond energy in the
Figure 3. Three CNTs in parallel to the gate
tight bonding model [4] and e is the unit electron charge and
Figure 4 shows the capacitances Cgc_e and Cgc_m for DCNT is diameter of CNT. In this paper, Vth = 0.2V is used
different pitches. As mentioned previously, the pitch of a CNT because of the smallest value of PDP is attained by
is also a parameter that determines the CNTFET current. simulation
The gate to mid and edge CNT coupling capacitance [F]

2.80E-010 2) Gate capacitance

2.60E-010

2.40E-010 The gate capacitance affects the speed and power

Cgc_e
consumption, and is determined based on device size. The
2.20E-010

2.00E-010
Cgc_m
1.80E-010

1.60E-010
CNTFET gate capacitance (Cgate,CNT) consists of three
1.40E-010

1.20E-010
components [8]: the gate to channel capacitance (Cgch,CNT), the
1.00E-010 gate outer fringe capacitance (Cfr,CNT), and the coupling
capacitance between the gate and the adjacent contacts
8.00E-011

6.00E-011

0 2 4 6 8 10 12
Pitch(nm)
14 16 18 20 22
(Cgtg,CNT). Because the portion of the Cfr,CNT is much smaller
than Cgtg,CNT and Cgch,CNT , it can be ignored . Therefore, the
Figure 4, The gate to middle and edge CNT channel total gate capacitance can be expressed as
capacitances
C gate ,CNT ≈ {η ( N − 2 ) + 2}C gc _ e ,CNT ⋅ + C gtg ⋅ Wg (5)
If there are more than N (N>2) tubes in the CNTFET, then
the total channel capacitance is given by (N-2) Cgc_m +2Cgc_e ,
and it can be expressed in terms of Cgc_e as (η(N-2)+2)Cgc_e , 3) Fan-out factor for minimum delay
and the total channel capacitance Cgch is, therefore, given by; Its optimum value can be found by differentiating the
minimum delay expression [9] by the number of stages and
Cgch = Cgc_1 if N=1 setting the result to 0, i.e.
=2Cgc_e if N= 2 N
F ln F (6)
=(η(N-2)+2)Cgc_e if 2<N (2)
γ +N F − = γ + f − f ln f = 0
N
where N is the number of tubes, Cgc_1 is the channel where γ(Cint/Cg) a proportionality factor that is only a
capacitance of the CNTFET with only one tube, and η is the function of technology and is determined by the pitch and the
ratio between Cgc_e and Cgc_m , i.e. η =(Cgc_e/Cgc_m). η is gate width, (that also determines the intrinsic capacitance) , F
determined based on the pitch, supply voltage, channel length, denotes the overall effective fan-out of the circuit and f
and the diameter of the CNT, and η is shown in Table 1 (found denotes the effective fan-out factor. For CNTFETs, the value
based on HSPICE simulation) for different pitches. of γ can be found by HSPICE simulation. It is a function of
the pitch and the number of tubes. Using the simulated value
B. CNTFET area of γ, the optimum fan-out factor f is given by 4.
The total area of the CNTFET is determined by the width
of the gate (as for the device structure of Fig. 1). The gate III. DESIGN METHODOLOGY FOR CNTFET CIRCUIT WITH
width can be determined by the pitch. By setting the minimum PERFORMANCE OPTIMIZATION

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 1) Optimum number of CNTs for minimum delay. the gate capacitance to accomplish the delay are computed as
For driving a load in CMOS technology, the ratio between y=45∙(3/2)/5.3=12.7 and x= (12.7+12.7)∙4/2/5.3=9.6 .
the load and driver’s gate capacitances is often used. In x

CMOS, this ratio is almost same as the ratio x

y
45
(Wload/Lload)/(Wdriver/Ldriver). However for CNTFET, as shown A 8
x
in a previous section, the gate capacitance is not proportional y B
45

to the number of carbon nanotubes. This is caused by the

screening effect that affects the gate capacitance and the Figure 5. Example of circuit for logical effort
current. Therefore, it is important to choose a right number of
tubes in each driver and load. As an example, a buffer chain To establish the number of tubes for each gate can be found
is considered; in this circuit, the ratio between the gate using the Equation (8). Assume the first stage inverter gate
capacitance of the i-th inverter and the next stage is has 8 tubes and its pitch is 4nm, then the 3-input NAND gate
in the next stage can be found by using η = 0.6 for 4nm pitch,
{η ( N i − 2 ) + 2}C gc _ e ≈ f {η ( N i −1 − 2 ) + 2}}C gc _ e (7) f = 9.6/8 = 1.2 , and Ni-1 = 8. Therefore, the number of tubes
of the three input NAND gate is 12. Similarly, the number of
Equation (8) is obtained by solving Equation (7) for Ni. tubes for the third stage 2-input NOR gate can be found to be
⎛ f 1⎞ (8) 16.
N i = f ⋅ N i −1 + 2⎜1 − f + − ⎟ = f ⋅ N i −1 + K ( f ,η )
⎜
⎝ ηη ⎟⎠
where ⎛ f 1⎞
K ( f ,η ) = 2⎜⎜1 − f + − ⎟⎟ IV. SIMUATION RESULTS
⎝ η η⎠
The technology parameters for the CNTFETs are used as an
Ni denotes the number of carbon nanotubes of the i-th default of CNTFET HSPICE library[4] except diameter and
stage, and f is the effective fan-out factor. K(f, η) is a function pitch, gate width.
of f and η and the values are determined by the pitch and the
number of tubes in the CNTFET. Based on γ obtained from 1) Delay
extensive simulations, the optimum value of f turns out to be To verify the proposed design methodology to find the
4 and the value of η can be found from Table 1. number of tubes for each logic stage, an inverter chain is
designed and its delay has been simulated. Each CNTFET in
2) Logical effort for combinational logic. the inverters has the same pitch (4nm) and fan-out factor
The so-called logical effort of a gate denotes the (f=4) except for the fourth stage which is the load. The load
additional input capacitance of a gate to deliver the same has 64 tubes and 20nm pitch. Theoretically, the number of
output current as an inverter. The logical effort is an tubes for the second stage must be 8 from Equation (8).
important figure of merit, because it is used to reduce the path However, since an approximation was used when deriving
delay of a circuit[9] [10]. Equation (8), the exact number of tubes for the second stages
can be different from 8. Extensive simulations were
Table 2.Logical Effort for CNTFET and CMOS performed for different numbers of tubes near the value of 8
Lo gical Efforts
N um ber of
Inverter N AN D NOR for the second stage to find the optimum delay. The optimum
Inputs
C N FET CM O S C N FET CM O S number of tubes is found in the same way for the third stage.
1
2 3/2 5/4 3/2 7/4
3 4/2 6/4 4/2 10/4
4 5/2 7/4 5/2 13/4
n (N -1)/2 (N + 3)/4 (N -1)/2 (3n+ 1)/2

In a CNTFET, the P-type and N-type have almost the same

carrier mobility unlike CMOS technology (which is 3:1).
Therefore, the sizes of the P-type and N-type CNTFETs can
be the same in inverter. Table 2 shows the logical efforts for Figure 6. Inverter chain delay for 6 cases.
CNTFET and 32nm CMOS gates. Based on the CNTFET
logical effort, different measures (such as the path logical Six different cases are simulated for different number of tubes
effort, the path electrical effort, the path effort, the path in each stage. The number of tubes in each stage is denoted as
branching effort, the path delay and the path effort delay) can (1st,2nd,3d,4th). From case 1 to case 6, the numbers of tubes are
be found [10]. Let’s consider the circuit in Figure 5 as an (1,4,16,64), (1,6,24,64), (1,7,32,64), (1,8,36,64), (1,9,40,64),
example. The logical effort can be used to reduce the delay of (1,10,44,64), respectively. For Case 1, the screening effect is
this CNTFET based circuit. The path logical effort is given not considered. For all cases, the first stage inverter has only
by G= (1)∙(4/2)∙(3/2)∙(1)=12/4, the path electrical effort is one tube (corresponding to a minimum sized inverter), the
H=5, the path branching effort is B=3 x 2=6, the path effort is number of tube for the second stage (i.e. (4,6,7,8,9,10)) was
^
F=GBH =152, and f = 3 F = 5 . 3 . As the parasitic delay is chosen near the theoretical value (8), and the number of tubes
P=2+3+2=7 the minimum path delay is D=3∙5.3+7=23, and for the third and the fourth inverters are determined based on

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Equation (8). The delay of the inverter chain is shown in V. CONCLUSIONS
Figure 6. These results show that either case 3 or case 4 In this paper, a new design methodology for CNTFET
provides the best delay and this value is close to the value was proposed. The characteristics of CNTFET is different
obtained from Equation (8). Therefore, simulation has shown from conventional bulk CMOS. These characteristics are
that the proposed methodology is effective in finding the explained in this paper and a design method for CNTFET
optimum number of CNTs for minimum delay. Figure 7 circuits was investigated based on the characteristics. By
shows the results of the case where the logical effort choosing the diameter form chirality, the threshold voltages
approach is used to find the optimum gate size for the circuit can be determined. The channel capacitance and current vary
shown in Figure 5. Two cases are considered. The first case is as pitch changes because of screening effects. With these
the practical one with the screening effect (pitch 4nm, η=0.6) factors, the gate capacitance was approximated with number
and the other corresponds to the ideal case in which there is of tubes in device and optimum fan-out factor was found.
no screening effect (pitch 20nm, η=1). In both cases, the Using those parameter, logical effort was calculated and the
numbers of tubes are calculated from Equation (8). From minimum delay of multistage circuit topology was analyzed.
these results, a 48% difference between ideal and non-ideal To prove the effectiveness of the proposed circuit design
cases is found, which shows that the minimum delay can be method, simulations have been performed using HSPICE
achieved even with the presence of the screening effect by with CNTFET library [4][5], and their results demonstrate
using the proposed methodology to find optimum pitch and that the proposed design methods are effective and practical.
fanout, diameter, number of CNTs (Carbon Nano Tube). In order to design the CNTFET circuit, circuit designer have
to take into account the diameter at certain chirality, pitch,
and the optimum number of tubes. Considering all those
factors, this paper proposed the design methods to find the
optimum pitch, diameter, number of CNTs (Carbon Nano
Tube), optimum fan-out factor, and proved their legitimacy. It
will be a good reference for the future design methodology
for any other emerging technologies.
VI. REFERENCES
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