Power Supply

Design Seminar
Tips, tricks and advanced
applications of linear regulators

Author
Stephen Ziel
Agenda
• Linear regulator (LDO) overview
• LDO tips and tricks:
o Noise
o Power-supply rejection ratio (PSRR)
o Thermal performance
o Transient performance near dropout
• Advanced LDO applications:
o Parallel LDOs using ballast resistors
o Constant current regulation
o Multiple-input single-output (MISO) LDOs

2
LDOs vs. switching converters
• Power converter types: Switching Converter
o Switching converters: switches IN Switching Low Pass OUT
Elements Filter
are either on or turned off
o LDO: pass element is always VIN Feedback ILOAD
on and Control

• LDO GND

o Pros: cheap, simple, quiet

o Cons: efficiency, temperature Linear Regulator
IN Pass OUT
VIN Element ILOAD
VOUT × IOUT
Efficiency η = VIN × IOUT + IQ Feedback
VIN – VOUT = 100 mV
and Control

GND

3
What is the structure of an LDO?
Key LDO characteristics:
• Dropout voltage (VDO)
• Power dissipation (PD) and relationship to
IN Pass OUT
temperature rise of the LDO
FET
CIN
VIN
Reference
RNR
+
CFF COUT ILOAD • Noise
Error
NR
Amplifier
RTOP o Intrinsic noise (en) is dominated by the
FB
CNR
- noise of the internal reference and error
RBOTTOM
amplifier
o PSRR measures how much noise from the
GND
input couples into the output through the
LDO
• Quiescent current (IQ)
• Stability
• Turnon time 4
Noise fundamentals 10 Hz-100 kHz
µVRMS

• LDO noise measurements:

o Noise spectral density (µV/√Hz) 100 Hz-100 kHz
o Total (integrated) output noise (µVRMS) µVRMS

o An industry standard to compare

different LDOs against one another
• Integrated output noise is typically
measured from 10 Hz to 100 kHz
o 100 Hz to 100 kHz was also sometimes
used in the past
o For accurate noise comparison, be sure
the measurements are using the same
frequency range

5
What conditions do not affect intrinsic noise
Output current (∆IOUT)* Input voltage (∆VIN) Output capacitance**
(∆COUT)

*For ultra-low-IQ devices, ILOAD **Very high values of COUT may

may affect noise affect noise
6
What conditions affect intrinsic noise
Output voltage (∆VOUT)
IN Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM

GND

VOUT has no effect when placing an LDO in unity gain feedback

IN Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error
Amplifier
FB
-
CNR

GND

7
 What conditions affect intrinsic noise
IN
Feedforward capacitor (∆CFF)
Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM

GND

CFF has no effect when placing an LDO in unity gain feedback

IN Pass OUT
FET
CIN
VIN
Reference
RNR
+
CFF COUT ILOAD • CFF creates a short across RTOP in the mid-
Error
NR
Amplifier band frequency
CNR
-
FB
• The error amplifier operates closer to unity
gain feedback within the mid-band
frequency range
GND
8
What conditions affect intrinsic noise
Noise reduction (NR)
capacitor (∆CNR)

IN Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM

GND

• The NR capacitor and internal NR resistor form a

low-pass filter
• This low-pass filter removes noise from the
reference voltage before the error amplifier

9
PSRR
PSRR represents the ability of the LDO to filter input-
voltage changes
VIN(AC)
PSRR = 20 × log
VOUT(AC)

Region 1: PSRR of the reference and the resistor-

capacitor filter
Region 2: Open-loop gain of the error amplifier
Region 3: Parasitic capacitance of the field-effect VIN(AC) VOUT(AC)
transistor and the output capacitor and associated
IN
parasitic (capacitive divider) Pass
FET
OUT

VIN CIN
• The smaller the parasitic capacitor, the less the VIN Reference
RNR
+
CFF COUT ILOAD
NR Error RTOP
AC-couples to VOUT Amplifier
FB
• The larger the COUT, the more noise shunted to GND CNR
-
ESL
• Associated equivalent series inductance (ESL) can RBOTTOM
also impact PSRR performance GND
10
What conditions do not affect PSRR
Bias voltage (VBIAS) Output voltage (VOUT) Output capacitance (∆COUT)

No impact if VBIAS is above Small impact at low frequency Small impact at high frequency
the minimum value

11
What conditions affect PSRR
How small is VIN-VOUT?

IN Pass
VOUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM
VOUT = 0.8 V
GND

• When the pass field-effect transistor (FET) is in the

saturation region, you can maintain the necessary
gain (large VDS)
• When the pass FET enters the linear region, you
cannot maintain the necessary gain (small VDS)
12
What conditions affect PSRR
Output current (∆IOUT)
IN Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM

GND

• As the load increases, at some point the pass FET

will enter the metal-oxide semiconductor triode
region and the gain of the pass FET will be
degraded for the same VDS

13
What conditions affect PSRR
NR capacitor (∆CNR)

IN Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM

GND

• The PSRR of VREF itself affects the PSRR of the

LDO
• Adding a low-pass filter increases the PSRR of
VREF

14
 What conditions affect PSRR
IN
Feedforward capacitor (∆CFF)
Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error RTOP
Amplifier
FB
-
CNR
RBOTTOM

GND

CFF has no effect when placing an LDO in unity gain feedback

IN Pass OUT
FET
VIN CIN RNR CFF COUT ILOAD
Reference +
NR Error • At higher frequencies, feedback and
Amplifier
-
FB VOUT are effectively shorted by CFF,
CNR
which prevents the gain of the error
amplifier from increasing the reference
GND
noise
15
JEDEC thermal metrics
JEDEC high-k board

• TI LDO thermal metrics are

modeled using the Joint Electron Side view
Device Engineering Council
(JEDEC) high-K board in order to
easily compare devices
• The most common thermal
characteristic is the junction-to-
ambient (θJA) thermal resistance Top view
• θJA is a measure of the thermal GND fill
performance of an integrated Traces to
each pin
circuit (IC) mounted on a printed
IC
circuit board (PCB)
16
θJA: Understanding usage and limitations
Temperature (°C)
• It is possible to reduce the θJA 25% to 50% JEDEC simulation
θJA = 68.5°C/W
93.5
through good layout practices 79.8

• Good layout practices: 66.1

o Maximize the number of thermal vias within 52.4

the thermal pad to transfer heat away from 38.7
the LDO
25.0
o Maximize the PCB copper around the device

PD = VIN − VOUT × IOUT + IQ

PD ≊ VIN − VOUT × IOUT
TJ = TA + θJA × PD
EVM Measurement
θJA = 34.7 °C/W 17
Using Ψ𝐉𝐁 and Ψ𝐉𝐓 in-application
• JEDEC has defined ΨJB and ΨJT thermal
metrics to provide a more accurate way to
estimate the junction temperature from the
measured case temperature (TC) on a
PCB

TJ = TC + ΨJT × PD

TJ = 59°C + 4.5 °CൗW × 1 W = 63.5°C

18
Transient performance near dropout
• Transient performance is typically
characterized with more headroom
voltage than the dropout specification
• An LDO enters dropout when it can no
longer regulate the output voltage
o Dropout is a DC specification
• The dropout of the TPS7A14 is typically
45 mV at 1 A (25°C)

19
Parallel LDOs LDO1

IN OUT

• Benefits: LDO2

IN OUT
o Increased load current
o Reduced noise (√n) LDOn
VIN VOUT
o Improved PSRR for a given load current IN OUT

IOUT
o Improved thermal spreading
o Reduced headroom requirement (dropout)
o Reduced volume over other converters: COUT LDO1
IN OUT
typically drives the maximum system height LDO2
COUT RB

• You must use a ballast resistor to connect IN OUT

COUT RB
each LDO’s output together
LDOn
o Direct VOUT connection: Small differences in VIN
IN OUT
VLOAD

VOUT will result in one LDO turning on and COUT

ILOAD
trying to carry the load while the rest are turned
off
20
 Parallel LDOs: Fundamental equations and analysis
max VEn − min VEn
1<x<n 1<x<n
RB =
ILOAD RB1 IOUT1 RB2 IOUT2 RB3 IOUT3 RBn IOUTn ∆IMAX Maximum current
imbalance between
LDOs
n
VLOAD VE1 VE2 VE3 VEn VOUTn − VLOAD + VEn
ILOAD = ෍
R Bn
n=1
VOUT1 VOUT2 VOUT3 VOUTn
VOUTn + VEn
LDO#1 LDO#2 LDO#3 LDO#n σnn=1 − ILOAD
R Bn
VLOAD =
IMAX 1
VLOAD_REG σnn=1
R Bn

VOUTn − VLOAD VEn

Increasing the ballast Decreasing the IOUTn = +
resistance reduces R Bn R Bn
ballast resistance
the current reduces the load
imbalance (∆IMAX) regulation VLOAD_REG If RB1 =…= RBn and VOUT1 = … = VOUTn:
between LDOs

V
0 Rb ILOAD − σnn=1 REn VEn
B
IOUTn = +
n RB
21
Ballast resistor design
1206-sized
• Option 1: PCB trace resistor
o Avoid microstrip analysis; use
Institute of Printed Circuits (IPC) PCB
2221 resistors
o Include temperature rise of the PCB
trace and TG of the PCB dielectric in
the analysis
o Pros: Low production costs, high 6
temperature, will not go out of stock

Resistance (mΩ)
100%
or become obsolete 5

PD (Rated)
PCB trace
• Option 2: discrete resistor 4
o Typically 0603- or 0805-sized
3
o Review the data-sheet power
derating curve 2 100-ppm discrete resistor
0%
70 TMAX

20
50
80
-70
-40
-10

110
140
170
o Pros: Low tolerance, low parasitics,
smallest footprint TA (°C) Temperature (°C)
22
Effects of PCB impedance
• Ideally, the PCB resistance is RF1-2
significantly less than the ballast RF1 RF2
resistance
IOUT_1 RB RB IOUT_2 IOUT_1 RB RB IOUT_2
o PCB copper has a wide tolerance
• The PCB resistance (forward and VE VE VE VE
Load
return) is in series with the ballast
resistance VOUT VOUT VOUT VOUT

• When RB < 50 mΩ, the PCB resistance LDO#1 LDO#2 LDO#1 LDO#2
can meaningfully change the design RR1 RR2
RR1-2
o Conduct a post-route analysis to simulate
the PCB resistance at hot temperatures
• You must assess two paths (a) (b)

23
Parallel LDO calculator
Step 1: Select the LDO
using the drop-down
box
Step 2: The data-
sheet parameters are
automatically entered

Step 3: Enter the

system requirements

Step 4: Select the

ballast resistor
Step 5: Use this many
LDOs to meet the
system requirements
Parallel LDO calculator 24
Three parallel TPS7A57 LDO analysis and test data
100% 100%
VIN – VOUT = 100 mV
95%
75% 90%

Efficiency
VIN – VOUT = 300 mV 85%
Efficiency

50% 80%
ILOAD = 10 A
75%
VLOAD = 748.5 mV 70% VIN – VOUT = 100 mV
25% VIN – VOUT = 200 mV
Analysis 65% VIN – VOUT = 300 mV
Measurement 60%
0% PD = 6.75 W, 30 minutes
2 4 6 8 10 12 14 16 0.5 1.5 2.5 3.5 4.5 5.5
VIN = 1.5 V, VLOAD = 1 V, ILOAD = 13.5 A
ILOAD (A) VLOAD (V)

25
Three parallel TPS7A57 LDO analysis and test data
VIN

VOUT

5 APK

26
LDOs configured as constant-current sources
LDO1

IN OUT
IREF COUT RB 14
Three TPS7A57 LDOs
12 RB = 50 mΩ
LDO2
10
IN OUT

ILOAD (A)
IREF COUT RB 8
6
4
LDOn
VLOAD 2 Measurement
IN OUT
COUT RB
Analysis
VIN
IREF 0
ILOAD 20 220 420 620 820 1020 1220 1420 1620
RNR/SS (Ω)
CNR/SS RNR/SS

• Applications include noise-sensitive

IOUT R B ILOAD R B electronics typically driven by constant-
R NR/SS = = 2
N × IREF N × IREF current drivers (laser diodes, LEDs)
27
MISO power supply
• Modern complex systems have many
power supplies, both on the input to the
system and internally VSOURCE (5W maximum) SISO Power Converter Load (7W)

• Sometimes the required power to a

load is higher than the available power
from a single input rail
VSOURCE (5W maximum)
• MISO power supplies can take multiple
input supplies and merge power to VSOURCE (2W maximum) MISO Power Converter Load (7W)
provide a load on a single output
VSOURCE (3W maximum)

28
MISO parallel LDO design process
#1 Obtain:
• Maximum rail current
#5
• Number of parallel LDOs required
Simulate in PSpice for TI

#2
Set VLOAD based on VOUTn and the
allowable load regulation #6

Does the simulated IOUTn

and VLOAD meet the
#3 Assume VE for each rail
No system requirements?
VE,high: IOUTn VLOAD
VE,low: IOUTn VLOAD
VE,typical : IOUTn VLOAD
Yes

#4 Calculate RBn for each LDO #7

𝑉𝑂𝑈𝑇𝑛 −𝑉𝐿𝑂𝐴𝐷 𝑉𝐸𝑛 Fabricate the design
𝑅𝐵𝑛 = +
𝐼𝑂𝑈𝑇𝑛 𝐼𝑂𝑈𝑇𝑛

29
Parallel SISO LDOs vs. MISO LDOs

VOUT = 748.5 mV

VLOAD = 0.75 V
VLOAD = 0.75 V
PD each LDO = 1.55 W
PD each LDO = 1.55 W
VIN1 = 1.72 V, IOUT1 = 1.6 A
VIN1 = VIN2 = VIN3 = 1.25 V
VIN2 = 1.25 V, IOUT2 = 3.1 A
ILOAD = 9.3 A
VIN3 = 1.09 V, IOUT3 = 4.6 A
MISO LDO Single-input single-output (SISO) LDO 30
Summary
• Covered the basic characteristics of LDO noise, PSRR, thermal performance
and operation near dropout
o Discussed what does and does not affect LDO noise and PSRR
• It is easy to configure LDOs to regulate current instead of voltage
• New resources allow you to quickly design with parallel LDOs using ballast
resistors
o Parallel LDOs can increase the load current, reduce system noise, improve PSRR,
improve thermal performance and reduce the required headroom
• Connecting different input voltages to each parallel LDO input creates a MISO
converter
o Changing the ballast resistor adjusts the power sourced from each input supply

31
Resources
• "Accurately measuring efficiency of ultralow Iq devices"
• "Overcoming Low-Iq Challenges in Low-Power Applications“
• "Optimizing feedforward compensation in linear regulators“
• "Simplifying Stability Checks“
• "Avoid Start-up Overshoot of LDO"
• "LDOs Ease the Stress of Start-Up"
• "Soft-start circuits for LDO linear regulators"
• “LDO Basics”
• “How to Measure LDO Noise”
• “LDO PSRR Measurement Simplified”
32
Resources
• "Understanding power supply ripple rejection in linear regulators“
• “Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout
Regulator”
• “An Empirical Analysis of the Impact of Board Layout on LDO Thermal
Performance”
• “Measuring the Thermal Impedance of LDOs in Situ”
• "Switch-mode power converter compensation made easy“
• “Comprehensive Analysis and Universal Equations for Parallel LDOs Using
Ballast Resistors”
• “Parallel LDO Architecture Design Using Ballast Resistors”
• "Parallel LDO calculator"
33
Resources
• “Scalable, High-Current, Low-Noise Parallel LDO Reference Design”
• “Semiconductor and IC Package Thermal Metrics”

34
Q&A

35
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated