Week 12

Interrupts

These lecture notes are based on the book by Muhammed Ali Mazidi,
Janice Gillispie Mazidi, Danny Causey; «The x86 PC assembly language,
design, ad interfacing», 5the Ed., Prentice Hall
 8088/86 INTERRUPTS
u An interrupt is an external event that
informs the CPU that a device needs its
service.
u In 8088/86 there are a total of 256 interrupts.
u INT 00, INT 01, ..., INT FF (sometimes called TYPEs).

u When an interrupt is executed, the

processor:
u Saves the flag register (FR), instruction pointer
(IP), and code segment register (CS) on the stack,.
u Goes to a fixed memory location where the address
of the interrupt service routine is stored.
u In x86, always four times the value of the interrupt
number.
 8088/86 INTERRUPTS
interrupt service routine (ISR)
There must be an interrupt service
routine associated with every
interrupt .
This program i.e., the interrupt
service routine (ISR), is also called
the interrupt handler.
 8088/86 INTERRUPTS
interrupt service routine (ISR) Interrupt vector table

u For every interrupt there are four bytes of

memory allocated in the interrupt vector
table.

– Two bytes for the IP.

– Two for the CS of the ISR.
• These locations provide the addresses
of the interrupt service routine for which
the interrupt was invoked.
– The lowest 1024 bytes of memory
space are set aside for the interrupt
vector table.
 8088/86 INTERRUPTS
interrupt service routine (ISR)
 8088/86 INTERRUPTS
Types of Interrupts

https://www.tutorialspoint.com/microprocessor/microprocessor_8086_interrupts.htm
 8088/86 INTERRUPTS
categories of interrupts
u Three x86 pins are associated with hardware interrupts...
u INTR (interrupt request)
u NMI (non-maskable interrupt)
u INTA (interrupt acknowledge)
u INTR is a CPU input signal, which can be masked (ignored) &
unmasked through use CLI and STI.
u NMI, also an input signal into the CPU, cannot be masked and
unmasked using CLI & STI.
u For this reason, it is called a non-maskable interrupt.
 8088/86 INTERRUPTS
hardware interrupts
u INTR and NMI are activated externally by putting 5V on the x86
microprocessor NMI & INTR pins.
u On activation of either interrupt, x86:
u Finishes the instruction it is executing.
u Pushes FR & CS:IP of the next instruction onto the stack.
u Jumps to a fixed location in the interrupt vector table and fetches the CS:IP
for the interrupt service routine (ISR) associated with that interrupt.

• At the end of the ISR, IRET causes the CPU to get (pop)
back its original FR and CS:IP from the stack.
– Forcing the CPU to continue at the instruction where it left off
when the interrupt came in.
 8088/86 INTERRUPTS
hardware interrupts
u Intel has embedded "INT 02" in x86, only for NMI.
u When the NMI pin is activated, the CPU location 00008 to get the
address (CS:IP) of the ISR.
u Memory locations 00008, 00009, 0000A, and 0000B contain the 4 bytes of
CS:IP of the ISR belonging to NMI.
u There is no specific location in the vector table assigned to
INTR.
u Allowed to use any "INT nn" not previously assigned.
u The INTR interrupt is usually activated by an external hardware device
u The 8259 programmable interrupt controller (PIC) chip can be
connected to INTR to expand the number of hardware interrupts to 64.
Example HW interrupt
Example
If an interrupt C2H is to be issued, what would be the values 2A4-1A1?

2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1

 8088/86 INTERRUPTS
software interrupts
u An ISR called as a result of execution of
an x86 instruction such as "INT nn“ is
referred to as a software interrupt.
u As it was invoked from software, not external
hardware.
u DOS "INT 21H" function calls,
and video interrupts "INT 10H".
u Can be invoked in code like a CALL or other x86
instruction
u Some of the interrupts are associated with
predefined functions.
 8088/86 INTERRUPTS
software interrupts

INT 00 to INT 04 have

predefined functions.
INT 00 (divide error)
INT 01 (single step)
INT 03 (breakpoint)
INT 04 (signed number overflow)

Interrupts INT 05 to INTFF can be

used for either software or
hardware interrupts.

Figure 14-1 Intel's List of Designated Interrupts for the 8088/86

 8088/86 INTERRUPTS
interrupts and the flag register
u Two flag register bits are associated with interrupt:
u D9, or IF (interrupt enable flag)
u D8, or TF (trap or single step flag).
u OF (overflow flag) can be used by the interrupt.
 8088/86 INTERRUPTS
processing interrupts
When 8088/86 processes any interrupt:
1. The flag register (FR) is pushed onto the stack & SP is decremented
by 2, as FR is a 2-byte register.
2. The IF (interrupt enable flag) & TF (trap flag) are both cleared. (IF
= 0 and TF = 0).
3. The current CS is pushed onto the stack and SP is decremented by 2.
4. The current IP is pushed onto the stack and SP is decremented by 2.
 8088/86 INTERRUPTS
processing interrupts
u When 8088/86 processes any interrupt:

5. The INT number (type) is multiplied by 4 to get the physical

address of the location within the vector table to fetch the CS and
IP of the interrupt service routine.
6. From the new CS:IP, the CPU starts to fetch and execute
instructions belonging to the ISR program.
7. The last instruction of the interrupt service routine must be IRET,
to get IP, CS, and FR back from the stack and make the CPU run
the code where it left off.
 x86 PC AND INTERRUPT ASSIGNMENT

u Of 256 possible interrupts in the x86…

u Some are used by the PC peripheral hardware. (BIOS)
u Some are used by the Microsoft operating system.
u The rest are available for programmers of software applications.
8259 INTERRUPT CONTROLLER
• x86 has only pins INTR
& INTA for interrupts.

Figure 14-3 8259A Programmable Interrupt Controller

8259 INTERRUPT CONTROLLER

The Intel 8259

programmable interrupt
controller (PIC) makes
expansion of the number of
hardware interrupts much
easier.

Figure 14-4 Partial Block Diagram of the 8259A

 8259 INTERRUPT CONTROLLER
pins
u CAS0, CAS1, and CAS2 - can be used to set up several 8259
chips to expand the number of hardware interrupts to 64.
u SP/EN, slave programming/enable
 8259 INTERRUPT CONTROLLER
pins
u INT - an output connected to INTR of the x86.
u INTA - input to the 8259 from INTA of the x86.
u IR0 to IR7, interrupt request - hardware interrupts.
u Just to recap, remember;
u When a HIGH is put on any interrupt from IR0 to IR7, 8088/86 will
jump to a vector location.
u For each IR there exists a physical memory location in the
interrupt vector table.
u The x86 has 256 hardware or software interrupts. (INT 00–INT FF)
 8259 INTERRUPT CONTROLLER
control words and ports
u Four control words associated with
the 8259:

– ICW1 (initialization command

word); ICW2; ICW3; ICW4.
– There is only one address line
A0 to communicate with the chip.

Figure 14-3 8259A Programmable Interrupt Controller

Connection of 8259 to 8086
 8259 INTERRUPT CONTROLLER
control words and ports

Table 14-3 and Example 14-7 show

the values that A0 and CS must
take to initialize the 8259.
1
 8259 INTERRUPT CONTROLLER
control words and ports

u ICW1, initialization command word 1 - functions to

make a distinction between ICW2, ICW3, and ICW4
when they are sent to the same address of 8259.
u D0, LSB of ICW1, tells 8259 if it should look for ICW4 or not.
u If D1 is high, it knows the system is configured in single
mode, should not expect any ICW3 in the initialization
sequence.
u Initialization must always start with ICW1, followed by ICW2, and
finally the last one, if needed; there is no jumping ahead.
 8259 INTERRUPT CONTROLLER
control words and ports
u ICW1, initialization command word 1.

D2 is always set
low (= 0) for x86.
D3 chooses between level
triggering or edge triggering
of the input signals IR0–IR7.
D4 must always be high.
D5, D6, and D7 are all low
for x86 processors.

Figure 14-5 ICW Formats (ICW1 and ICW2)for the 8259

 8259 INTERRUPT CONTROLLER
control words and ports
u ICW2, initialization command word 2 - assigns interrupt
numbers to IR0–IR7.
u The 8-bit INT type number assigned to the corresponding IR0 through
IR7 is formed by the lower three bits D3–D7. (T3 through T7)
u Lower three bits, D0, D1, and D2, vary from 000 to 111.
u For example, if 40F is assigned to IR0, then 41 will be assigned to IR1, 42
will be assigned to IR2 and so on; i.e.
0100 0000
0100 0001
0100 0010
..
..
 8259 INTERRUPT CONTROLLER
control words and ports
D3–D7 can only be
u ICW2, initialization command word 2. programmed according
to the assignment of
the INT type.
The lower bits are
provided by 8259,
depending on which
interrupt of IR0 to IR7
is activated.
 8259 INTERRUPT CONTROLLER
control words and ports
u ICW3, initialization command word 3 - used only when two or more
8259s are cascaded.
u A single 8259 can be connected to eight slave 8259s.
u In cascade mode, there are separate ICW3 words for the master and the slave.

u ICW4, initialization command word 4 - D0 indicates the processor

mode. (PM)
u D0 equals 1 for the 8088/86 and 0 for the 8080/8085.
u D1 is AEOI (automatic end of interrupt), is high it eliminates the need for an
EOI instruction to be present before the IRET (interrupt return) instruction in
the interrupt service routine.
 8259 INTERRUPT CONTROLLER
control words and ports – ICW3
• For example, if there is
slave connected to IR2; for
this connection, in both
master and slave, we place
04H in ICW3.
• Suppose we have two slaves
connected to a master
using IR0 and IR1. The
master is programmed with
an ICW3 of 03H; one slave
is programmed with an
ICW3 of 01H and the other
with an ICW3 of 02H.
 8259 INTERRUPT CONTROLLER
control words and ports (ICW4)

SFNM, special fully nested

mode must be used when
8259 is in master mode,

Figure 14-6a & b

ICW Formats (ICW3 and CW4)for the 8259 - Master & Slave
Example

(a) Find the ICWs of the 8259 if it is used with an 8088/86 CPU, single, level
triggering IRs, and IR0 is assigned “INT 50H.” The 8259 is in slave buffered mode
with normal EOI.
(b) Show the program to initialize the 8259 using the port addresses 26H
(c) Find the addresses associated with IR0, IR1, and IR2 in the interrupt vector
table.
Note: This example is not PC-compatible and is given only for an exercise
Solution (a)
ICW1 1BH

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 1 0 1 1

ICW2 50H
D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 1 0 0 0 0

ICW3 Not needed

Solution (a) cont.

ICW4 09H

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 1 0 0 1
Solution (b) and ( c )
8259 INTERRUPT CONTROLLER
masking/prioritization IR0–IR7 interrupts

What happens if more than one of interrupts IR0–IR7

is activated at the same time?

Can we mask any of the interrupts?

What about responding to another interrupt while an

interrupt is being serviced?
 8259 INTERRUPT CONTROLLER
operation command word OCW
u After ICW1, ICW2, ICW3 and ICW4 have been issued to
initialize the 8259, 8088/86 is ready to receive hardware
interrupts through 8259's IR0–IR7 pins.
u After the process of initialization, the operation command word, OCW,
can be sent (optional) to mask any of IR0–IR7, or change the priority
assigned to each IR.

There are three operation

command words:
OCW1, OCW2, OCW3.
 8259 INTERRUPT CONTROLLER
operation command word OCW
u With the help of OCWs, a programmer can dynamically change the
priority associated with each of IR0–IR7, or mask any of them.
u Example 14-9 shows how OCWs are sent to the 8259.
 8259 INTERRUPT CONTROLLER
operation command word OCW

Three registers to note in the

8259:
ISR
(in-service register)
IRR
(interrupt request register)
IMR (interrupt mask register)

Figure 14-4 Partial Block Diagram of the 8259A

 8259 INTERRUPT CONTROLLER
operation command word 1 OCW1 OCW1 is used to mask any of IR0–IR7.
Logic 1 is for masking. (disabling)
Logic 0 is for unmasking. (enabling)

Figure 14-7 OCW Format for 8259A

 8259 INTERRUPT CONTROLLER
operation command word 1 OCW3
8259 INTERRUPT CONTROLLER
OCW3

u OCW3 is used read 8259 registers IRR (interrupt request register)

& ISR (in-service register).
u D0 and D1 allow the program to read these registers in order to see which
of IR0–IR7 is pending for service, and which one is being served.
 8259 INTERRUPT CONTROLLER
operation command word 2 OCW2
u OCW2 - used to assign a specific priority to the IRs.
u Fully nested default mode - assigns the highest priority to IR0 and the
lowest to IR7.
u 8259 can be programmed to change the default mode to assign the highest
priority to any IR.

– Specific rotation mode - 8259 can be programmed to

make rotation follow a specific sequence rather than
IR0 to IR7.
• The IR served will be stamped as the lowest priority, and will
not be served until every other request has had a chance.
OCW2
 MORE ON INTERRUPTS IN x86 PCs
x86 PC hardware interrupts

Master controls the slaves thru CAS lines.

They act as chip select to the slaves
Figure 14-11 8259 Chips in Master/Slave
Relation for 286 and x86 PCs
 USE OF THE 8259 CHIP IN x86 PCs
Interfacing 8259 to the IBM PC
Two port addresses must be assigned to the 8259:
One for ICW1; the second for ICW2/ICW4.
Since the chip select is activated
by Y1 and all the x's for don't care
must be zero, the addresses can
be calculated in the manner
shown.
 USE OF THE 8259 CHIP IN x86 PCs 8259
initialization words in the PC
u Configuration for the control words ICW1, ICW2, and ICW4 can be calculated:
 USE OF THE 8259 CHIP IN x86 PCs 8259
initialization words in the PC
u PC designers assigned INT 08–INT 0F for expansion of hardware
interrupts.
u Used by 8259 IR0–IR7, commonly called IRQ0–IRQ7.

INT 08 is for IRQ0,

INT 09 is for IRQ1,
etc.
 USE OF THE 8259 CHIP IN x86 PCs 8259
initialization words in the PC

u ICW2 informs 8259 which interrupt numbers

are assigned to IRQ0–IRQ7.
u By equating 8259 ICW2 to the interrupt assigned to IRQ0.
u ICW2 is the interrupt number for IR0, in the IBM PC, INT08.
u The 8259 is only programmed for the value of IRQ0, so the
8259 generates the INT numbers for IR1 through IR7.
u ICW3 is used only when multiple 8259 chips are
connected in master/slave mode.
 USE OF THE 8259 CHIP IN x86 PCs 8259
initialization words in the PC
u ICW4 configuration:

– Gives the following code for 8259 initialization:

 USE OF THE 8259 CHIP IN x86 PCs 8259
initialization

u Once the 8259 is initialized, it is ready to accept an

interrupt on any inputs IRQ0–IRQ7.
u Expanding the number of hardware interrupts.
u The 8259 is tested by a program in BIOS during the POST
(power on self test).
8288 Bus controller
 USE OF THE 8259 CHIP IN x86 PCs
sequences of 8259 hardware interrupts
Sequence of events after an 8259 IR is activated.
1. After an IR is activated, the 8259 will respond by putting a high on
INTR.
Signaling the CPU for an interrupt request.
2. 8088/86 puts the appropriate signals on S0, S1 & S2 (S0 = 0, S1 = 0,
and S2 = 0- Interrupt acknowledgement), indicating to the 8288 that an
interrupt has been requested.
3. The 8288 issues the first INTA to the 8259.
4. The 8259 receives the first INTA and does internal housekeeping,
which includes resolution of priority, and resolution of cascading.
5. The 8288 issues the second INTA to the 8259.
 USE OF THE 8259 CHIP IN x86 PCs
sequences of 8259 hardware interrupts
u Sequence of events after an 8259 IR is activated.

6. On the second INTA pulse, 8259 puts a single interrupt vector

byte on the data bus in which 8088/86 will latch. INTR.
• The value of the single byte depends on ICW2 and which IR has been
activated.
7. 8088/86 uses this byte to calculate the vector location,
which is four times the value of the INT type.
 USE OF THE 8259 CHIP IN x86 PCs
sequences of 8259 hardware interrupts
u Sequence of events after an 8259 IR is activated.

8. 8088/86 pushes the flag register onto the stack, clears IF

(Interrupt Flag) & TF (Trap Flag), disabling further external
interrupt requests and single-step mode. INTR.
• And pushes the present CS:IP registers onto the stack.
9. The 8088/86 reads CS:IP of the interrupt service routine
from the vector table and begins execution of the interrupt
routine.
 USE OF THE 8259 CHIP IN x86 PCs
sources of hardware interrupts
u With the 8259, the PC has eight interrupts.
u IR0 to IR7, plus NMI of the 8088/86.
u IBM has used two for internal use by the system.
u IR0 - for channel 0 of the 8253 timer to update the time of day (TOD)
clock,
u IR1 - dedicated to the keyboard.
u IR2 through IR7 are available through the expansion slots.

u The following interrupts are used on the motherboard:

u INT 08 IRQ0 Channel 0 of 8253 timer to update TOD
u INT 09 IRQ1 Keyboard input data
 USE OF THE 8259 CHIP IN x86 PCs
sources of hardware interrupts

Figure 14-9
PC Sources of Hardware Interrupts
 USE OF THE 8259 CHIP IN x86 PCs
sources of NMI

u The NMI, nonmaskable interrupt, is a CPU pin, and cannot be masked (disabled)
by software.
u There are three sources of activation of the NMI:
1. NPIRQ. (numerical processor interrupt request)
2. Read/write PCK. (parity check)
3. IOCHK. (input/output channel check)
u The PC recognizes which of interrupt requests has been activated by checking
input port C of the 8255.
 USE OF THE 8259 CHIP IN x86 PCs
sources of NMI

NMI is masked by a RESET

signal from the CPU with
CLR of the D flip-flop when
the computer is turned on.