GHOUSIA COLLEGE OF ENGINEERING, RAMANAGARAM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LESSON PLAN
Name of the faculty : C. K. VENKATESH Academic Year : 2017 - 18
Subject with Code : DSP Algorithm & Architecture 10EC751 Class : VII Sem 'A'

Sl. Schedule Dtea Of Actual

Topic Proposed To Be Covered
No Date Coverage

Unit 1
1 11/8/2017 Introduction to DSP System
2 16/8/2017 The Sampling Process, Discrete Time Sequences
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT),
3
18/8/2017 Linear Time-Invariant Systems.
4 23/8/2017 Digital Filters
5 6/9/2017 Decimation and Interpolation
Numerical
6
8/9/2017
Unit 2
7 Introduction, Basic Architectural Features
13/9/2017
8 15/9/2017 DSP Computational Building Blocks, Bus Architectures
9 20/9/2017 Memory, Data Addressing Capabilities
10 22/9/2017 Address Generation Unit

11 27/9/2017 Programmability And Program Execution

12 4/10/2017 Features of External Interfacing

13 6/10/2017 Numericals

Unit 3
11/10/2017 Programmable Digital Signal Processors

16 13/10/2017 Commercial Digital Signal Processing Devices

17 25/10/2017 Data Addressing Modes of TMS32OC54xx

18 27/10/2017 Memory Space of TMS32OC54xx Processors

Unit 4
19 3/11/2017 Detail Study Of TMS32OC54xx & 54xx Instructions and programming

20 8/11/2017 On-Chip Peripherals, Interrupts of TMS32OC54xx Processors

21 10/11/2017 Pipeline Operation of TMS32OC54xx Processors

22 15/11/2017 Numericals

Signature of the staff Signature of HOD Signature of Principal

 GHOUSIA COLLEGE OF ENGINEERING, RAMANAGARAM
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
LESSON PLAN
Name of the faculty : C. K. VENKATESH Academic Year : 2017 - 18
Subject with Code : DSP Algorithm & Architecture 10EC751 Class : VII Sem 'B'

Sl. Schedule Dtea Of Actual

Topic Proposed To Be Covered
No Date Coverage

Unit 1
1 10/8/2017 Introduction to DSP System
2 14/8/2017 The Sampling Process, Discrete Time Sequences
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT),
3
17/8/2017 Linear Time-Invariant Systems.
4 28/8/2017 Digital Filters
5 31/8/2017 Decimation and Interpolation
Numerical
6
4/9/2017
Unit 2
7 Introduction, Basic Architectural Features
7/9/2017
8 11/9/2017 DSP Computational Building Blocks, Bus Architectures
9 14/9/2017 Memory, Data Addressing Capabilities
10 18/9/2017 Address Generation Unit

11 21/9/2017 Programmability And Program Execution

12 25/9/2017 Features of External Interfacing

13 28/9/2017 Numericals

Unit 3
9/10/2017 Programmable Digital Signal Processors

16 12/10/2017 Commercial Digital Signal Processing Devices

17 16/10/2017 Data Addressing Modes of TMS32OC54xx

18 19/10/2017 Memory Space of TMS32OC54xx Processors

Unit 4
19 23/10/2017 Detail Study Of TMS32OC54xx & 54xx Instructions and programming

20 30/10/2017 On-Chip Peripherals, Interrupts of TMS32OC54xx Processors

21 9/11/2017 Pipeline Operation of TMS32OC54xx Processors

22 13/11/2017 Numericals
Signature of the staff Signature of HOD Signature of Principal

VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI B.E: Electronics & Communication Engineering /

B.E: Electronics & Telecommunication Engineering NEP, Outcome Based Education (OBE) and Choice
Based Credit System (CBCS) (Effective from the academic year 2021 – 22) VII Semester DSP Algorithms &
Architecture Course Code 21EC723 CIE Marks 50 Teaching Hours/Week (L:T:P:S) 3:0:0:1 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100 Credits 3 Exam Hours 3 Course objectives: This course will
enable the students to  Understand the concepts of digital signal processing techniques.  Understand
the computational building blocks of DSP processors and its speed issues.  Understand the various
addressing modes, peripherals, interrupts and pipelining structure of the TMS320C54xx processor. 
Learn how to interface the external devices to the TMS320C54xx processor in various modes. 
Understand DSP algorithms and applications with their implementation using TMS320C54xx processor.
Teaching-Learning Process (General Instructions) The sample strategies, which the teacher can use to
accelerate the attainment of the various course outcomes are listed in the following: 1. Lecture method
(L) does not mean only the traditional lecture method, but a different type of teaching method may be
adopted to develop the outcomes. 2. Show Video/animation films to explain the functioning of various
techniques. 3. Encourage collaborative (Group) Learning in the class 4. Ask at least three HOTS (Higher-
order Thinking) questions in the class, which promotes critical thinking 5. Adopt Problem Based Learning
(PBL), which fosters students’ Analytical skills, develop thinking skills such as the ability to evaluate,
generalize, and analyze information rather than simply recall it. 6. Topics will be introduced in multiple
representations. 7. Show the different ways to solve the same problem and encourage the students to
come up with their own creative ways to solve them. 8. Discuss how every concept can be applied to the
real world - and when that's possible, it helps improve the students' understanding. Module-1
Introduction to Digital Signal Processing: Introduction, A Digital Signal – Processing system, Major
features of programmable Digital signal processors, The Sampling Process, Discrete Time Sequences,
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear Time-Invariant Systems,
Digital Filters, Decimation and Interpolation. Section 1.3, 2.1 to 2.8 of Text 1 Teaching-Learning Process
Chalk and talk method, Power point presentation RBT Level: L1, L2, L3 Module-2 Architectures for
Programmable Digital Signal Processing Devices: Introduction, Basic Architectural Features, DSP
Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address
Generation Unit, Programmability and Program Execution, Speed Issues, Features for External
Interfacing. Section 4.1 to 4.9 of Text 1 Teaching-Learning Chalk and talk method, Power point
presentation 19.09.2023 21EC733 03.10.2022 Process RBT Level: L1, L2, L3 Module-3 Programmable
Digital Signal Processors: Introduction, Commercial Digital Signal-processing Devices, Data Addressing
Modes of TMS32OC54XX, Memory Space of TMS32OC54xx Processors, Program Control. Detail Study of
TMS320C54X & 54xx Instructions and Programming, On – Chip Peripherals, Interrupts of TMS32OC54XX
Processors, Pipeline Operation of TMS32OC54xx Processor. Section 5.1 to 5.10 of Text 1 Teaching-
Learning Process Chalk and talk method, Power point presentation RBT Level: L1, L2, L3 Module-4
Implementation of Basic DSP Algorithms: Introduction, The Q – notation, FIR Filters, IIR Filters,
Interpolation and Decimation Filters (one example in each case). Implementation of FFT Algorithms:
Introduction, An FFT Algorithm for DFT Computation, Overflow and Scaling, Bit – Reversed Index.
Generation & Implementation on the TMS32OC54xx. Section 7.1 to 7.6 and 8.1 to 8.6 of Text 1
Teaching-Learning Process Chalk and talk method, Power point presentation RBT Level: L1, L2, L3
Module-5 Interfacing Memory and Parallel I/O Peripherals to Programmable DSP Devices: Introduction,
Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface,
Programmed I/O, Interrupts and I/O Direct Memory Access (DMA). Interfacing and Applications of DSP
Processors: Introduction, Synchronous Serial Interface, A CODEC Interface Circuit, DSP Based Bio-
telemetry Receiver, A Speech Processing System, An Image Processing System. Section 9.1 to 9.8, 10.1 to
10.5 and11.1 to 11.5 of Text 1 Teaching-Learning Process Chalk and talk method, Power point
presentation RBT Level: L1, L2, L3 Course outcome (Course Skill Set) At the end of the course the student
will be able to: 1. Comprehend the knowledge & concepts of digital signal processing techniques. 2.
Apply knowledge of various types of addressing modes, interrupts, peripherals and pipelining structure
of TMS320C54xx processor. 3. Develop assembly language programs to implement FIR, IIR filters and FFT
algorithms. 4. Build the Applications on Programmable DSP devices. Assessment Details (both CIE and
SEE) The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50). A
student shall be deemed to have satisfied the academic requirements and earned the credits allotted to
each subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together. Continuous Internal
Evaluation: Three Unit Tests each of 20 Marks (duration 01 hour) 1. First test at the end of 5th week of
the semester 2. Second test at the end of the 10th week of the semester 3. Third test at the end of the
15th week of the semester Two assignments each of 10 Marks 4. First assignment at the end of 4th
week of the semester 5. Second assignment at the end of 9th week of the semester Group
discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20 19.09.2023
03.10.2022 Marks (duration 01 hours) 6. At the end of the 13th week of the semester The sum of three
tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks and will be scaled
down to 50 marks (to have less stressed CIE, the portion of the syllabus should not be common
/repeated for any of the methods of the CIE. Each method of CIE should have a different syllabus portion
of the course). CIE methods /question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course. Semester End Examination: Theory SEE will be
conducted by University as per the scheduled timetable, with common question papers for the subject
(duration 03 hours) 1. The question paper will have ten questions. Each question is set for 20 marks. 2.
There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module. The students have to
answer 5 full questions, selecting one full question from each module.. Marks scored out of 100 shall be
reduced proportionally to 50 marks Suggested Learning Resources: Text Book: “Digital Signal
Processing”, Avatar Singh and S Srinivasan, Thomson Learning, 2004 Reference Books: 1. “Digital Signal
Processing: A practical approach”, Ifeachor E C, Jervis B. W Pearson-Education, PHI, 2002. 2. “Digital
Signal Processors”, B Venkataramani and M Bhaskar, TMH, 2nd Ed., 2010 3. “Architectures for Digital
Signal Processing”, Peter Pirsch, John Wiley.

Course objectives:
This course will enable the students to
Understand the concepts of digital signal processing techniques.
Understand the computational building blocks of DSP processors and its speed issues.
Understand the various addressing modes, peripherals, interrupts and pipelining structure of the
TMS320C54xx processor.
Learn how to interface the external devices to the TMS320C54xx processor in various modes.
Understand DSP algorithms and applications with their implementation using TMS320C54xx
processor.