Data Converters for Solving Hard

Problems
Advanced Techniques of Higher Performance Signal Processing
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2
Today’s Agenda

 Data converters in the signal chain

 Basics of data conversion
 Dynamic signal processing
 Driving ADCs
 Input structures
 DACs for high speed and high resolution

3
Analog to Electronic Signal Processing

SENSOR AMP CONVERTER

(INPUT)

DIGITAL
PROCESSOR

ACTUATOR AMP CONVERTER

(OUTPUT)

4
Analog to Electronic Signal Processing

SENSOR AMP ADC

(INPUT)

DIGITAL
PROCESSOR

ACTUATOR AMP DAC

(OUTPUT)

5
Analog and Digital Domains
Why Convert to Digital?

 Analog signals are continuous and provide the entire signal

 Digital signals capture only a portion of the signal
 Why digitize?
 Improved signal analysis potential
 More robust storage
 More accurate transmission

 Why not digitize?

 Cost
 Complexity
 Processing time available.

 Development objective of sampled data systems is to minimize

effect of the sampling process

6
Basic ADC with External Reference

SAMPLING VDD
VREF
CLOCK
VDIO

ANALOG
INPUT
DIGITAL
ADC OUTPUT

VSS
GROUND CONTROL SIGNALS
(MAY BE INTERNALLY (EOC, DATA READY, ETC.)
CONNECTED TO VSS)

7
Sampled Data System: Sampling and
Quantization

fs fs

fa LPF LPF
N-BIT N-BIT
OR DSP OR
ADC DAC
BPF BPF

AMPLITUDE
QUANTIZATION DISCRETE
TIME SAMPLING

fa

1
ts=
fs

8
Unipolar Binary Code, 4-Bit Converter

BASE 10 +10 V FS BINARY

SCALE
NUMBER

+15 +FS – 1 LSB = 15/16 FS 9.375 1111

+14 +7/8 FS 8.750 1110
+13 +13/16 FS 8.125 1101
+12 +3/4 FS 7.500 1100
+11 +11/16 FS 6.875 1011
+10 +5/16 FS 6.250 1010
+9 +9/16 FS 5.625 1001
+8 +1/2 FS 5.000 1000
+7 +7/16 FS 4.375 0111
+6 +3/8 FS 3.750 0110
+5 +5/16 FS 3.125 0101
+4 +1/4 FS 2.500 0100
+3 +3/16 FS 1.875 0011
+2 +1/8 FS 1.250 0010
+1 1 LSB = +1/16 FS 0.625 0001
0 0 0.000 0000

9
Bipolar Codes, 4-bit Converter

BASE 10 OFFSET TWOS ONES SIGN

NUMBER SCALE ±5V FS BINARY COMP. COMP. MAG.
+7 +FS – 1LSB = +7/8 FS +4.375 1111 0111 0111 0111
+6 +3/4 FS +3.750 1110 0110 0110 0110
+5 +5/8 FS +3.125 1101 0101 0101 0101
+4 +1/2 FS +2.500 1100 0100 0100 0100
+3 +3/8 FS +1.875 1011 0011 0011 0011
+2 +1/4 FS +1.250 1010 0010 0010 0010
+1 +1/8 FS +0.625 1001 0001 0001 0001
0 0 0.000 1000 0000 *0 0 0 0 *1 0 0 0
–1 – 1/8 FS –0.625 0111 1111 1110 1001
–2 – 1/4 FS –1.250 0110 1110 1101 1010
–3 – 3/8 FS –1.875 0101 1101 1100 1011
–4 –1/2 FS –2.500 0100 1100 1011 1100
–5 –5/8 FS –3.125 0011 1011 1010 1101
–6 –3/4 FS –3.750 0010 1010 1001 1110
–7 – FS + 1LSB = –7/8 FS –4.375 0001 1001 1000 1111
–8 – FS –5.000 0000 1000
ONES SIGN
COMP. MAG.
0+ 0000 0000
CODES NOT NORMALLY USED * 0– 1111 1000
IN COMPUTATIONS (SEE TEXT)
10
The Size of a Least Significant Bit (LSB)

RESOLUTION 2N VOLTAGE ppm FS % FS dB FS

N (10V FS)
2-bit 4 2.5 V 250,000 25 -12
4-bit 16 625 mV 62,500 6.25 -24
6-bit 64 156 mV 15,625 1.56 -36
8-bit 256 39.1 mV 3,906 0.39 -48
10-bit 1,024 9.77 mV (10 mV) 977 0.098 -60
12-bit 4,096 2.44 mV 244 0.024 -72
14-bit 16,384 610 mV 61 0.0061 -84
16-bit 65,536 153 mV 15 0.0015 -96
18-bit 262,144 38 mV 4 0.0004 -108
20-bit 1,048,576 9.54 mV (10 mV) 1 0.0001 -120
22-bit 4,194,304 2.38 mV 0.24 0.000024 -132
24-bit 16,777,216 596 nV* 0.06 0.000006 -144

*600nV is the Johnson Noise in a 10kHz BW of a 2.2kW Resistor @ 25°C

11
Practical Resolution Needs for Data Converters

 Instrumentation measurements
 Sensor resolution/accuracy of 0.5% = 1/200
 8 bits equivalent to 1/256 -- digitizing will lose information
 10x sensor resolution = 1/2000 -- 12 bits is 1/4096
 Allows discrimination of small changes
 Can also be driven by display requirements

 Dynamic signal measurements

 Audio systems need better than 0.1% distortion at 5% of full scale
 Equivalent to 1/20,000 -- 16 bits is 1/65,536

12
Transfer Functions for Ideal 3-Bit DAC and ADC

DAC ADC
FS

111

110

ANALOG DIGITAL 101

OUTPUT OUTPUT
100

011
QUANTIZATION
UNCERTAINTY
010 QUANTIZATION
UNCERTAINTY
001

000
000 001 010 011 100 101 110 111 ANALOG INPUT FS
DIGITAL INPUT

13
Primary Errors in Data Converters
(DC Parametrics)

 Instrumentation and measurement

 Described in LSBs (least-significant-bit), % of FS, ppm of FS
 Offset error – the input level needed to change the first code
 Gain/full-scale error – the input level need to change the last code
 Nonlinearity – deviation of codes from the line from zero to FS
 Differential nonlinearity – code-to-code deviation from 1 LSB
 Transition noise – ADC uncertainty in code center point

14
Primary Errors in Data Converters
(AC Parametrics)
 Dynamic systems
 SINAD (Signal-to-Noise-and-Distortion Ratio):

The ratio of the rms signal amplitude to the mean value of the root-
sum-squares (RSS) of all other spectral components, including
harmonics, but excluding DC.

 ENOB (Effective Number of Bits):

SINAD – 1.76dB
ENOB =
6.02dB
 SNR (Signal-to-Noise Ratio), or Signal-to-Noise Ratio without
Harmonics:

The ratio of the rms signal amplitude to the mean value of the root-
sum-squares (RSS) of all other spectral components, excluding the first
5 harmonics and DC

 SFDR (Spurious-Free-Dynamic-Range) Signal dynamic range in the

bandwidth of interest containing no frequency noise spurs
15
Quantifying Data Converter
Dynamic Performance
 Harmonic Distortion
 Worst Harmonic
 Total Harmonic Distortion (THD)
 Total Harmonic Distortion Plus Noise (THD + N)
 Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D)
 Effective Number of Bits (ENOB)
 Signal-to-Noise Ratio (SNR)
 Analog Bandwidth (Full-Power, Small-Signal)
 Spurious Free Dynamic Range (SFDR)
 Two-Tone Intermodulation Distortion
 Multi-tone Intermodulation Distortion
 Noise Power Ratio (NPR)
 Adjacent Channel Leakage Ratio (ACLR)
 Noise Figure
 Settling Time, Overvoltage Recovery Time

16
The Comparator: A 1-Bit ADC

LATCH
ENABLE

DIFFERENTIAL LOGIC
ANALOG INPUT OUTPUT
–
COMPARATOR
OUTPUT
"1"

VHYSTERESIS

"0"
0
DIFFERENTIAL ANALOG INPUT

17
Quantization and Quantization Noise

111
110
DIGITAL OUTPUT

101
100
011
010
001

1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS

NORMALIZED ANALOG INPUT
Quantization
error function

Quantization noise error: RMS value is LSB/3.464

18
Combined Effects of Code Transition Noise
and DNL

CODE TRANSITION NOISE DNL TRANSITION NOISE

AND DNL

ADC
OUTPUT
CODE

ADC INPUT ADC INPUT ADC INPUT

19
Ideal ADC Sampling
3 Different Frequencies, Sampled the Same

20
Ideal ADC Sampling
Once Sampled, Information Is Lost

21
Nyquist's Criteria

 A signal with a maximum bandwidth of fa must be sampled at a rate fs > 2fa

or information about the signal will be lost because of aliasing.
 Aliasing occurs whenever fs < 2fa
 A signal which has frequency components between fa and fb must be
sampled at a rate fs > 2 (fb – fa) in order to prevent alias components from
overlapping the signal frequencies.
 The concept of aliasing is widely used in communications applications
such as direct IF-to-digital conversion.

22
Analog Signal fa Sampled @ fs Has Images
(Aliases) At |±Kfs ±fa|, K = 1, 2 ...

fa I I I I

0.5fs fs 1.5fs 2fs

ZONE 1 ZONE 2 ZONE 3 ZONE 4

I fa I I
I

0.5fs fs 1.5fs 2fs

23
Oversampling Relaxes Requirements
on Baseband Antialiasing Filter

A B
fa Kfs – f
fa fs – fa a

DR

fs fs Kfs Kfs
2 2
STOPBAND ATTENUATION = DR STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to fs – fa TRANSITION BAND: fa to Kfs – fa
CORNER FREQUENCY: fa CORNER FREQUENCY: fa

24
Advantages of Differential Analog Input
Interfaces for Data Converters
 Differential inputs give twice the signal swing vs. single-ended
(especially important for low voltage single-supply operation)
 Differential inputs help suppress even order distortion products
 Many IF/RF components such as SAW filters and mixers are
differential
 Differential inputs suppress common-mode ADC switching noise
including LO feed-through from mixer and filter stages
 Differential ADC designs allow better internal component matching
and tracking than single-ended. Less need for trimming
 Helps minimize the effects of noise on the ground.
 If you drive them single-ended, you will have degradation in
distortion and noise performance
 However, many signal sources are single-ended, so the differential
amplifier is useful as a single-ended to differential converter
2.25
ADA4941 Driving AD7690 18-Bit PulSAR® ADC
in +5V Application
VREF = +4.096V
VREF = +4.096V +5V
+5V 0.1µF
0.1µF +5V
9.53kW ADA4941-1 ADR444
11.3kW
+2.1V
+ 41.2W
8.45kW 10.0kW REF VDD
– IN+ INPUT RANGE =
0.1µF 3.9nF
+2.1V +/– 2V 8.192V p-p DIFF.
AD7690, 400kSPS
R VCM = +2.1V
R AD7691, 250kSPS
0.1µF 10.2nV/Hz 18-BIT
PulSAR
+1.75V +2.1V – /+ 2V ADCs
+ SNR = 100dB
41.2W IN–
FOR AD7690
VIN = 10V
–
4.02kW 3.9nF

CF LPF CUTOFF = 1MHz

 After filter, noise = 13 µV rms due to amp

806W  Signal = 8V p-p differential
 SNR = 107 dB

2.26
ADA4937-1 Driving AD6645
in +5V DC-Coupled Application
+5V
0.1µF
200W
0.1µF
VIN +2.4V – / + 0.55V
+5V AD6645
±1.1V 200W 14-BIT ADC
24.9W
+ AIN–
FROM 50W
SOURCE 65.5W +2.4V C 2.2V p-p
ADA4937-1 5nV/Hz
DIFFERENTIAL
VOCM INPUT SPAN
24.9W
226W – AIN+
0.1µF
VREF
200W fs =
80/105MSPS

+1.2V + / – 0.275V +2.4V + / – 0.55V

OUTPUT NOISE = 5nV/Hz 1.57270106 = 103µV rms AD6645 SPECS:

INPUT BW = 270MHz
0.778 1 LSB = 134µV
OUTPUT SNR = 20 log = 77.6dB
10310–6 SNR = 75dB

2.27
Buffered and Unbuffered Differential
ADC Inputs Structures
(A) AVDD (B)
VINA

R1 R1
INPUT SHA
VINA
BUFFER
INPUT
SHA VINB
BUFFER
VINB
R2 R2
BUFFERED INPUTS VREF

GND

(C)
S5

CP S3
S1 CH
VINA +
5pF
UNBUFFERED Z
IN S7 A
INPUT CH
S2
VINB -
5pF
CP S4

S6
2.28
Input Impedance Model for Buffered and
Unbuffered Input ADCs

ADC

ZIN R C

BUFFERED INPUT UNBUFFERED INPUT

 R and C are constant over frequency  R and C vary with both frequency and mode
 Typically: (track/hold)

R: 1 kW – 2 kW  Use Track mode R and C at the input frequency

C: 1.5 pF – 3 pF of interest

2.29
Unbuffered CMOS ADC (AD9236 12-Bit, 80 MSPS)
Series Input Impedance in Track Mode and Hold Mode

200 20

SERIES IMAGINARY IMPEDANCE (pF)

180 18
SERIES REAL IMPEDANCE (OHMS)

160 RS 16
ZIN
140 14
CS
120 12
REAL Z, HOLD
100 10

80 REAL Z, TRACK 8
IMAG Z, TRACK
60 6

40 4

20
IMAG Z, HOLD 2

0 0
0 100 200 300 400 500 600 700 800 900 1000

ANALOG INPUT FREQUENCY (MHz)

2.30
Basic Principles of Resonant Matching

SERIES RESONANT @ f (70MHz) PARALLEL RESONANT @ f (70MHz)

LS/2 ADC ADC

(69W) RS
ZIN ZIN LP RP CP
LS/2 (4.3pF) CS
(4kW) (4.3pF)

 Make XLS = XCS  Make XLP = XCP

1 1
 LS = (1.2µH)  LP =
(2 f )2 CS
(1.2µH)
(2 f )2 CP
 ZIN = RS + j0 @ f  ZIN = RP + j0 @ f

RP 4kW @ 70MHz
|ZIN| |ZIN| For AD9236

69W @ 70MHz
RS
For AD9236
f f

2.31
Before and After Adding
Matching Analog Antialiasing Filter Network

WITHOUT NETWORK WITH NETWORK

SAMPLING RATE = 76.8MSPS SAMPLING RATE = 76.8MSPS

INPUT = 70MHz INPUT = 70MHz
NOISE FLOOR = –84.3dBFS NOISE FLOOR = –95dBFS
THD = –63.9dBc THD = –76.8dBc
SFDR = 68.0dBc SFDR = 81.4dBc
SNR = 42.1dBFS SNR = 52.8dBFS

 SFDR Improved by 13.4 dB, SNR improved by 10.7 dB

 Note: Measured at maximum gain of 35 dB (gain code 255, high gain mode) using
76.8 MHz sampling clock

2.32
Effective Aperture Delay Time
Measured with Respect to ADC Input

+FS

ANALOG INPUT ZERO CROSSING

SINEWAVE
0V

–FS

+te ' –t e '

SAMPLING
CLOCK

t e'

33
Effects of Aperture Jitter
and Sampling Clock Jitter
dv Dt
Dv =
ANALOG dt
INPUT
dv
= SLOPE D v RMS = APERTURE JITTER ERROR
dt

NOMINAL
HELD
OUTPUT

D t RMS = APERTURE JITTER

HOLD

TRACK

34
Theoretical SNR and ENOB Due to Jitter
vs. Full-Scale Sinewave Analog Input Frequency

tj = 50fs
120 1
tj = 0.1ps
SNR = 20log 10 2 ft j 18

100 tj = 1ps 16

14
80 tj = 10ps
SNR
(dB) 12 ENOB

tj = 100ps 10
60
8

tj = 1ns
40 6

4
20
1 3 10 30 100

FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz)

35
Oscillator Requirements
vs. Resolution and Analog Input Frequency

tj
(ps)
Clock and Timing IC Jitter

90.0

85.0
Signal to Noise Ratio (SNR) in dB

80.0

75.0
50 fs
70.0

100 fs
65.0

200 fs
60.0

55.0 400 fs

50.0
800 fs
300 400 500
AIN = 200 MHz MHz MHz MHz
45.0
100 1000
Frequency of Fullscale Analog Input to ADC in MHz
37
SNR Plot for the AD9445 Evaluation Board
with Proper Decoupling

4.38
AD9445 Pinout Diagram

4.39
SNR Plot for an AD9445 Evaluation Board with
Caps Removed from the Analog Supply

4.40
SNR Plot for an AD9445 Evaluation Board with
Caps Removed from the Digital Supply

4.41
ADIsimADC

42
ADIsimADC

43
VisualAnalog™

44
SPI Controller

45
High Accuracy Sources

 Resolution to 1 ppm
 One microvolt out of 1 volt

 Everything matters
 External amplifiers – low offset, drift, noise
 Voltage reference – 1 ppm drift
 Layout and design

 Applications
 MRI – magnetic resonance imaging
 Precise gradient in magnetic field
 Test equipment

46
High Accuracy 18-Bit ±10 V Source

47
ADC References

 Input level compared to reference

 ADC accuracy is relative to that reference

 Internal reference
 Simplicity and lower cost
 Reference tuned to ADC performance
 Specifications all-inclusive

 External reference
 Can be chosen for higher absolute accuracy
 Allows common reference in multiple-ADC system
 Common reference for sensor driver and ADC

 Power supply as reference

 Lowest cost in most cases
 Noise is biggest issue
 Tolerance and drift may degrade accuracy

48
Voltage Reference Comparison

49
ADC References

50
Analog to Electronic Signal Processing

SENSOR AMP ADC

(INPUT)

DIGITAL
PROCESSOR

ACTUATOR AMP DAC

(OUTPUT)

51
DAC Signal Construction

SAMPLED
SIGNAL

RECONSTRUCTED
SIGNAL

1
fc t

IDEAL TRANSITION TRANSITION WITH TRANSITION WITH

DOUBLET GLITCH UNIPOLAR (SKEW) GLITCH

t t t

52
DAC sin x/x Roll Off
(Amplitude Normalized)
RECONSTRUCTED
SIGNAL

t
1
fc
1
f
–3.92dB sin
A A= fc
f
IMAGES
IMAGES fc
IMAGES

0 f

0.5fc fc 1.5fc 2fc 2.5fc 3fc

FS – FOUT FS + FOUT 2FS – FOUT 2FS + FOUT

53
LPF Required to Reject Image Frequency

54
Analog Filter Requirements for fo = 10 MHZ:
fc = 30 MSPS, and fc = 60 MSPS

A
ANALOG LPF
fCLOCK = 30MSPS
dB

fo
IMAGE
IMAGE IMAGE
IMAGE

10 20 30 40 50 60 70 80
FREQUENCY (MHz)
B

fCLOCK = 60MSPS

dB

fo ANALOG
LPF

IMAGE IMAGE

10 20 30 40 50 60 70 80

55
DAC Images (continued)

102
POWER

101

0 X X X
0 50 100 150 200 250
FREQUENCY

In the above example, FOUT = 0.45 3 Fs

As the DAC output (FOUT) approaches Nyquist frequency, the images come closer
together, making it extremely difficult to filter the image from the signal.

56
Interpolation

fSIGNAL fCLOCK = 2 x fSIGNAL fSIGNAL fCLOCK = 8 x fSIGNAL

 Maximum Output Frequency of Standard DAC is FCLOCK  2 (Nyquist Rate).

 In an Interpolating D/A Converter, Digital Interpolation Filters and a PLL Clock Multiplier Are
Used to Multiply the Input Data Rate to the DAC by a Factor of x Times the Clock Rate.

 Produces an Image at x Times FSIGNAL, Smoothing the Sine Function and Simplifying the
Filter Requirements and Digital Interface.

57
AD9775 TxDAC® 14-Bit CMOS DAC Core

5 31 31
31
BITS 1-5
CURRENT
DECODE
SWITCHES

5-TO-31
14 14-BIT I = 512 LSB
51-BIT
LATCH CURRENT
4 15 LATCH 15
15 OUTPUT
BITS 6-9
CURRENT
DECODE
SWITCHES FS =
I = 32 LSB 2mA-
4-TO-15 20mA
5 BINARY
5 5 5 CURRENT
SWITCHES
I = 1 LSB
CLOCK NOTE: Differential Outputs Not Shown

58
Oversampling Interpolating TxDAC®
Simplified Block Diagram

N N DIGITAL N N
LATCH INTERPOLATION LATCH DAC
FILTER

fc K•fc
PLL LPF

fo
TYPICA L APP LICATION: fc = 160MSPS
fo = 50MHz
K=2
Image Frequency = 320– 50 = 270MHz

59
AD9772: 2X Interpolation vs.
Nyquist DAC

Nyquist DAC AD9772 DAC

1st IMAGE
1st NEW IMAGE

IMAGES FILTERED BY
DIGITAL 2X
INTERPOLATION

60
What We Covered

 Data converters in the signal chain

 Basics of data conversion
 Dynamic signal processing
 Driving ADCs
 Input structures
 DACs for high speed and high resolution

61 Tweet it out! @ADI_News #ADIDC13

Design Resources Covered in This Session

 Design tools & resources:

Name Description URL

ADIsimADC Shows dynamic performance of ADCs in real
applications
Voltage Reference
Selection Wizard
Visual Analog
SPI Controller
 Ask technical questions and exchange ideas online in our
EngineerZone® Support Community
 Choose a technology area from the homepage:
 ez.analog.com
 Access the Design Conference community here:
 www.analog.com/DC13community

62 Tweet it out! @ADI_News #ADIDC13

Visit the 16-Bit 250 kSPS 8-Channel, Isolated Data
Acquisition System in the Exhibition Room

 Circuits from the Lab® CN0254 is

a cost effective, highly integrated
16-bit, 250 kSPS, 8-channel data
acquisition system that can
digitize ±10 V industrial level
signals. The circuit also provides
2500 V rms isolation between the
measurement circuit and the host
controller, and the entire circuit is
powered from a single isolated
PWM controlled 5 V supply.

This demo board is available for purchase:

www.analog.com/DC13-hardware

63 Tweet it out! @ADI_News #ADIDC13

16-Bit 250 kSPS 8-Channel Isolated Data
Acquisition System—CN0254

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The Data Conversion Handbook

The Data Conversion Handbook, edited by Walt Kester (Newnes,

2005), is written for design engineers who routinely use data
converters and related circuitry. Comprising Data Converter
History, Fundamentals of Sampled Data Systems, Data
Converter Architectures, Data Converter Process Technology,
Testing Data Converters, Interfacing to Data Converters, Data
Converter Support Circuits, Data Converter Applications, and
Hardware Design Techniques, it may be the ultimate expression
of product "augmentation" as it relates to data converters. The
last chapter discusses practical issues, including common pitfalls
and solutions related to the non-ideal properties of passive
components.
The Data Conversion Handbook can be purchased from your
favorite bookseller.

Individual chapters--or a zip file containing all chapters--of the original Basic Linear
Design seminar notes can be downloaded by selecting the appropriate links below
http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html

65
Linear Circuit Design Handbook

Linear Circuit Design Handbook, edited by Hank Zumbahlen

(Newnes, 2008), bridges the gap between circuit component
theory and practical circuit design. Effective analog circuit design
requires a strong understanding of core linear devices and how
they affect analog circuit design. This book provides complete
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designing linear circuits, and serves as a useful learning tool and
reference for design engineers involved in analog and mixed-
signal design. It features complete coverage of analog circuit
components for the practicing engineer; market-validated design
information for all major types of linear circuits; practical advice
on how to read op amp data sheets and how to choose off-the-
shelf op amps; printed circuit board design issues; and over 1000
figures, including working circuit diagrams. Analog Dialogue
readers can get a 20% discount when they order this book
directly from Newnes. Enter discount code 92222.

Individual chapters--or a zip file containing all chapters--of the original Basic Linear
Design seminar notes can be downloaded by selecting the appropriate links below
http://www.analog.com/library/analogDialogue/archives/43-09/linear_circuit_design_handbook.html

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