Tishk International University

Computer Engineering Department

Computer Organization CMPE 352/A
Lecture 6: 21-04-2019

Computer Organization:
Top Level View of Computer Function and
Interconnection

Dr. Rand Basil Alhashimie

[email protected]
Top Level of Computer

• Computer consists of:

• CPU
• Memory
• I/O interconnections

• These components are connected to achieve the main function of

the computer, which is to execute program.
Program Concept

• Hardwired systems are inflexible

• General purpose hardware can do different tasks, given correct

control signals.

• Instead of re-wiring, supply a new set of control signals

Hardware and Software
Approaches
What is a program?

• A sequence of steps

• For each step, an arithmetic or logical operation is done

• For each operation, a different set of control signals is needed

Function of Control Unit
• For each operation a unique code is provided
• e.g. ADD, MOVE
• A hardware segment accepts the code and issues the control signals

• We have a computer!
Components

• The Control Unit and the Arithmetic and Logic Unit constitute the
Central Processing Unit.

• Data and instructions need to get into the system and results out
• Input/output

• Temporary storage of code and results is needed

• Main memory
Von Neumann Architecture
• Data and instructions are stored in a single read–write memory.
• The contents of this memory are addressable by location, without regard to the
type of data contained there.
• Execution occurs in a sequential fashion (unless explicitly modified) from one
instruction to the next.
• A particular set of hardware will perform various functions on data depending
on control signals applied to the hardware.
Von Neumann Architecture

• How shall control signals be supplied? The answer is simple but subtle
(not easily grasped).

• The entire program is actually a sequence of steps. At each step, some

arithmetic or logical operation is performed on some data.

• Programming is now much easier. Instead of rewiring the hardware for

each new program, all we need to do is provide a new sequence of codes.
Von Neumann Architecture
• Each code is, in effect, an instruction, and part of the hardware interprets
each instruction and generates control signals.

• To distinguish this new method of programming, a sequence of codes or

instructions is called software.

• Figure 2 indicates two major components of the system: an instruction

interpreter and a module of general-purpose arithmetic and logic functions.
These two constitute the CPU.
Computer Components:
Top Level View
I/O Components
• Data and instructions must be put into the system. For this we need some sort
of input module.

• This module contains basic components for accepting data and instructions in
some form and converting them into an internal form of signals usable by the
system.

• A means of reporting results is needed, and this is in the form of an output

module. Taken together, these are referred to as I/O components.
Main Memory (Temporary Storage)
• An input device will bring instructions and data in sequentially. But a program is
not invariably executed sequentially; it may jump around (e.g., the IAS jump
instruction).

• Similarly, operations on data may require access to more than just one element
at a time in a predetermined sequence. Thus, there must be a place to store
temporarily both instructions and data.

• That module is called memory, or main memory, to distinguish it from external

storage or peripheral devices. Von Neumann pointed out that the same memory
could be used to store both instructions and data.
CPU Registers
• MAR (Memory Address Register)

• MBR (Memory Buffer Register)

• PC (Program Counter)

• IR (Instruction Register)

• AC (Accumulator-Temporary Register)

• I/O AR (Input-Output Address Register)

• I/O BR (Input-Output Buffer Register)

MAR and MBR (CPU Data Exchange)

• The CPU exchanges data with memory. For this purpose, it typically makes
use of two internal (to the CPU) registers:
• Memory address register (MAR), which specifies the address in memory
for the next read or write
• Memory buffer register (MBR), which contains the data to be written into
memory or receives the data read from memory.
I/O Address and Buffer Registers

• Similarly, an I/O address register (I/O AR) specifies a particular I/O

device.

• An I/O buffer (I/O BR) register is used for the exchange of data
between an I/O module and the CPU.
Memory Locations and I/O
• A memory module consists of a set of locations, defined by sequentially
numbered addresses.

• Each location contains a binary number that can be interpreted as either an

instruction or data.

• An I/O module transfers data from external devices to CPU and memory, and
vice versa. It contains internal buffers for temporarily holding these data until
they can be sent on.
Computer Function
• The basic function performed by a computer is execution of a program,
which consists of a set of instructions stored in memory.

• The processor does the actual work by executing instructions specified in

the program.

• In its simplest form, instruction processing consists of two steps:

• The processor reads (fetches) instructions from memory one at a time.

• Executes each instruction.

Program Execution
• Program execution consists of repeating the process of instruction fetch and
instruction execution.

• The instruction execution may involve several operations and depends on the
nature of the instruction. The processing required for a single instruction is
called an instruction cycle.

• The instruction cycle involves two steps which are referred to as the fetch
cycle and the execute cycle.
Program Execution Stop

Program execution halts only:

• if the machine is turned off,

• some sort of unrecoverable error occurs,
• or a program instruction that halts the computer is
encountered.
Instruction Cycle: Fetch and Execute
• Two steps:
• Fetch
• Execute
Program Counter (PC)
• At the beginning of each instruction cycle, the processor fetches an
instruction from memory. In a typical processor, a register called the
program counter (PC) holds the address of the instruction to be fetched
next.

• Unless told otherwise, the processor always increments the PC after each
instruction fetch so that it will fetch the next instruction in sequence (i.e., the
instruction located at the next higher memory address).
Fetch Cycle
• Program Counter (PC) holds address of next instruction to fetch

• Processor fetches instruction from memory location pointed to

by PC

• Increment PC
• Unless told otherwise

• Instruction loaded into Instruction Register (IR)

• Processor interprets instruction and performs required actions

Execute Cycle
• Processor-memory
• data transfer between CPU and main memory
• Processor I/O
• Data transfer between CPU and I/O module
• Data processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations
• e.g. jump
• Combination of above
Example of Program Execution
Example of Program Execution A
1. The PC contains 300, the address of the first instruction. This instruction (the
value 1940 in hexadecimal) is loaded into the instruction register IR.
2. Then the PC is incremented. Note that this process involves the use of a
memory address register (MAR) and a memory buffer register (MBR). For
simplicity, these intermediate registers are ignored.

3. The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to be
loaded. The remaining 12 bits (three hexadecimal digits) specify the address
(940) from which data are to be loaded.
Example of Program Execution B

4. The next instruction (5941) is fetched from location 301, and the PC is
incremented.

5. The old contents of the AC and the contents of location 941 are added, and
the result is stored in the AC.

6. The next instruction (2941) is fetched from location 302, and the PC is
incremented.

7. The contents of the AC are stored in location 941.

Opcode and Address code
•
Instruction format (in Hexadecimals)

The hexadecimal notations used in the previous example

help the designer to recognize opcodes and address codes.
The computer only uses binary digits.
Instruction Cycle State Diagram
Steps of the Instruction Cycle
• Instruction fetch (if): Read instruction from its memory location into the processor.

• Instruction operation decoding (iod): Analyze instruction to determine type of

operation to be performed and operand(s) to be used.

• Operand address calculation (oac): If the operation involves reference to an

operand in memory or available via I/O, then determine the address of the operand.

• Operand fetch (of): Fetch the operand from memory or read it in from I/O.

• Data operation (do): Perform the operation indicated in the instruction.

• Operand store (os): Write the result into memory or out to I/O.
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing
• Program
• e.g. overflow, division by zero

• Timer
• Generated by internal processor timer
• Used in pre-emptive multitasking

• I/O
• from I/O controller

• Hardware failure
• e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
• Suspend execution of current program
• Save context
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) - State Diagram
Multiple Interrupts
• Disable interrupts
• Processor will ignore further interrupts whilst processing one interrupt

• Interrupts remain pending and are checked after first interrupt has been
processed

• Interrupts handled in sequence as they occur

• Define priorities
• Low priority interrupts can be interrupted by higher priority interrupts

• When higher priority interrupt has been processed, processor returns to

previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Connecting

• All the units must be connected

• Different type of connection for different type of unit

• Memory

• Input/Output

• CPU
Computer Modules
Memory Connection

• Receives and sends data

• Receives addresses (of locations)

• Receives control signals

• Read

• Write

• Timing
Input/Output Connection(1)
• Similar to memory from computer’s viewpoint

• Output
• Receive data from computer

• Send data to peripheral

• Input
• Receive data from peripheral

• Send data to computer

Input/Output Connection(2)
• Receive control signals from computer

• Send control signals to peripherals

• e.g. spin disk

• Receive addresses from computer

• e.g. port number to identify peripheral

• Send interrupt signals (control)

CPU Connection
• Reads instruction and data

• Writes out data (after processing)

• Sends control signals to other units

• Receives (& acts on) interrupts

Buses
• There are a number of possible interconnection systems

• Single and multiple BUS structures are most common

• e.g. Control/Address/Data bus (PC)

• e.g. Unibus (DEC-PDP)

What is a Bus?
• A communication pathway connecting two or more devices

• Usually broadcast

• Often grouped
• A number of channels in one bus

• e.g. 32 bit data bus is 32 separate single bit channels

• Power lines may not be shown

Data Bus

• Carries data
• Remember that there is no difference between “data” and “instruction”
at this level

• Width is a key determinant of performance

• 8, 16, 32, 64 bit
Address bus

• Identify the source or destination of data

• e.g. CPU needs to read an instruction (data) from a given

location in memory

• Bus width determines maximum memory capacity of system

• e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus
• Control and timing information
• Memory read/write signal

• Interrupt request

• Clock signals
Bus Interconnection Scheme
Big and Yellow?

• What do buses look like?

• Parallel lines on circuit boards

• Ribbon cables

• Strip connectors on motherboards

• e.g. PCI

• Sets of wires
Physical Realization of Bus Architecture
Single Bus Problems

• Lots of devices on one bus leads to:

• Propagation delays
• Long data paths mean that co-ordination of bus use can adversely affect
performance

• If aggregate data transfer approaches bus capacity

• Most systems use multiple buses to overcome these problems

Traditional (ISA)
(with cache)
High Performance Bus
Bus Types
• Dedicated
• Separate data & address lines

• Multiplexed
• Shared lines

• Address valid or data valid control line

• Advantage - fewer lines

• Disadvantages
• More complex control

• Ultimate performance
Bus Arbitration

• More than one module controlling the bus

• e.g. CPU and DMA controller

• Only one module may control bus at one time

• Arbitration may be centralised or distributed

Centralised or Distributed Arbitration
• Centralised
• Single hardware device controlling bus access
• Bus Controller

• Arbiter

• May be part of CPU or separate

• Distributed
• Each module may claim the bus

• Control logic on all modules

Timing

• Coordination of events on bus

• Synchronous
• Events determined by clock signals

• Control Bus includes clock line

• A single 1-0 is a bus cycle

• All devices can read clock line

• Usually sync on leading edge

• Usually a single cycle for an event

Synchronous Timing Diagram
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
PCI Bus
• Peripheral Component Interconnection
• Intel released to public domain
• 32 or 64 bit
• 50 lines
PCI Bus Lines (required)
• Systems lines
• Including clock and reset
• Address & Data
• 32 time mux lines for address/data
• Interrupt & validate lines
• Interface Control
• Arbitration
• Not shared
• Direct connection to PCI bus arbiter
• Error lines
PCI Bus Lines (Optional)
• Interrupt lines
• Not shared
• Cache support
• 64-bit Bus Extension
• Additional 32 lines
• Time multiplexed
• 2 lines to enable devices to agree to use 64-bit transfer
• JTAG/Boundary Scan
• For testing procedures
PCI Commands
• Transaction between initiator (master) and target
• Master claims bus
• Determine type of transaction
• e.g. I/O read/write
• Address phase
• One or more data phases
PCI Read Timing Diagram
PCI Bus Arbiter
PCI Bus Arbitration
End of Chapter - 3