CUDA

In computing, CUDA is a proprietary[2] parallel computing platform and application programming interface
CUDA
(API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-
purpose processing, an approach called general-purpose computing on GPUs. CUDA was created by Nvidia
in 2006.[3] When it was first introduced, the name was an acronym for Compute Unified Device
Architecture,[4] but Nvidia later dropped the common use of the acronym and now rarely expands it.[5]

CUDA is a software layer that gives direct access to the GPU's virtual instruction set and parallel
computational elements for the execution of compute kernels.[6] In addition to drivers and runtime kernels,
the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their
Developer(s) Nvidia
applications.
Initial release February 16, 2007[1]
CUDA is designed to work with programming languages such as C, C++, Fortran and Python. This Stable release 12.8 / January 2025
accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior
Operating system Windows, Linux
APIs like Direct3D and OpenGL, which require advanced skills in graphics programming.[7] CUDA-powered
GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL.[8][6] Platform Supported GPUs
Type GPGPU
License Proprietary
Background Website developer.nvidia.com
/cuda-zone (https://develop
The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time
er.nvidia.com/cuda-zone)
high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-
core systems allowing efficient manipulation of large blocks of data. This design is more effective than
general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

cryptographic hash functions

machine learning
molecular dynamics simulations
physics engines
Ian Buck, while at Stanford in 2000, created an 8K gaming rig using 32 GeForce cards, then obtained a DARPA grant to perform general purpose parallel
programming on GPUs. He then joined Nvidia, where since 2004 he has been overseeing CUDA development. In pushing for CUDA, Jensen Huang aimed for
the Nvidia GPUs to become a general hardware for scientific computing. CUDA was released in 2007. Around 2015, the focus of CUDA changed to neural
networks.[9]

Ontology
The following table offers a non-exact description for the ontology of CUDA framework.

The ontology of CUDA framework

computation
memory memory (code, or computation computation
(code
(hardware) variable scoping) (hardware) (code semantics)
syntax)

RAM non-CUDA variables host program one routine call

VRAM,
simultaneous call of the same subroutine
GPU L2 global, const, texture device grid
on many processors
cache

GPU L1
local, shared SM ("streaming multiprocessor") block individual subroutine call
cache

warp = 32 threads SIMD instructions

GPU L0
thread (aka. "SP", "streaming processor", "cuda core", but analogous to individual scalar ops within a
cache,
these names are now deprecated) vector op
register

Programming abilities
The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to
industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc,
Nvidia's LLVM-based C/C++ compiler, or by clang itself.[10] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler
from The Portland Group. Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the
Khronos Group's OpenCL,[11] Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP.[12] Third party wrappers are also available for Python,
Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.
In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations
(physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also
been used to accelerate non-graphical applications in computational biology, cryptography and other fields
by an order of magnitude or more.[13][14][15][16][17]

CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API
(CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for
Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,[18] which supersedes the
beta released February 14, 2008.[19] CUDA works with all Nvidia GPUs from the G8x series onwards,
including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

cuBLAS – CUDA Basic Linear Algebra Subroutines library

CUDART – CUDA Runtime library
cuFFT – CUDA Fast Fourier Transform library Example of CUDA processing flow
cuRAND – CUDA Random Number Generation library 1. Copy data from main memory to GPU
cuSOLVER – CUDA based collection of dense and sparse direct solvers memory
cuSPARSE – CUDA Sparse Matrix library 2. CPU initiates the GPU compute kernel
NPP – NVIDIA Performance Primitives library 3. GPU's CUDA cores execute the kernel
nvGRAPH – NVIDIA Graph Analytics library in parallel
NVML – NVIDIA Management Library 4. Copy the resulting data from GPU
NVRTC – NVIDIA Runtime Compilation library for CUDA C++ memory to main memory
CUDA 8.0 comes with these other software components:

nView – NVIDIA nView Desktop Management Software

NVWMI – NVIDIA Enterprise Management Toolkit
GameWorks PhysX – is a multi-platform game physics engine
CUDA 9.0–9.2 comes with these other components:

CUTLASS 1.0 – custom linear algebra algorithms,

NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK
CUDA 10 comes with these other components:

nvJPEG – Hybrid (CPU and GPU) JPEG processing

CUDA 11.0–11.8 comes with these other components:[20][21][22][23]

CUB is new one of more supported C++ libraries

MIG multi instance GPU support
nvJPEG2000 – JPEG 2000 encoder and decoder

Advantages
CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

Scattered reads – code can read from arbitrary addresses in memory.

Unified virtual memory (CUDA 4.0 and above)
Unified memory (CUDA 6.0 and above)
Shared memory – CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed
cache, enabling higher bandwidth than is possible using texture lookups.[24]
Faster downloads and readbacks to and from the GPU
Full support for integer and bitwise operations, including integer texture lookups

Limitations
Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.[25] This was not
always the case. Earlier versions of CUDA were based on C syntax rules.[26] As with the more general case of compiling C code with a C++
compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA
not having access to OpenGL memory.
Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly
alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches
in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD
execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during
ray tracing).
No emulation or fallback functionality is available for modern revisions.
Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device
limitations.
C++ run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
 In single-precision on first generation CUDA compute capability 1.x devices, denormal numbers are unsupported and are instead flushed to
zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math.
Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754
compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting
compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.[27]
Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia as it is proprietary.[28][2] Attempts to implement CUDA on other GPUs
include:

Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to run TensorFlow.[29][30][31]
CU2CL: Convert CUDA 3.2 C++ to OpenCL C.[32]
GPUOpen HIP: A thin abstraction layer on top of CUDA and ROCm intended for AMD and Nvidia GPUs. Has a conversion tool for
importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.[33] The developer,
Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither
company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to
release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.[34]
chipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.[35]

Example
This example code in C++ loads a texture from an image into an array on the GPU:

texture<float, 2, cudaReadModeElementType> tex;

void foo()
{
cudaArray* cu_array;

// Allocate array
cudaChannelFormatDesc description = cudaCreateChannelDesc<float>();
cudaMallocArray(&cu_array, &description, width, height);

// Copy image data to array

cudaMemcpyToArray(cu_array, image, width*height*sizeof(float), cudaMemcpyHostToDevice);

// Set texture parameters (default)

tex.addressMode[0] = cudaAddressModeClamp;
tex.addressMode[1] = cudaAddressModeClamp;
tex.filterMode = cudaFilterModePoint;
tex.normalized = false; // do not normalize coordinates

// Bind the array to the texture

cudaBindTextureToArray(tex, cu_array);

// Run kernel
dim3 blockDim(16, 16, 1);
dim3 gridDim((width + blockDim.x - 1)/ blockDim.x, (height + blockDim.y - 1) / blockDim.y, 1);
kernel<<< gridDim, blockDim, 0 >>>(d_data, height, width);

// Unbind the array from the texture

cudaUnbindTexture(tex);
} //end foo()

__global__ void kernel(float* odata, int height, int width)

{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < width && y < height) {
float c = tex2D(tex, x, y);
odata[y*width+x] = c;
}
}

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from
PyCUDA.[36]

import pycuda.compiler as comp

import pycuda.driver as drv
import numpy
import pycuda.autoinit

mod = comp.SourceModule(
"""
__global__ void multiply_them(float *dest, float *a, float *b)
{
const int i = threadIdx.x;
dest[i] = a[i] * b[i];
}
"""
)

multiply_them = mod.get_function("multiply_them")

a = numpy.random.randn(400).astype(numpy.float32)
b = numpy.random.randn(400).astype(numpy.float32)

dest = numpy.zeros_like(a)
multiply_them(drv.Out(dest), drv.In(a), drv.In(b), block=(400, 1, 1))

print(dest - a * b)

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.[37]
 import numpy
from pycublas import CUBLASMatrix

A = CUBLASMatrix(numpy.mat([[1, 2, 3], [4, 5, 6]], numpy.float32))

B = CUBLASMatrix(numpy.mat([[2, 3], [4, 5], [6, 7]], numpy.float32))
C = A * B
print(C.np_mat())

while CuPy directly replaces NumPy:[38]

import cupy

a = cupy.random.randn(400)
b = cupy.random.randn(400)

dest = cupy.zeros_like(a)

print(dest - a * b)

GPUs supported
Supported CUDA compute capability versions for CUDA SDK version and microarchitecture (by code name):

Compute capability (CUDA SDK support vs. microarchitecture)

CUDA SDK Kepler Kepler Ada
Tesla Fermi Maxwell Pascal Volta Turing Ampere Hopper Blackwell
version(s) (early) (late) Lovelace

1.0[39] 1.0 – 1.1

1.1 1.0 – 1.1+x

2.0 1.0 – 1.1+x

2.1 – 2.3.1[40][41][42][43] 1.0 – 1.3

[44][45] 1.0 2.0
3.0 – 3.1

3.2[46] 1.0 2.1

4.0 – 4.2 1.0 2.1

5.0 – 5.5 1.0 3.5

6.0 1.0 3.2 3.5

6.5 1.1 3.7 5.x

7.0 – 7.5 2.0 5.x

8.0 2.0 6.x

9.0 – 9.2 3.0 7.0 – 7.2

10.0 – 10.2 3.0 7.5

[47] 3.5 8.0
11.0

11.1 – 11.4[48] 3.5 8.6

[49] 3.5 8.7
11.5 – 11.7.1
[50] 3.5 8.9 9.0
11.8
12.0 – 12.6 5.0 9.0

12.8 5.0 12.0

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA compute capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):
 Compute capability, GPU semiconductors and Nvidia GPU board products
Compute Tegra,
Micro-
capability GPUs GeForce Quadro, NVS Tesla/Datacenter Jetson,
architecture
(version) DRIVE
GeForce 8800 Ultra, Quadro FX 5600,
GeForce 8800 GTX, Quadro FX 4600, Tesla C870, Tesla D870, Tesla
1.0 G80
GeForce 8800 Quadro Plex 2100 S870
GTS(G80) S4
Quadro FX 4700
X2, Quadro FX
3700, Quadro FX
1800, Quadro FX
1700, Quadro FX
580, Quadro FX
570, Quadro FX
470, Quadro FX
380, Quadro FX
370, Quadro FX
370 Low Profile,
Quadro NVS 450,
Quadro NVS 420,
GeForce GTS 250, Quadro NVS 290,
GeForce 9800 GX2, Quadro NVS 295,
GeForce 9800 GTX, Quadro Plex 2100
GeForce 9800 GT, D4,
GeForce 8800 Quadro FX
GTS(G92), GeForce 3800M, Quadro
8800 GT, GeForce FX 3700M,
9600 GT, GeForce Quadro FX
9500 GT, GeForce 3600M, Quadro
G92, G94, G96, G98, G84,
1.1 9400 GT, GeForce FX 2800M,
G86
8600 GTS, GeForce Quadro FX
8600 GT, GeForce 2700M, Quadro
8500 GT, FX 1700M,
GeForce G110M, Quadro FX
GeForce 9300M GS, 1600M, Quadro
GeForce 9200M GS, FX 770M, Quadro
GeForce 9100M G, FX 570M, Quadro
GeForce 8400M GT, FX 370M, Quadro
GeForce G105M FX 360M, Quadro
Tesla
NVS 320M,
Quadro NVS
160M, Quadro
NVS 150M,
Quadro NVS
140M, Quadro
NVS 135M,
Quadro NVS
130M, Quadro
NVS 450, Quadro
NVS 420,[51]
Quadro NVS 295
GeForce GT 340*,
GeForce GT 330*,
GeForce GT 320*,
GeForce 315*, GeForce Quadro FX 380
310*, GeForce GT 240, Low Profile,
GeForce GT 220, Quadro FX
GeForce 210, 1800M, Quadro
GeForce GTS 360M, FX 880M, Quadro
1.2 GT218, GT216, GT215
GeForce GTS 350M, FX 380M,
GeForce GT 335M, Nvidia NVS 300,
GeForce GT 330M, NVS 5100M, NVS
GeForce GT 325M, 3100M, NVS
GeForce GT 240M, 2100M, ION
GeForce G210M,
GeForce 310M,
GeForce 305M
Quadro FX 5800,
Quadro FX 4800,
GeForce GTX 295,
Quadro FX 4800
GTX 285, GTX 280, Tesla C1060, Tesla S1070,
1.3 GT200, GT200b for Mac, Quadro
GeForce GTX 275, Tesla M1060
FX 3800, Quadro
GeForce GTX 260
CX, Quadro Plex
2200 D2
Fermi Quadro 6000,
GeForce GTX 590,
Quadro 5000,
GeForce GTX 580,
Quadro 4000,
GeForce GTX 570, Tesla C2075, Tesla
Quadro 4000 for
2.0 GF100, GF110 GeForce GTX 480, C2050/C2070, Tesla
Mac, Quadro Plex
GeForce GTX 470, M2050/M2070/M2075/M2090
7000,
GeForce GTX 465,
Quadro 5010M,
GeForce GTX 480M
Quadro 5000M
 GeForce GTX 560 Ti,
GeForce GTX 550 Ti,
GeForce GTX 460,
GeForce GTS 450,
GeForce GTS 450*,
GeForce GT 640
(GDDR3), GeForce GT
630, GeForce GT 620,
GeForce GT 610,
GeForce GT 520,
GeForce GT 440,
GeForce GT 440*,
GeForce GT 430,
GeForce GT 430*,
GeForce GT 420*,
GeForce GTX 675M,
GeForce GTX 670M, Quadro 2000,
GeForce GT 635M, Quadro 2000D,
GeForce GT 630M, Quadro 600,
GeForce GT 625M, Quadro 4000M,
GF104, GF106 GF108, GeForce GT 720M, Quadro 3000M,
2.1 GF114, GF116, GF117, GeForce GT 620M, Quadro 2000M,
GF119 GeForce 710M, Quadro 1000M,
GeForce 610M, NVS 310, NVS
GeForce 820M, 315, NVS 5400M,
GeForce GTX 580M, NVS 5200M, NVS
GeForce GTX 570M, 4200M
GeForce GTX 560M,
GeForce GT 555M,
GeForce GT 550M,
GeForce GT 540M,
GeForce GT 525M,
GeForce GT 520MX,
GeForce GT 520M,
GeForce GTX 485M,
GeForce GTX 470M,
GeForce GTX 460M,
GeForce GT 445M,
GeForce GT 435M,
GeForce GT 420M,
GeForce GT 415M,
GeForce 710M,
GeForce 410M
GeForce GTX 770,
GeForce GTX 760,
GeForce GT 740,
GeForce GTX 690,
GeForce GTX 680,
GeForce GTX 670,
Quadro K5000,
GeForce GTX 660 Ti,
Quadro K4200,
GeForce GTX 660,
Quadro K4000,
GeForce GTX 650 Ti
Quadro K2000,
BOOST, GeForce GTX
Quadro K2000D,
650 Ti, GeForce GTX
Quadro K600,
650,
Quadro K420,
GeForce GTX 880M,
Quadro K500M,
GeForce GTX 870M,
Quadro K510M,
GeForce GTX 780M,
Quadro K610M,
GeForce GTX 770M,
Quadro K1000M, Tesla K10, GRID K340, GRID
3.0 GK104, GK106, GK107 GeForce GTX 765M,
Quadro K2000M, K520, GRID K2
GeForce GTX 760M,
Quadro K1100M,
GeForce GTX 680MX,
Quadro K2100M,
GeForce GTX 680M,
Quadro K3000M,
GeForce GTX 675MX,
Quadro K3100M,
GeForce GTX 670MX,
Quadro K4000M,
GeForce GTX 660M,
Quadro K5000M,
GeForce GT 750M,
Quadro K4100M,
GeForce GT 650M,
Quadro K5100M,
Kepler GeForce GT 745M,
NVS 510, Quadro
GeForce GT 645M,
410
GeForce GT 740M,
GeForce GT 730M,
GeForce GT 640M,
GeForce GT 640M LE,
GeForce GT 735M,
GeForce GT 730M
Tegra K1,
3.2 GK20A
Jetson TK1
GeForce GTX Titan Z,
GeForce GTX Titan
Black, GeForce GTX
Titan, GeForce GTX
780 Ti, GeForce GTX
780, GeForce GT 640
Quadro K6000, Tesla K40, Tesla K20x, Tesla
3.5 GK110, GK208 (GDDR5), GeForce GT
Quadro K5200 K20
630 v2, GeForce GT
730, GeForce GT 720,
GeForce GT 710,
GeForce GT 740M (64-
bit, DDR3), GeForce
GT 920M
3.7 GK210 Tesla K80
5.0 Maxwell GM107, GM108 GeForce GTX 750 Ti, Quadro K1200, Tesla M10
GeForce GTX 750, Quadro K2200,
GeForce GTX 960M, Quadro K620,
GeForce GTX 950M, Quadro M2000M,
 GeForce 940M, Quadro M1000M,
GeForce 930M, Quadro M600M,
GeForce GTX 860M, Quadro K620M,
GeForce GTX 850M, NVS 810
GeForce 845M,
GeForce 840M,
GeForce 830M
GeForce GTX Titan X, Quadro M6000
GeForce GTX 980 Ti, 24GB, Quadro
GeForce GTX 980, M6000, Quadro
GeForce GTX 970, M5000, Quadro
GeForce GTX 960, M4000, Quadro Tesla M4, Tesla M40, Tesla
5.2 GM200, GM204, GM206
GeForce GTX 950, M2000, Quadro M6, Tesla M60
GeForce GTX 750 SE, M5500,
GeForce GTX 980M, Quadro M5000M,
GeForce GTX 970M, Quadro M4000M,
GeForce GTX 965M Quadro M3000M
Tegra X1,
Jetson TX1,
5.3 GM20B Jetson Nano,
DRIVE CX,
DRIVE PX
6.0 GP100 Quadro GP100 Tesla P100
Quadro P6000,
Quadro P5000,
Nvidia TITAN Xp, Titan
Quadro P4000,
X,
Quadro P2200,
GeForce GTX 1080 Ti,
Quadro P2000,
GTX 1080, GTX 1070
Quadro P1000,
Ti, GTX 1070, GTX
Quadro P400,
GP102, GP104, GP106, 1060,
6.1 Quadro P500, Tesla P40, Tesla P6, Tesla P4
Pascal GP107, GP108 GTX 1050 Ti, GTX
Quadro P520,
1050, GT 1030, GT
Quadro P600,
1010,
Quadro P5000
MX350, MX330,
(mobile), Quadro
MX250, MX230,
P4000 (mobile),
MX150, MX130, MX110
Quadro P3000
(mobile)
Tegra X2, Jetson TX2,
6.2 GP10B[52] DRIVE PX 2
7.0 GV100 NVIDIA TITAN V Quadro GV100 Tesla V100, Tesla V100S
Tegra Xavier,
Volta GV10B[53] Jetson Xavier NX,
Jetson AGX Xavier,
7.2 GV11B[54][55] DRIVE AGX Xavier,
DRIVE AGX Pegasus,
Clara AGX
Quadro RTX
NVIDIA TITAN RTX,
8000, Quadro
GeForce RTX 2080 Ti,
RTX 6000,
RTX 2080 Super, RTX
Quadro RTX
2080, RTX 2070 Super,
5000, Quadro
RTX 2070, RTX 2060
RTX 4000, T1000,
TU102, TU104, TU106, Super, RTX 2060
7.5 Turing T600, T400 Tesla T4
TU116, TU117 12GB, RTX 2060,
T1200 (mobile),
GeForce GTX 1660 Ti,
T600 (mobile),
GTX 1660 Super, GTX
T500 (mobile),
1660, GTX 1650 Super,
Quadro T2000
GTX 1650, MX550,
(mobile), Quadro
MX450
T1000 (mobile)
8.0 GA100 A100 80GB, A100 40GB, A30
RTX A6000, RTX
GeForce RTX 3090 Ti, A5500, RTX
RTX 3090, RTX 3080 A5000, RTX
Ti, RTX 3080 12GB, A4500, RTX
RTX 3080, RTX 3070 A4000, RTX
GA102, GA103, GA104, Ti, RTX 3070, RTX A2000
8.6 A40, A16, A10, A2
GA106, GA107 3060 Ti, RTX 3060, RTX A5000
RTX 3050, RTX 3050 Ti (mobile), RTX
Ampere (mobile), RTX 3050 A4000 (mobile),
(mobile), RTX 2050 RTX A3000
(mobile), MX570 (mobile), RTX
A2000 (mobile)
Jetson Orin Nano,
Jetson Orin NX,
Jetson AGX Orin,
8.7 GA10B
DRIVE AGX Orin,
DRIVE AGX Pegasus OA,
Clara Holoscan
GeForce RTX 4090, RTX 6000 Ada,
RTX 4080 Super, RTX RTX 5880 Ada,
4080, RTX 4070 Ti RTX 5000 Ada,
Ada AD102, AD103, AD104, Super, RTX 4070 Ti, RTX 4500 Ada,
8.9 L40S, L40, L20, L4, L2
Lovelace[56] AD106, AD107 RTX 4070 Super, RTX RTX 4000 Ada,
4070, RTX 4060 Ti, RTX 4000 SFF,
RTX 4060, RTX 4050 RTX 3500 Ada
(mobile) (mobile)
9.0 Hopper GH100 H200, H100
 10.0 GB100 B200, B100, GB200 (?)
10.1 G10 (?) GB10 (?)
GeForce RTX 5090,
Blackwell GB202, GB203, GB205,
12.0 RTX 5080, RTX 5070 B40
GB206, GB207
Ti, RTX 5070
Jetson Thor (?), AGX Thor
12.x (?)
(?), Drive Thor (?)
Compute Tegra,
Micro-
capability GPUs GeForce Quadro, NVS Tesla/Datacenter Jetson,
architecture
(version) DRIVE

* – OEM-only products

Version features and specifications

Compute capability (version)

Feature support (unlisted features are supported for all compute
capabilities) 1.0, 1.2, 3.5, 3.7, 5.x, 6.x, 9.0, 10.x,
2.x 3.0 3.2 7.5 8.x
1.1 1.3 7.0, 7.2 12.0
Warp vote functions (__all(), __any()) No Yes
Warp vote functions (__ballot())
Memory fence functions (__threadfence_system())
Synchronization functions (__syncthreads_count(), __syncthreads_and(),
No Yes
__syncthreads_or())
Surface functions
3D grid of thread blocks
Warp shuffle functions
No Yes
Unified memory programming
Funnel shift No Yes
Dynamic parallelism No Yes

Uniform Datapath[57] No Yes

Hardware-accelerated async-copy
Hardware-accelerated split arrive/wait barrier
No Yes
Warp-level support for reduction ops
L2 cache residency management
DPX instructions for accelerated dynamic programming
Distributed shared memory
No Yes
Thread block cluster
Tensor memory accelerator (TMA) unit
3.5, 3.7, 5.x, 6.x, 9.0, 10.x,
Feature support (unlisted features are supported for all compute 1.0,1.1 1.2,1.3 2.x 3.0 3.2 7.5 8.x
7.0, 7.2 12.0
capabilities)
Compute capability (version)
[58]

Data types

Floating-point types

Storage Length
Used Length
Supported vector Bits Sign Exponent Mantissa
Data type Bits Comments
types (complete Bits Bits Bits
(single value)
vector)
E2M1 = FP4 e2m1x2 / e2m1x4 8 / 16 4 1 2 1
E2M3 = FP6
e2m3x2 / e2m3x4 16 / 32 6 1 2 3
variant
E3M2 = FP6
e3m2x2 / e3m2x4 16 / 32 6 1 3 2
variant
UE4M3 ue4m3 8 7 0 4 3 Used for scaling (E2M1 only)
E4M3 = FP8 e4m3 / e4m3x2 /
8 / 16 / 32 8 1 4 3
variant e4m3x4
E5M2 = FP8 e5m2 / e5m2x2 /
8 / 16 / 32 8 1 5 2 Exponent/range of FP16, fits into 8 bits
variant e5m2x4
Used for scaling (any FP4 or FP6 or FP8
UE8M0 ue8m0x2 16 8 0 8 0
format)
FP16 f16 / f16x2 16 / 32 16 1 5 10
BF16 bf16 / bf16x2 16 / 32 16 1 8 7 Exponent/range of FP32, fits into 16 bits
Exponent/range of FP32,
TF32 tf32 32 19 1 8 10
mantissa/precision of FP16
FP32 f32 / f32x2 32 / 64 32 1 8 23
FP64 f64 64 64 1 11 52

Version support

Supported since Supported since

Data type Basic Operations Supported since Atomic Operations
for global memory for shared memory
8-bit integer
loading, storing, conversion 1.0 — —
signed/unsigned
16-bit integer
general operations 1.0 atomicCAS() 3.5
signed/unsigned
32-bit integer
general operations 1.0 atomic functions 1.1 1.2
signed/unsigned
64-bit integer
general operations 1.0 atomic functions 1.2 2.0
signed/unsigned
any 128-bit trivially copyable type general operations No atomicExch, atomicCAS 9.0
addition, subtraction, half2 atomic addition 6.0
16-bit floating point
multiplication, comparison, 5.3
FP16 atomic addition 7.0
warp shuffle functions, conversion
addition, subtraction,
16-bit floating point
multiplication, comparison, 8.0 atomic addition 8.0
BF16
warp shuffle functions, conversion
atomicExch() 1.1 1.2
32-bit floating point general operations 1.0
atomic addition 2.0
32-bit floating point float2 and float4 general operations No atomic addition 9.0
64-bit floating point general operations 1.3 atomic addition 6.0
Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[59]

Tensor cores

FMA per
cycle per 7.5 7.5 8.6 8.6 8.9 8.9
tensor Supported since 7.0 7.2 8.0 8.7 9.0
Workstation Desktop Workstation Desktop Desktop Workstation
core[60]

1st 1st
For dense For sparse
Data Type Gen Gen? 2nd Gen (8x/SM) 3rd Gen (4x/SM) 4th Gen (4x/SM)
matrices matrices
(8x/SM) (8x/SM)
1-bit values 8.0 as
No
(AND) experimental
No 4096 2048
1-bit values
1024
(XOR) 7.5–8.9 as
No Deprec
4-bit experimental 8.0–8.9 as
256 1024 512
integers experimental
4-bit
floating
10.0 No 4
point FP4
(E2M1)
6-bit
floating
point FP6 10.0 No 2
(E3M2 and
E2M3)
8-bit
7.2 8.0 No 128 128 512 256
integers
8-bit
floating
point FP8
(E4M3 and 256
E5M2) with
FP16
1024 2
accumulate
8.9 No
8-bit
floating
point FP8
(E4M3 and 128
E5M2) with
FP32
accumulate
16-bit
floating
point FP16 64 128
with FP16
accumulate
7.0 8.0 64 64
16-bit
floating
point FP16 256 512 1
with FP32
accumulate
64 128
16-bit
floating
32
point BF16 64[62]
with FP32
accumulate
7.5[61] 8.0
32-bit (19
No speed tbd
bits used)
128 32 64 256
floating (32?)[62]
point TF32
64-bit
floating 8.0 No No 16 speed tbd 32
point

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[63][64] [65] [66] [67] [68]

Tensor Core Composition 7.0 7.2, 7.5 8.0, 8.6 8.7 8.9 9.0
[69][70][71][72] 4 (8) 8 (16) 4 (8) 16 (32)
Dot Product Unit Width in FP16 units (in bytes)

Dot Product Units per Tensor Core 16 32

Tensor Cores per SM partition 2 1
[73] [74] 256 512 256 1024
Full throughput (Bytes/cycle) per SM partition

FP Tensor Cores: Minimum cycles for warp-wide matrix calculation 8 4 8

FP Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)[75] 2048

INT Tensor Cores: Minimum cycles for warp-wide matrix calculation No 4

INT Tensor Cores: Minimum Matrix Shape for full throughput (Bytes) No 1024 2048 1024
[76][77][78][79]
 FP64 Tensor Core Composition 8.0 8.6 8.7 8.9 9.0
Dot Product Unit Width in FP64 units (in bytes) 4 (32) tbd 4 (32)
Dot Product Units per Tensor Core 4 tbd 8
Tensor Cores per SM partition 1

Full throughput (Bytes/cycle)[73] per SM partition[74] 128 tbd 256

Minimum cycles for warp-wide matrix calculation 16 tbd

[75] 2048
Minimum Matrix Shape for full throughput (Bytes)

Technical specification

Technical Compute capability (version)

specifications 1.0 1.1 1.2 1.3 2.x 3.0 3.2 3.5 3.7 5.0 5.2 5.3 6.0 6.1 6.2 7.0 7.2 7.5
Maximum
number of
resident grids
per device
(concurrent
1 16 4 32 16 128 32 16 128 16
kernel
execution, can
be lower for
specific
devices)
Maximum
dimensionality
2 3
of grid of
thread blocks
Maximum x-
dimension of a
grid of thread
65535 231 − 1
blocks
Maximum y-,
or z-dimension
65535
of a grid of
thread blocks
Maximum
dimensionality 3
of thread block
Maximum x- or
y-dimension of 512 1024
a block
Maximum z-
dimension of a 64
block
Maximum
number of
512 1024
threads per
block
Warp size 32
Maximum
number of
resident blocks 8 16 32 16
per
multiprocessor
Maximum
number of
resident warps 24 32 48 64 32
per
multiprocessor
Maximum
number of
resident 768 1024 1536 2048 1024
threads per
multiprocessor
Number of 32-
bit regular 128
8K 16 K 32 K 64 K 64 K
registers per K
multiprocessor
Number of 32- 2 K[80
bit uniform [81]
No
registers per
multiprocessor
Maximum
number of 32-
64 32
bit registers 8K 16 K 32 K 64 K 32 K 64 K 32 K
K K
per thread
block
Maximum 124 63 255
number of 32-
bit regular
registers per
thread
Maximum
number of 32- 63[80]
bit uniform No [82]
registers per
warp
Amount of
shared 80 /
memory per 96 /
16 / 0 / 8 / 16 /
multiprocessor 112
48 KiB 16 / 32 / 48 32 / 64 /
(out of overall 16 KiB KiB 64 KiB 96 KiB 64 KiB 96 KiB 64 KiB 32 / 64 KiB (o
(of 64 KiB (of 64 KiB) 96 KiB (of
shared (of
KiB) 128 KiB)
memory + L1 128
cache, where KiB)
applicable)
Maximum
amount of
96 48
shared 16 KiB 48 KiB 64 KiB
KiB KiB
memory per
thread block
Number of
shared 16 32
memory banks
Amount of
local memory 16 KiB 512 KiB
per thread
Constant
memory size
accessible by
CUDA C/C++
(1 bank, PTX 64 KiB
can access 11
banks, SASS
can access 18
banks)
Cache working
set per
multiprocessor 8 KiB 4 KiB
for constant
memory
Cache working
set per 24 KiB
16 KiB per 32 –
multiprocessor
TPC
per 12 KiB 12 – 48 KiB[83] 24 KiB 48 KiB 32 KiB[84] 24 KiB 48 KiB 24 KiB
128 KiB
32 – 64
for texture TPC
memory
Maximum
width for 1D
texture
reference 8192 65536
bound to a
CUDA
array
Maximum
width for 1D
texture
reference 227 228 227 228 227
bound to linear
memory
Maximum
width and
number of
layers for a 1D 8192 × 512 16384 × 2048
layered
texture
reference
Maximum
width and
height for 2D
texture
65536 × 32768 65536 × 65535
reference
bound
to a CUDA
array
Maximum
width and
height for 2D
texture
65000 x 65000 65536 x 65536
reference
bound
to a linear
memory
Maximum — 16384 x 16384
width and
height for 2D
texture
reference
bound
to a CUDA
array
supporting
texture gather
Maximum
width, height,
and number of
8192 × 8192 × 512 16384 × 16384 × 2048 3
layers for a 2D
layered texture
reference
Maximum
width, height
and depth for
a 3D texture
reference 20483 40963
bound to linear
memory or a
CUDA array
Maximum
width (and
height) for a
— 16384
cubemap
texture
reference
Maximum
width (and
height) and
number of
— 16384 × 2046
layers
for a cubemap
layered texture
reference
Maximum
number of
textures that
128 256
can be bound
to a
kernel
Maximum Not
width for a 1D supported
surface
65536 16384
reference
bound to a
CUDA array
Maximum
width and
number of
layers for a 1D 65536 × 2048 16384 × 2048
layered
surface
reference
Maximum
width and
height for a 2D
surface 65536 × 32768 16384 × 65536
reference
bound to a
CUDA array
Maximum
width, height,
and number of
layers for a 2D 65536 × 32768 × 2048 16384 × 16384 × 2048 3
layered
surface
reference
Maximum
width, height,
and depth for
a 3D surface 65536 × 32768 × 2048 4096 × 4096 × 4096 16
reference
bound to a
CUDA array
Maximum
width (and
height) for a
cubemap
32768 16384
surface
reference
bound to a
CUDA array
Maximum
width and
number of
layers for a
32768 × 2046 16384 × 2046
cubemap
layered
surface
reference
Maximum 8 16
number of
 surfaces that
can be bound
to a
kernel
Maximum
number of
2 million 512 million
instructions
per kernel
Maximum
number of
Thread Blocks
per Thread No
Block
Cluster[85]

Technical 1.0 1.1 1.2 1.3 2.x 3.0 3.2 3.5 3.7 5.0 5.2 5.3 6.0 6.1 6.2 7.0 7.2 7.5
specifications Compute capability (version)

[86]
[87]

Multiprocessor architecture

Architecture Compute capability (version

specifications 1.0 1.1 1.2 1.3 2.0 2.1 3.0 3.2 3.5 3.7 5.0 5.2 5.3 6.0
Number of
ALU lanes for
INT32
arithmetic
operations
Number of
ALU lanes for
any INT32 or
FP32
8 32 48 192[88] 128
arithmetic
operation 128 64
Number of
ALU lanes for
FP32
arithmetic
operations
Number of
ALU lanes for
FP16x2 No
arithmetic
operations
Number of
ALU lanes for 16 by 4 by 8/
FP64 No 1 8 64 4[95] 32
arithmetic FP32[92] FP32[93] 64[94]
operations
4 8 8 per 2
Number of
per per SM / 3 8 per 3
Load/Store 16 32 16
2 2 SM
Units
SM SM SM[94]

Number of
special
function units
for single-
precision 2[96] 4 8 32 16
floating-point
transcendental
functions
Number of 4 8 8 per 2
texture per per 8 per 3
mapping units 2 2
/
SM
4 4 / 8[94] 16 8 16 8
(TMU) SM SM 3SM[94]

Number of
ALU lanes for
uniform INT32 No
arithmetic
operations

Number of
No
tensor cores

Number of
raytracing No
cores

Number of SM
Partitions =
Processing 1 4 2
Blocks[99]
 Number of
warp
1 2 4
schedulers per
SM partition
Max number of
new
instructions
issued each 2[101] 1 2[102] 2
cycle by a
single
scheduler[100]
Size of unified
memory for 64 KiB SM + 96 KiB SM + 64 KiB SM + 64 KiB SM +
16 128
data cache 16 KiB[103] 64 KiB 24 KiB L1 24 KiB L1 24 KiB L1 24 KiB L1
KiB[103] KiB
and shared (separate)[104] (separate)[104] (separate)[104] (separate)[104]
memory
Size of L3
instruction 32
cache per KiB[106]
GPU
Size of L2 use L
instruction
cache per
8 KiB
Texture
Processor
Cluster (TPC)
Size of L1.5
instruction 32
cache per KiB
32 KiB 48 KiB[84] 128 KiB
SM[107] 4 KiB
Size of L1
instruction 8 KiB 8K
cache per SM
Size of L0
instruction
only 1 partition per SM No
cache per SM
partition

Instruction 64 bits instructions + 64

32 bits instructions and 64 bits instructions[111] bits control logic every 64 bits instructions + 64 bits control logic every 3
Width[107] 7 instructions
Memory Bus
Width per
64 ((G)DDR) 32 ((G)DDR) 512 (HBM)
Memory
Partition in bits
L2 Cache per 32
Memory 16 KiB[112] 128 KiB 256 KiB 1 MiB 512 KiB 128 KiB 512 KiB
Partition KiB[112]

Number of
Render Output
Units (ROP)
per memory 4 8 4 8 16 8 12
partition (or
per GPC in
later models)

Architecture 1.0 1.1 1.2 1.3 2.0 2.1 3.0 3.2 3.5 3.7 5.0 5.2 5.3 6.0
specifications Compute capability (version

[115]

For more information read the Nvidia CUDA programming guide.[116]

Current and future usages of CUDA architecture

Accelerated rendering of 3D graphics
Accelerated interconversion of video file formats
Accelerated encryption, decryption and compression
Bioinformatics, e.g. NGS DNA sequencing BarraCUDA[117]
Distributed calculations, such as predicting the native conformation of proteins
Medical analysis simulations, for example virtual reality based on CT and MRI scan images
Physical simulations,[118] in particular in fluid dynamics
Neural network training in machine learning problems
Large Language Model inference
Face recognition
Volunteer computing projects, such as SETI@home and other projects using BOINC software
Molecular dynamics
Mining cryptocurrencies
 Structure from motion (SfM) software

Comparison with competitors

CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.

Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.

Intel OneAPI
oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures.[119] The oneAPI libraries must
implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement
their own versions of oneAPI libraries.[120][121]

Originally made by Intel, other hardware adopters include Fujitsu and Huawei.

Unified Acceleration Foundation (UXL)

Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new
open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs).
The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and
VMware.[122]

AMD ROCm
ROCm[123] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).

See also
SYCL – an open standard from Khronos Group for programming a variety of platforms, including GPUs, with single-source modern C++,
similar to higher-level CUDA Runtime API (single-source)
BrookGPU – the Stanford University graphics group's compiler
Array programming
Parallel computing
Stream processing
rCUDA – an API for computing on remote computers
Molecular modeling on GPUs
Vulkan – low-level, high-performance 3D graphics and computing API
OptiX – ray tracing API by NVIDIA
CUDA binary (cubin) – a type of fat binary
Numerical Library Collection – by NEC for their vector processor

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Further reading
Buck, Ian; Foley, Tim; Horn, Daniel; Sugerman, Jeremy; Fatahalian, Kayvon; Houston, Mike; Hanrahan, Pat (2004-08-01). "Brook for GPUs:
stream computing on graphics hardware" (https://dl.acm.org/doi/10.1145/1015706.1015800). ACM Transactions on Graphics. 23 (3): 777–
786. doi:10.1145/1015706.1015800 (https://doi.org/10.1145%2F1015706.1015800). ISSN 0730-0301 (https://search.worldcat.org/issn/0730-0
301).
Nickolls, John; Buck, Ian; Garland, Michael; Skadron, Kevin (2008-03-01). "Scalable Parallel Programming with CUDA: Is CUDA the parallel
programming model that application developers have been waiting for?" (https://dl.acm.org/doi/10.1145/1365490.1365500). Queue. 6 (2): 40–
53. doi:10.1145/1365490.1365500 (https://doi.org/10.1145%2F1365490.1365500). ISSN 1542-7730 (https://search.worldcat.org/issn/1542-77
30).

External links
Official website (https://developer.nvidia.com/cuda-zone)

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