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Standard Cell Library Validation Methodology

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 Standard Cell Library Validation Methodology
M. de Carvalho, C. Nunes, B. Canal1, L. Puricelli, L. Reinicke, G. Webber,
A. Neutzling2, M. Altieri, E. Conto, T. Nagel, 3P. Butzen, 1,2R. P. Ribas, 1E. Fabris
Institute of Informatics / 1PGMicro / 2PPGC, UFRGS, Av. Bento Gonçalves, 9500, Porto Alegre – Brazil.
3
Federal University of Rio Grande (FURG), Av. Itália, Km 8, Rio Grande – Brazil.
.
Abstract— In digital IC design, the standard cell-based design is the c) Benchmarks for silicon sign-off
most used in the industry. It accounts on a mature validated cell library d) Silicon validation
to quickly design a reliable commercial IC. However, cell libraries are At the cell design step, once the electrical characteristics have
constantly modified and a series of validation tasks are employed to
been established through the transistors sizing, the two validation
guarantee correct IC design and fabrication. This work presents a
methodology for validating a standard cell library at different levels,
tasks are performed: design rule check (DRC) and the layout vs
from cell design verification to silicon validation. We use the schematic (LVS). The DRC process identifies whether the silicon
methodology to validate from scratch two 0.6µm CMOS cell libraries and metal layers respect the limits of dimensions and distances
designed for the Brazilian industry. according to the manufacturing process restrictions, whereas the
LVS task verifies whether the circuit functionality extracted from
Keywords— Validation methodology, tests, measurements.
the physical layout corresponds to the desired schematic circuit
I. INTRODUCTION behavior, as well as verifying corresponding gate, ports and net
In the context of the recent investment in Brazilian names. Lastly, the cells are electrically stimulated to determine if
semiconductor industry, an agreement between CEITEC S.A and output delays and voltages match according to specifications.
the Federal University of Rio Grande do Sul (UFRGS) was signed At the design flow phase, designers usually chose several
with the goal of developing a standard cell library in the X-Fab commonly used benchmarks to validate the library in the flow and
0.6µm technology. The project is financed by government agencies check whether they can be correctly synthesized into their
and also involves NSCAD Microeletrônica and the federal IC- respective physical layouts. These benchmarks can be
Brazil professional training program [1]. The project started in microprocessor cores (μP), encryption cores, communication
December 2013 and is scheduled to end in June 2016. cores, and etc. Although DRC and LVS tasks are executed during
Digital ICs are easily developed by using Electronic Design the cell design, it is necessary to run them again on the target
Automation (EDA) tools that exploits a trusted standard cell library design, because the ensemble of cells assembled on the same
to synthesize a high-level hardware description into silicon layout layout may produce wrong connections, shape sizes and distances.
Also, it is important to highlight that the physical layouts
for IC manufacturing. Standard cell libraries contain an ensemble
of logic functions and their corresponding layout scheme for produced in this phase are not sent for manufacturing, they must
silicon implementation. The cell library can be acquired by specific undergo the sign-off check phase.
vendors but is commonly provided by the foundry in a Process In order to be able to validate the library in silicon, specific
benchmarks must be selected [2]-[6]. They should be capable of
Design Kit (PDK) to ensure the correct IC design and manufacture.
Moreover, cell libraries may be frequently redesigned targeting maximizing distinct cell instantiation and configuring several test
particular requirements on timing, power consumption, supply modes. They should have auto-validation function and easy access
voltage, or other. Thus, once a new cell library version is available, to inner logic for detecting badly designed cells. Finally, they
a validation process is necessary in order to guarantee correct must allow the observation of the library maximum frequencies
commercial design manufacturing. and voltages, usually limited by the technology and
Usually, a standard cell library is validated at different design manufacturing process. Clearly, these specific benchmark differs
levels: from cell design to silicon. The last level accounts on from the ones used in the design flow validation level. On the
manufactured a IC containing effective benchmarks for evaluating other hand, not having an actual real case design makes the cell
the cells functions and electrical characteristics. If this test IC library validation task incomplete. Therefore we have also devised
includes configurable operating modes, it could also bring up a real case 16-bit CPU used for didactic activities based on the
reasonable test information to validate functionally and architecture presented in [7]. In addition, we developed it by using
electrically the library. an industry-like digital ASIC flow accounting on the newly
In this paper, we describe the main efforts and procedures designed cell library under evaluation.
needed to validate a standard cell library. In Section II, we define As soon as the chips containing the benchmarks are
the validation levels at different design phases and, from Section manufactured and packaged, a silicon validation task is
III to Section VI, we detail the techniques adopted at each level. performed, encompassing manufacturing and characterization
Then, in Section VII, we show the results of the proposed tests [8][9]. The former identifies possible manufacturing errors
validation methodology. Finally, in the last section, we draw some while the latter is capable of determining electrical and timing
conclusions and future works. information of a device under test (DUT), determining whether
the designs meet functional correctness according to
II. CELL LIBRARY VALIDATION LEVELS specifications.
The digital IC design exploiting the standard cell-based III. GATE DESIGN VALIDATION
method accounts on a mature validated cell library usually Each cell in the library is carefully drawn by a group of layout
developed in a full custom manner by designers. The validation engineers that take into consideration the technology constraints.
process comprises of a series of validation tasks occurring at Figure 1(a) shows a typical NAND gate layout with double-
different levels, as follows: headed arrows delimiting dimensions that need to be compliant
a) Gate (cell) design with design rules that are determined by the manufacturing
b) Standard cell design flow process limitations. Figure 1(b) shows a 3x3 array of NAND gates
and is commonly set up (as a possible design scenario) by include typical circuits of different applications to stress the
designers to check DRC between different cells. The basic idea synthesis and mapping flow steps. At physical implementation
behind this cell validation technique is to tightly place adjacent to phase, DRC and LVS are applied to each layout looking for any
the target cell (C) the same cell design in several different layout violation. If a failure is detected in any part of the design
reflected configurations: normal, upside down, and left-side right. flow, the library under evaluation is not ready for silicon
The target cell is placed in the center of the middle row (M). Also, validation and must undergo cell design refinement. Note that in
the top (T) and bottom (B) cells are reflected with respect to M this phase, the physical layouts are not sent for manufacturing,
such that the T and B cells can share, respectively, the same VDD they are only test cases to validate the cell library under the design
and GND as the M cells. flow usage.
V. BENCHMARKS FOR SILICON VALIDATION
In order to make the cell library validation task easier, we have
selected three special benchmarks. Two of them includes auto-
validation functions for stimulating distinct cells. One is effective
for evaluating the combinational cells and the other for the
sequential cells [6][10]. Then, a third benchmark embedding a real
case circuit was selected to perform a more realistic evaluation. It
embeds both combinational and sequential logic in a typical
Figure 1. DRC in the cell (a) and between cells (b) industry-like design using the typical ASIC flow. All benchmarks
Another typical cell validation task is the LVS. Figure 2 are described in the following subsections.
shows a possible situation where DRC passes but LVS fails. From A) COMBINATIONAL CELLS
the designed cell (Fig. 2a), LVS extracts the electrical schematic The most direct way of creating a chip specifically for cell
(Fig. 2b) and compares it with the desired schematic (Fig. 2c). In library validation is by placing distinct cells parallel to each other
the example shown in the figure, a connection (pointed out by the sharing the same inputs and multiplexing their outputs [5]. This
dark double-headed arrow) between b and out was mistakenly method can obviously validate each cells function, but electrical
inserted in the polysilicon routing, so differing from the desired and timing information may be quite difficult to obtain through a
schematic. LVS also compares all gates, ports and net names circuit with only one logic depth, especially when attached to high
between electrical and schematic levels, as highlighted in the capacitive input and output pins. Ideally, the cells should be
picture by the light red double-headed arrow. placed in a circuit where they drive other cells. In [6], the authors
proposed a methodology capable of automatically generating a
combinational cell library benchmark for overcoming the above-
mentioned issue, by placing all distinct cells in a circuit with
several logic fan-outs and depths.

Figure 2. LVS procedure: (a) cell layout, (b) extracted schematic, and
(c) targeted schematic
Finally, once DRC and LVS pass, the cell is thoroughly
characterized, i.e., it is stimulated in a simulation environment to
obtain electrical and timing information (e.g. rising and falling
transition times, output voltages, output currents and noise
margins). This information has to comply with the desired Fig 4. Benchmark for on silicon validation of combinational cells [6].
specifications, otherwise the cell must be redesigned.
Figure 4 depicts the benchmark architecture which is composed of
IV. STANDARD CELL DESIGN FLOW VALIDATION two main parts:
1) Combinational Blocks (CBs) (in blue) have two stages:
a. First Stage (FS): Distinct cells are arranged parallel to each
other implementing a function denoted as: f (In).
b. Second Stage (SS): Composed of a group of cells inverting the
FS logic function, represented as: f −1(f (In)).
2) Operation mode Blocks (in white): The combined function of
these modules allows selecting three test modes:
a. Synchronous: Tests the selected CB by analyzing the DFF
register contents which are incremented at every clock cycle
controlled by an external source
Figure 3. Cell library validation at IC design flow phase. b. Asynchronous: Automatically tests the selected CBs
Once the cell library design has been completed and fully performance by analyzing the DFF register contents, which is
characterized, the IC design flow is explored to check that any clocked when In and Out values are the same
sample benchmark can be sinthesized into a manufacturable c. Closed-loop oscillation Built-In Self-Test (OBIST): Helps
silicon layout. The cell library validation at the IC design flow determining timing information of specific cells by oscillating
phase is shown in Figure 3. Several different real benchmarks (1 a chosen path that propagates through the CBs.
to N) are carefully selected as test cases in the flow. They must
B) SEQUENTIAL CELLS VI. SILICON IC VALIDATION
An effective benchmark to validate sequential cells (FFs and Silicon validation tasks, usually called as bring-up, are the last
Latches) must include testing all possible inputs by stimulating step in the development of an IC. In contrast to pre-silicon
one at a time. One possible solution to achieve this goal is setting verification that tests the IC model in a virtual environment, post-
these cells in a ring oscillator configuration [8]. Figure 5 shows silicon validation occurs on the actual tangible IC prototype
the proposed benchmark (3 inverting FFs and 1 buffer) which is running slow and at-speed tests [8][9].
capable of stopping ring oscillation whenever a cell is faulty, or Silicon validation tasks basically falls into two categories:
not compliant with functional specifications. Also, it is effective manufacturing and characterization tests. The first allows
on determining maximum oscillation frequency for a specific determining if the tested sample was correctly built by controlling
sequential cell library. and observing gate-by-gate net-by-net using structural test
patterns. Once one good sample is found, characterization tests
must be applied to this sample in order to gather important timing
information about the manufactured device. In the latter test, test
patterns are manually defined according to synthesis results and
specifications. For both test types we employed a typical
validation setup shown in Figure 8.
Figure 5. Benchmark for sequential cells.
C) REAL CASE BENCHMARK
The third benchmark comprises of both combinational and
sequential cells in a real case study such that we can evaluate
whether the ASIC design flow embedding the target cell library
actually works. We have selected a 16-bit CPU core based on [7]
which has also been used to validated the ASIC flow in Section
IV. In the past years, this 16-bit CPU named Charrua has been Figure 8. Proposed post-silicon validation setup.
used for IC design training within the IC-Brazil professional
training program [1] and was initially created for teaching First, we separately analyze the design model and physical
Computer Architecture and programming at the University of Vale chip perspectives. From the design perspective, we use the sign-
do Itajaí [7]. The Charrua core described in [7], is placed in the off netlist of our benchmarks to generate test patterns. This task
top-level design together with two IP RAMs and an SPI bootloder may or may not account on an Automatic Test Pattern Generator
using the APB protocol bus, as shown in Figure 6. Moreover, it (ATPG). From the physical chip perspective, the chips will be
has 6 test pins, 5 operational pins, 4 bootloader pins and 16 I/O stimulated by the tester according to the test stimuli previously
pins for external communication and test purposes. generated and produce results that are collected by the tester. The
measured results are then compared to expected golden results.
For manufacturing tests, the expected results are computed during
pre-silicon verification by using simulation tools. Whereas for
characterization tests, the results are determined from the
specifications and synthesis reports. Also, a diagnosis task allows
analyzing faulty results and detect manufacturing errors or, for the
purpose of our work; to determine cell and routing layout bugs,
thus allowing cell library layout refinement.
Finally, we highlight that our benchmarks have internal pattern
generators, self-test mechanisms and easy access to test ports to
help us accurately evaluate the cell library without having to use
probe stations or expensive automatic test equipments.
VII. CASE STUDY AND RESULTS
Figure 6. Proposed Charrua benchmark top-level view. We designed two cell libraries versions in 0.6μm technology:
one standard (CTC06ST) and one small area version (CTC06LA).
In addition, we have implemented a shadow scan-chain to
Both libraries have 403 combinational cells and 26 sequential
evaluate and validate the benchmark. This means that, for each
ones. We have started the validation flow herein described but
FF, we added in parallel a scan FF (SFF) such that their outputs
there are still a long path to finish testing all samples in order to
are multiplexed. This strategy allows evaluating not only the
validate both cell libraries. In addition, our efforts account on a
combinational logic but also normal FFs, since Design-for-Test
group of 16 people executing design and validation tasks using
(DfT) synthesis usually replaces all normal FFs with SFF. This
Cadence tools. Results of each validation step are described in the
DfT strategy is depicted in Figure 7. If normal or scan FFs (but
following subsections.
not both) have layout bugs, then the design can still be evaluated.
A) GATE DESIGN VALIDATION RESULTS
We had difficulties in this initial stage as re-design was often
needed to meet DRC and LVS validation rules as well as sizing
constraints. Common mistakes stemmed from simple last-minute
modifications, which caused severe errors that were hard to detect.
After iterating through cell design refinment and characterizing it
each time, we were able to complete design and validation tasks
for each cell. This initial phase required approximately 2000 hs on
Figure 7. Design-for-test strategy. designing and 1000 hs on validation for both library versions.
B) STANDARD CELL DESIGN FLOW VALIDATION benchmarks using this library worked correctly, providing 7.5 to
12.5 MHz frequencies with a jitter that could not be correctly
We stressed the cell design flow by using different benchmarks:
measured. Recently, we have adjusted the LibTestLA and finished
128-bit AES encryption core, 128-bit AES fixed secret, different
the 16-bit CPU using the CTC06ST cell library version. Both
versions of a CPU core, the benchmarks in Section V, and several
sign-offs have been sent for manufacturing thanks to the Brazilian
small peripherals, like SPI modules. Initially, summing all errors multi-user project offered by CEITEC. Figure 10 shows their
of all benchmarks, we obtained more than 20,000 errors. These
corresponding 3x3 mm2 sign-off layouts.
problems were mainly notch errors that arouse from exporting a
.DEF file from Encounter to Virtuoso.
IP IP
RAM RAM

IP IP
(a) (b) RAM RAM
Figure 9. (a) Virtuoso and (b) Encounter .
(a) (b)
Figure 9 shows an example of notch error in Virtuoso (Fig. 9a)
Figure 10. (a) Charrua CPU (b) LibTestLA.
occurring at this validation stage. As it can be seen, double vias
had different definitions in the foundry technology .LEF file in
both tools. In Virtuoso they were slightly dislocated to the left VIII. CONCLUSIONS
(50nm) as well as the connection (0.5μm to the right). Note that We have presented a standard cell library validation approach
some layers cannot be seen by Encounter (Fig. 9b), so it does not which tackles validation at several different stages. The proposed
report these DRC errors, whereas in Virtuoso, many of errors like approach has the goal of delivering a trusted cell library to a
in the picture were spotted. The reported DRC errors were customer which will take for granted that using it he will be able
eliminated at the instant the library .LEF file used by Encounter to manufacture any design for the target foundry (as long a certain
was modified to match Virtuoso technology file. number of rules are respected). We explained these validation
steps starting from bottom-up, that is beginning from basic
C) BENCHMARK VALIDATION standard cell design to a real manufactured digital ASIC prototype
The combinational benchmark explained in Section V(A) was that accounts on the provided cell library. Also, the proposed
verified in logic and electrical simulations and validated on silicon benchmarks have shown to be very effective on detecting layout
using a mature 0.6μm technology provided by XFAB[11]. bugs that helped quickly correcting mistakes and arranging
Simulation results and real measurements have shown to be very another tapeout. Results have demonstrated that the proposed cell
similar, especially the maximum frequency (~7MHz) when all library validation approach is on the right track.
combinational blocks were stimulated together. The sequential
benchmark was also verified using logic and electrical simulations ACKNOWLEDGEMENTS
by combining several different FF ring oscillator configurations. Project partially founded by CNPQ (grant 305113/2014-3) in
Although results have not yet been published, they have shown to partnership with CEITEC S.A.
oscillate at 12MHz to 50MHz frequencies. Finally, the 16-bit
CPU core was throughly verified and stimulated, achieving a REFERENCES
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