MALLA REDDY ENGINEERING COLLEGE (AUTONOMOUS)

II B.Tech I Semester(MR 22) I Mid Question Bank 2024-25 (Subjective)

Subject: Computer Organization and Architecture (C0509) Branch: CSE-AIML
Name of the Faculty: T. KISHORE, CH.V.S SURYANARAYAN

S BT
Questions Marks
Level
CO
NO.

Module-1
1 Sketch a neat diagram and explain in detail the functional units of a computer. 5 2 1

2 Describe Bus and Memory Transfers 5 2 1

3 Explain the one stage of arithmetic logic shift unit with a neat sketch. 5 3 1

4 Classify different logic micro operations with the functional table. 5 2 1

5 Demonstrate different shift micro operations in detail. 5 2 1

6 Write about Computer Design and Computer Architecture 5 3 1

7 Explain the different memory reference instructions 5 2 1

8 Explain Input – Output and Interrupt 5 2 1

S BT
Questions Marks
Level
CO
NO.
Module-2
1 Explain briefly about control memory 5 3 2

2 Describe Micro Program with an example 5 2 2

3 Explain about address sequencing capabilities in control memory. 5 2 2
4 Distinguish between data transfer and data manipulation instructions. 5 2 2
5 Use different instruction format and evaluate the expression Y=(A-B)/(C+D*E) 5 2 2
Explain about Addressing Modes with an Numerical Example? 2
6 5 2

7 Illustrate about General Register Organization 5 2 2

8 Define an instruction? Explain the instruction cycle. 5 2 2

 S BT
Questions Marks
Level
CO
NO.
Module-3
Explain the fixed point representation and floating point representation? 5 2 3
1
Design the flow chart for Booths Multiplication algorithm with an example? 5 2 3
2

3 Write about Computer Arithmetic Addition with neat flow chart. 5 2 3

4 Illustrate Decimal Arithmetic Unit and Operations 5 2 3

Prepared By Name: Dr J Anitha & Mr D Syam Kumar

Signature: HOD Signature
 MALLA REDDY ENGINEERING COLLEGE (AUTONOMOUS)
II B.Tech I Semester(MR 22) I Mid Question Bank 2024-25 (Subjective)
Subject: Computer Organization and Architecture (C0509) Branch: CSE-AIML
Name of the Faculty: T. KISHORE, CH.V.S SURYANARAYAN

S.
Questions Ans
NO.
Model-1
Which sequential circuits generate the feedback path due to the cross-coupled connection from
1 output of one gate to the input of another gate? B
a)Synchronous b) Asynchronous c) Both d) None of the above
What is/are the crucial function/s of memory elements used in the sequential circuits?
2 a) Storage of binary information b)Specify the state of sequential C
c) Both a & b d) None of the above
How are the sequential circuits specified in terms of time sequence?
3 D
a) By Inputs b) By Outputs c) By Internal states d)All of the above
The behavior of synchronous sequential circuit can be predicted by defining the signals at
4 a) discrete instants of time b) continuous instants of time A
c) sampling instants of time d) at any instant of time
Which memory elements are utilized in an asynchronous & clocked sequential circuits
respectively?
5 B
a) Time- delay devices & registers b) Time- delay devices & flip-flops
c) Time- delay devices & counters d) Time-delay devices & latches
Why do the D-flip-flops receives its designation or nomenclature as 'Data Flipflops' ?
a) Due to its capability to receive data from flip-flop
6 C
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop d) None of this
The characteristic equation of D-flip-flop implies that
a) the next state is dependent on previous state
7 b) the next state is dependent on present state D
c) the next state is independent of previous state
d) the next state is independent of present stated
Which circuit is generated from D-flip-flop due to addition of an inverter by causing reduction
8 in the number of inputs? D
a) Gated JK- latch b) Gated SR- latch c) Gated T- latch d) Gated D- latch
What is the bit storage binary information capacity of any flip-flop?
9 a) 1 bit b) 2 bits c) 16 bits d) infinite bits A
What is/are the directional mode/s of shifting the binary information in a shift register?
10 B
a) Up-Down b) Left – Right c) Front – Back d) All of the above
Which time interval specify the shifting of overall contents of the shift registers?
11 a) Bit time b) Shift time c) Word time d) Code time C
A counter is fundamentally a sequential circuit that proceeds through the
12 predetermined sequence of states only when input pulses are applied to it. C
a) Register b) memory unit c) Flip-flop d) arithmetic logic unit
What is the maximum possible range of bit-count specifically in n-bit binary counter consisting
13 of 'n' number of flip-flops? B
a) 0 to 2n b) 0 to 2n-1 c) 0 to 2n+1 d) 0 to 2n+1 / 2
 Which property of unit distance counters has the potential to overcome the consequences of
multi-bit change flashing that arises in almost all conventional binary and decimal counters?
14 A
a) one bit change per unit change b) two bits change per unit change
c) three bits change per unit change d) four bits change per unit change
What contributes to the triggering of clock pulse inputs for all the flip-flops excluding the first
15 flip-flop in a ripple counter? B
a) Incoming Pulses b) Output Transition c) Double Clock Pulses d) All of the above
What is the required relationship between number of flip-flops and the timing signals in Johnson
Counter?
a) No. of flip-flops = 1/2 x No. of timing signals
16 A
b) No. of flip-flops = 2/3 x No. of timings signals
c) No. of flip-flops = 3/4 x No. of timing signals
d) No. of flip-flops = 4 x No. of timing signals
Which clock pulses are generated by the microprocessor so as to handle the timing and control
operations related to internal functioning level?
B
17 a) single phase clock pulses b) multi-phase clock pulses
c) anti-phase clock pulses d) none of the above
The bus-request control input of micro-processor indicates the temporary suspension of current
18 operation by driving all buses into . A
a) high impedance state b) low impedance state c) both a & b d) none of the above
Which feature conducts the memory transfer by controlling the address and data buses on the
basis of request originated by the device when buses get disabled by the microprocessor?
19 B
a) Indirect Memory Access b) Direct Memory Access
c) Read Memory Access d) Write Memory Access
By default counters are incremented by
20 A
a) 1 b) 2 c) 3 d) 4
Simplest registers only consists of
21 D
a) Counter b) EPROM c) Latch d) flip-flop
Three decade counter would have
22 B
a) 2 BCD counters b) 3 BCD counters c) 4 BCD counters d) 5 BCD counters
A decimal counter has
23 a) 5 states b) 10 states c) 15 states d) 20 states B
Memory that is called a read write memory is
24 C
a) ROM b) EPROM c) RAM d) Registers
2 left shifts are referred to as multiplication with
25 B
a) 2 b) 4 c) 8 d) 16
Ripple counters are also called
26 a) SSI counters b) asynchronous counters c) synchronous counters d) VLSI counters B
Transformation to information into registers is called
27 A
a) Loading b) gated latch c) Latch d) Storing
Binary counter that count incrementally and decrementally is called
28 a) up-down counter b) LSI counters c) down counter d) up counter A
Shift registers having four bits will enable shift control signal for
29 a) 2 clock pulses b) 3 clock pulses c) 4 clock pulses d) 5 clock pulses C
A group of binary cells is called
30 B
a) Counter b) Register c) Latch d) Flip-flop
 Synchronous counter is a type of
31 a) SSI counters b) LSI counters c) MSI counters d) VLSI counters C
BCD counter is also known as
32 B
a) parallel counter b) decade counter c) synchronous counter d) VLSI counter
A 8-bit flip-flop will have
33 a) 2binary cells b) 4binary cells c) 6binary cells d) 8binary cells D
Parallel load transfer is done in
34 a) 1 cycle b) 2 cycle c) 3 cycle d) 4 cycle A
To start counting enable input should be
35 B
a) 0 b) 1 c) Reset d) Clear
Ripple counter cannot be described by
36 A
a) Boolean equation b) clock duration c) Graph d) flow chart
Time between clock pulses are called
37 D
a) bit duration b) clock duration c) Duration d) bit time
Parallel loading is done in
38 a) 1 cycle b) 2 cycle c) 3 cycle d) 4 cycle A
Control unit in serial computer generates a( B)
39 B
a) reset signal b) word-time signal c) word signal d) clear signal
BCD counter counts from
40 C
a) 0 to 5 b) 1 to 5 c) 0 to 9 d) 1 to 9
J=K=0 will make flip-flops
41 a) Changed b) Reversed c) Unchanged d) Stopped C
Special type of registers are
42 a) Latch b) Flip-flop c) Counters d) Memory C
Flip-flops in registers are
43 C
a) Present b) level triggered c) edge triggered d) not present
Down counter decrement value by
44 A
a) 1 b) 2 c) 3 d) 4
Ripple counter is a type of
45 C
a) SSI counters b) LSI counters c) MSI counters d) VLSI counters
Propagation of signal through counters is in
46 a) ripple fashion b) serial fashion c) parallel fashion d) both a and b A
Register shifting left and right both is called
47 a) unidirectional shift register b) bidirectional shift register B
c) left shift register d) right shift register
A decimal counter has
48 a) 2 flip-flops b) 3 flip-flops c) 4 flip-flops d) 5 flip-flops C
Control variable of registers is also called
49 B
a) store control input b) load control input c) store control output d) load control output
Time to transfer content of shift register is called
50 a) word duration b) clock duration c) Duration d) bit time A

Model-2
Fast electronic machine accepts digital input information process and produce resulting output is
51 a) Analog Computer b) Digital Computer c) Workstation d) Super Computer B
 List of Instructions is
52 a) Computer Program b) Function c) Procedure d) Sub Routine A
Internal Storage is called
53 A
a) Computer Memory b) Stack c) Queue d) Data structure
Computer used in home, office and schools is
54 a) Super Computer b) Mainframe Computer c) Personal Computer d) Client machine C
Computer having High resolution graphics I/O capability
55 a) Desktop Computer b) Digital Computer c) Network Computer d) Workstation D
Systems used for business data processing
56 C
a) Super computers b) Servers c) Mainframe d) Network PC
Computers used for large scale numerical calculations is
57 A
a) Super computers b) Servers c) Mainframe d) Network PC
Systems handling large volumes of requests to access data is
58 B
a) Super computers b) Servers c) Mainframe d) Network PC
Computer consists of functional independent main parts
59 a) 1 b) 3 c) 5 d) 7 C
unit accepts information from human operators
60 B
a) Output b) Input c) ALU d) Control Unit
A computer language that is written in binary codes only is
61 A
a) Machine language b) C c) C# d) Pascal
Expand ASCII
a) American Standard Code for Information Interchange
62 A
b) American Social code for Instruction Interchange
c) Asian standard for Interrupt Interchange d) Asian Stack for Invoice Interchange
Two classes of storage
63 B
a) Serial, parallel b) Primary, secondary c) Input, output d) ION,IOF
ASCII is a bit code
64 a) 1 b) 3 c) 5 d) 7 D
Convert the binary equivalent 10101 to its decimal equivalent.
65 A
a) 21 b) 12 c) 22 d) 31
Number of bits in each word is referred to as
66 a) Bytelength b) Bitlength c) Wordlength d) Nibblelength C
The time required to access one word is called the
67 a) Memory Read Time b) Memory WriteTime D
c) Memory Buffer Time d) Memory Access Time
Basic arithmetic operations are performed in
68 a) CU b) ALU c) Memory d) Input B
sends the processor results to outside world
69 A
a) Output Unit b) Input Unit c) Memory Unit d) Control Unit
determines when a given action has to take place
70 a) Clock b) Interval c) Timing Signal d) Pulse C
A group of lines that serve as connecting path for several devices is
71 a) Cable b) Bus c) Wire d) Line B
All activities inside the machine are directed by
72 D
a) Output Unit b) Input Unit c) Memory Unit d) Control Unit
 is a collection of programs
73 a) Hardware b) System Software c) Circuitry d) Directory B
Expand SCSI
74 a) Small Computer System Interface b) Semi Classic Software Interface A
c) Semi Circuitry System Interface d) System Computer System Interface
Important measure of computer is
75 a) System Software b) System Hardware c) Performance d) Bus C
Processor Circuits are controlled by a timing signal called a
76 A
a) Clock b) Pulse c) FlipFlop d) Registers
Clock defines regular time intervals called
77 a) Instruction Cycle b) Interrupt Cycle c) Clock Cycle d) Fetch Cycle C
Overlapping the execution of successive instructions called
78 B
a) Vector Processing b) Pipelining c) Array Processing d) Central Processing
3 bits full adder contains
79 a) 3 combinational inputs b) 4 combinational inputs D
c) 6 combinational inputs d) 8 combinational inputs
translates high level language to machine language
80 C
a) Assembler b) Router c) Compiler d) Interpreter
hold the address which is to be accessed
81 D
a) MDR b) PC c) IR d) MAR
Operations executed on data stored registers are
82 a) Micro operations b) Mini operaions c) Large scale operations d) Small scale operations A
micro operations are performed on numeric data stored in registers
83 B
a) Register transfer b) Arithmetic c) Logic d) Shift
micro operations perform bit manipulation operations on non numeric data stored
84 in registers C
a) Register transfer b) Arithmetic c) Logic d) Shift
Addition , Subtraction, Increment and Decrement are
85 a) Register transfer micro operations b) Arithmetic micro operations B
c) Logic micro operations d) Shift micro operations
A number of storage registers connected to a common operational unit
86 a) ALU b) CU c) Input d) Output A
The code where all successive numbers differ from their preceding number by single bit is
87 a) Alphanumeric Code b) BCD c) Excess 3 d) Gray D
operation sets to 1 the bits in register A where the corresponding 1's in register B
88 B
a) Selective Clear b) Selective Set c) Selective Complement d) Selective Reset
operation complements bits in register A where there are corresponding 1's in
89 register B C
a) Selective Clear b) Selective Set c) Selective Complement d) Selective Reset
operation clears to zero the bits in A only where there are corresponding 1's in register B
90 a) Selective Clear b) Selective Set c) Selective Complement d) Selective Reset A
Mask operation is a micro operation
91 C
a) NAND b) NOR c) AND d) OR
Insert operation is a micro operation
92 D
a) NAND b) NOR c) AND d) OR
 Many to one combinational circuit is
93 a) Encoder b) Decoder c) Multiplexer d) Adder C
Expand PC
94 A
a) Program Counter b) Process Counter c) Program Circuit d) Parity Counter
Expand IR
95 a) Interrupt Register b) Instruction Register c) Isolated Rate d) Integrated Route B
Expand MDR
96 a) Massive data rate b) Memory Decode Register D
c) Memory Dual Register d) Memory Data Register
A bus system can be constructed with a
97 a) One stage gate b) Two stage gate c) Three stage gate d) Four stage gate C
The output which is not being driven to any defined logic level
98 B
a) Low Impedence state b) High Impedence state c) 0 State d) 1 State
A group of bits that tell the computer to perform a specific operation is known as .
99 A
a) Instruction code b) Micro-operation c) Accumulator d) Register
The time interval between adjacent bits is called the
100 a) Word-time b) Bit-time c) Turnaround time d) Slice time B
Model-3
In micro-programmed approach, the signals are generated by .
101 A
a) Machine instructions b) System programs c) Utility tools d) None of the above
A word whose individual bits represent a control signal is .
102 B
a) Command word b) Control word c) Co –ordination word d) Generation word
A sequence of control words corresponding to a control sequence is called .
103 a) Micro routine b) Micro function c) Micro procedure d) None of the above A
Individual control words of the micro routine are called as .
104 C
a) Micro task b) Micro operation c) Micro instruction d) Micro command
The special memory used to store the micro routines of a computer is .
105 B
a) Control table b) Control store c) Control mart d) Control shop
To read the control words sequentially is used.
106 a) PC b) IR c) UPC d) None of the above C
Every time a new instruction is loaded into IR the output of is loaded into UPC.
107 A
a) Starting address generator b) Loader c) Linker d) Clock
are the different type/s of generating control signals.
108 a) Micro-programmed b) Hardwired c) Micro-instruction d) Both a and b D
The type of control signal are generated based on
109 a) Contents of the step counter b) Contents of IR D
c) Contents of condition flags d) All of the above
What does the hardwired control generator consist of?
110 a) Decoder/encoder b) Condition codes c) Control step counter d) All of the above D
What does the end instruction do?
a) It ends the generation of a signal b) It ends the complete generation process
111 C
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor
The disadvantage/s of the hardwired approach is
112 a) It is less flexible b) It cannot be used for complex instructions D
c) It is costly d) Both a and b
 Processors of all computers must have
113 a) ALU b) Primary storage c) Control unit d) All the above D
What is the control unit's function in the CPU
114 a) To transfer data to primary storage b) To store program instruction D
c) To perform logic operation d) To decode program instruction
What is meant by a dedicated computer?
115 a) Which is used by one person only b) Which is assigned to one and only one task B
c) Which does one kind of software d) Which is meant for application software only
A micro program written as string of 0’s and 1’s is a
116 a) Symbolic microinstruction b) Binary microinstruction D
c) Symbolic micro program d) Binary micro program
When sending an assembly language instruction over a bus, it is put on which lines of the bus
117 C
a) Control lines b) Cache lines c) Data lines d) Address lines
Which register is used to generate the different control signals?
118 a) PC b) MAR c) MBR d) IR D
Which register is used to hold the address when either reading or writing?
119 a) PC b) MAR c) MBR d) IR B
Control memory is
120 B
a) RAM b) ROM c) Virtual memory d) Cache memory
Micro programmed control unit is than hardwired but
121 a) Cheaper, more error prone b) Faster, more error prone C
c) Less error prone, slower d) Faster, harder to change
The goals of both hardwired and micro program control unit is
122 a) Access memory b) Generate control signals B
c) Access the ALU b) Cost a lot of memory
A micro-programmed control unit
a) is faster than a hard wired control unit
123 b) facilitates easy implementation of new instructions B
c) is useful when very small programs are to be run
d) usually refers to the control unit of microprocessor
Control program memory can be reduced by
124 a) Horizontal format b) Vertical format micro program B
c) Hardwired control unit d) None of the above
Hardwired control is usually done in
125 A
a) RISC architecture b) CISC architecture c) Both a and b d) None of above