COM Express™ conga-TS175

7th Generation Intel® Core™ i7, i5, i3 and Xeon processor with either QM175, HM175, or CM238 Chipset

User’s Guide

Revision 1.5
Revision History
Revision Date (yyyy-mm-dd) Author Changes
0.1 2017-03-13 AEM • Preliminary release
1.0 2017-08-01 AEM • Updated sections 2.5 “Power Consumption” and 2.6 “Supply Voltage Battery Power”
• Updated sections 10 “Resource List” and 11 “BIOS Setup Description”
1.1 2018-05-07 AEM • Corrected the unit of measurement in table 5 “Power Consumption Values”
• Corrected a typographic error in section 6.1.11 “General Purpose Serial Interface”
• Corrected the pin numbers of USB ports 0 and 1 in table 16 “USB SignalDescriptions”
1.2 2018-08-24 AEM • Updated the cooling diagrams and heatspreader thermal imagery in section 4 “Cooling Solutions”
1.3 2018-10-12 AEM • Added note about recommended boot mode in section 2.2 “Supported Operating Systems”
• Changed Intel 100 series PCH to Intel PCH
1.4 2019-04-25 AEM • Updated all cross references
• Updated section 2.3 “Mechanical Dimensions”
• Updated sections 4 .1 “CSA Dimensions”, 4.2 “CSP Dimensions”, 4.3 “HSP Dimensions”
• Updated sections 11.3 “Updating the BIOS“ and 11.4 “Supported Flash Devices”
1.5 2020-05-08 AEM • Updated section 4 “Cooling Solutions”
• Corrected the resolutions for three independent displays in table 7 “Maximum Supported Resolutions”
• Updated the link for power supply implementation guidelines in section 6.1.13 “Power Control”
• Added note about the minimum pulse width required for proper button detection in table 24 “Power and System
Management Signal Descriptions”
• Added information about congatec MLF file to section 11 “BIOS Setup Description”.
• Corrected typographic error in section 11.5 “Supported Flash Devices”
• Deleted section 12 “Industry Specifications”
• Restructured the whole document

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Preface
This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-TS175. It is
one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should
be used include the following:
COM Express™ Design Guide
COM Express™ Specification
The links to these documents can be found on the congatec AG website at www.congatec.com

Disclaimer
The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice.

congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims
any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes
no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for
discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or
exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information
contained herein or the use thereof.

Intended Audience
This user’s guide is intended for technically qualified personnel. It is not intended for general audiences.

Lead-Free Designs (RoHS)

All congatec AG designs are created from lead‑free components and are completely RoHS compliant.

Copyright © 2017 congatec AG TSKLm15 3/72

Electrostatic Sensitive Device
All congatec AG products are electrostatic sensitive devices. They are enclosed in static shielding bags, and shipped enclosed in secondary
packaging (protective packaging). The secondary packaging does not provide electrostatic protection.

Do not remove the device from the static shielding bag or handle it, except at an electrostatic-free workstation. Also, do not ship or store
electronic devices near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original
packaging. Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty.

Symbols
The following symbols are used in this user’s guide:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note
Notes call attention to important information that should be observed.

Trademarks
Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property
of their respective trademark holders. These trademark holders are not affiliated with congatec AG, our products, or our website.

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Copyright Notice
Copyright © 2017, congatec AG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted
without written permission from congatec AG.

congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is
supplied “as-is”.

Warranty
congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited
warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and
conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and
from time to time.

The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license
agreements, which are available at www.congatec.com and/or upon request.

Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the
products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or
due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec’s option and expense.

Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight
prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.

Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged
or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to
congatec’s direct customer only and is not assignable or transferable.

Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either
express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of
fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.

congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be
liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive
remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the
product only.

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 ISO 9001
Certification
congatec AG is certified to DIN EN ISO 9001 standard.
C N
ER
T I F I C AT I O TM

Technical Support
congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products
can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities
and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical
support department by email at [email protected]

Terminology

Term Description
GB Gigabyte
GHz Gigahertz
kB Kilobyte
MB Megabyte
Mb Megabit
kHz Kilohertz
MHz Megahertz
TDP Thermal Design Power
PCIe PCI Express
SATA Serial ATA
PEG PCI Express Graphics
PCH Platform Controller Hub
eDP Embedded DisplayPort
DDI Digital Display Interface
HDA High Definition Audio
N.C Not connected
N.A Not available
TBD To be determined

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Contents
1 Introduction.............................................................................. 10 6.1.6 SATA™...................................................................................... 30
6.1.7 USB........................................................................................... 30
1.1 COM Express™ Concept.......................................................... 10
6.1.8 Gigabit Ethernet ...................................................................... 31
1.2 Options Information.................................................................. 11
6.1.9 High Definition Audio (HDA) Interface..................................... 31
2 Specifications............................................................................ 12 6.1.10 LPC Bus..................................................................................... 31
2.1 Feature List............................................................................... 12 6.1.11 I²C Bus...................................................................................... 31
2.2 Supported Operating Systems................................................. 13 6.1.12 ExpressCard™.......................................................................... 31
2.3 Mechanical Dimensions............................................................ 13 6.1.13 General Purpose Serial Interface.............................................. 32
2.4 Supply Voltage Standard Power............................................... 14 6.1.14 GPIOs........................................................................................ 32
2.4.1 Electrical Characteristics........................................................... 14 6.1.15 Power Control........................................................................... 32
2.4.2 Rise Time.................................................................................. 14 6.1.16 Power Management.................................................................. 36
2.5 Power Consumption................................................................. 15 7 Additional Features................................................................... 37
2.6 Supply Voltage Battery Power.................................................. 16
7.1 congatec Board Controller (cBC).............................................. 37
2.7 Environmental Specifications.................................................... 17
7.1.1 Board Information..................................................................... 37
3 Block Diagram........................................................................... 18 7.1.2 General Purpose Input/Output................................................. 37
7.1.3 Watchdog................................................................................. 37
4 Cooling Solutions...................................................................... 19 7.1.4 I2C Bus....................................................................................... 37
4.1 CSA Dimensions....................................................................... 20 7.1.5 Power Loss Control................................................................... 38
4.2 CSP Dimensions........................................................................ 21 7.1.6 Fan Control............................................................................... 38
4.3 HSP Dimensions........................................................................ 22 7.2 OEM BIOS Customization......................................................... 38
4.4 Heatspreader Thermal Imagery................................................ 23 7.2.1 OEM Default Settings............................................................... 38
7.2.2 OEM Boot Logo........................................................................ 39
5 Onboard Temperature Sensors................................................. 24
7.2.3 OEM POST Logo...................................................................... 39
7.2.4 OEM BIOS Code/Data.............................................................. 39
6 Connector Rows........................................................................ 26
7.2.5 OEM DXE Driver....................................................................... 39
6.1 Primary and Secondary Connector Rows.................................. 26 7.3 congatec Battery Management Interface................................. 40
6.1.1 PCI Express™............................................................................ 26 7.4 API Support (CGOS)................................................................. 40
6.1.2 PCI Express Graphics (PEG)...................................................... 26 7.5 Security Features....................................................................... 40
6.1.3 Digital Display Interface............................................................ 27 7.6 Suspend to Ram........................................................................ 40
6.1.3.1 DisplayPort (DP)........................................................................ 28
8 conga Tech Notes..................................................................... 41
6.1.3.2 HDMI......................................................................................... 29
6.1.3.3 DVI............................................................................................ 29 8.1 Intel® Processor Features.......................................................... 41
6.1.4 LVDS/eDP.................................................................................. 29 8.1.1 Adaptive Thermal Monitor and Catastrophic Thermal Protection
6.1.5 VGA.......................................................................................... 30 41

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8.1.2 Intel® Turbo Boost Technology................................................. 42
8.1.3 Intel® Virtualization Technology................................................ 42
8.1.4 Thermal Management.............................................................. 43
8.1.5 Processor Performance Control................................................ 43
8.2 ACPI Suspend Modes and Resume Events............................... 44
8.3 DDR4 Memory.......................................................................... 44
9 Signal Descriptions and Pinout Tables...................................... 45
9.1 Connector Signal Descriptions................................................. 46
9.2 Boot Strap Signals.................................................................... 67
10 System Resources..................................................................... 68
10.1 I/O Address Assignment........................................................... 68
10.1.1 LPC Bus..................................................................................... 68
10.2 PCI Configuration Space Map.................................................. 69
10.3 I2C............................................................................................. 70
10.4 SM Bus...................................................................................... 70
11 BIOS Setup Description............................................................ 71
11.1 Navigating the BIOS Setup Menu............................................ 71
11.2 BIOS Versions........................................................................... 71
11.3 Updating the BIOS.................................................................... 72
11.4 Recovering from External Flash................................................ 72
11.5 Supported Flash Devices.......................................................... 72

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List of Tables
Table 1 COM Express™ 2.1 Pinout Types............................................. 10 Table 36 PCI Configuration Space Map.................................................. 69
Table 2 conga-TS175 Variants............................................................... 11
Table 3 Feature Summary...................................................................... 12
Table 4 Measurement Description......................................................... 15
Table 5 Power Consumption Values...................................................... 16
Table 6 CMOS Battery Power Consumption......................................... 16
Table 7 Cooling Solution Variants.......................................................... 19
Table 8 Maximum Supported Resolutions............................................. 28
Table 9 Wake Events.............................................................................. 44
Table 10 Signal Tables Terminology Descriptions................................... 45
Table 11 Connector A–B Pinout.............................................................. 46
Table 12 Connector C–D Pinout.............................................................. 48
Table 13 PCI Express Signal Descriptions (general purpose).................. 50
Table 14 PCI Express Signal Descriptions (x16 Graphics)........................ 51
Table 15 DDI Signal Description.............................................................. 53
Table 16 HDMI Signal Descriptions......................................................... 55
Table 17 DisplayPort (DP) Signal Descriptions........................................ 56
Table 18 Embedded DisplayPort Signal Descriptions............................. 57
Table 19 CRT Signal Descriptions............................................................ 58
Table 20 LVDS Signal Descriptions.......................................................... 58
Table 21 Serial ATA Signal Descriptions.................................................. 59
Table 22 USB 2.0 Signal Descriptions...................................................... 59
Table 23 USB 3.0 Signal Descriptions...................................................... 60
Table 24 Gigabit Ethernet Signal Descriptions....................................... 61
Table 25 Intel® High Definition Audio Link Signals Descriptions............. 61
Table 26 ExpressCard Support Pins Signal Descriptions......................... 62
Table 27 LPC Signal Descriptions............................................................ 62
Table 28 SPI BIOS Flash Interface Signal Descriptions............................ 62
Table 29 Miscellaneous Signal Descriptions............................................ 63
Table 30 General Purpose I/O Signal Descriptions................................. 63
Table 31 Power and System Management Signal Descriptions.............. 64
Table 32 General Purpose Serial Interface Signal Descriptions............... 65
Table 33 Module Type Definition Signal Description.............................. 65
Table 34 Power and GND Signal Descriptions........................................ 66
Table 35 Boot Strap Signal Descriptions................................................. 67

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1 Introduction
1.1 COM Express™ Concept
COM Express™ is an open industry standard defined specifically for COMs (computer on modules). Its creation makes it possible to smoothly
transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form factors:
• Mini 84 mm x 55 mm
• Compact 95 mm x 95 mm
• Basic 125 mm x 95 mm
• Extended 155 mm x 110 mm
Table 1 COM Express™ 2.1 Pinout Types

Types Connector Rows PCIe Lanes PCI IDE SATA Ports LAN ports USB 2.0/ USB 3.0 Display Interfaces
Type 1 A-B Up to 6 - 4 1 8/0 VGA, LVDS
Type 2 A-B C-D Up to 22 32 bit 1 4 1 8/0 VGA, LVDS, PEG/SDVO
Type 3 A-B C-D Up to 22 32 bit - 4 3 8/0 VGA,LVDS, PEG/SDVO
Type 4 A-B C-D Up to 32 1 4 1 8/0 VGA,LVDS, PEG/SDVO
Type 5 A-B C-D Up to 32 - 4 3 8/0 VGA,LVDS, PEG/SDVO
Type 6 A-B C-D Up to 24 - 4 1 8 / 4* VGA,LVDS/eDP, PEG, 3x DDI
Type 10 A-B Up to 4 - 2 1 8/0 LVDS/eDP, 1xDDI

* The SuperSpeed USB ports (USB 3.0) are not in addition to the USB 2.0 ports. Up to 4 of the USB 2.0 ports can support SuperSpeed USB.

The conga-TS175 modules use the Type 6 pinout definition and comply with COM Express 2.1 specification. They are equipped with two high
performance connectors that ensure stable data throughput.

The COM (computer on module) integrates all the core components and is mounted onto an application specific carrier board. COM modules
are legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These
functions include, but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial ATA,
USB 2.0, and Gigabit Ethernet. The Type 6 pinout provides the ability to offer PCI Express, Serial ATA, and LPC options thereby expanding
the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is
perfectly suited for all applications.

Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all
the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a
dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™

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 modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use
of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary.

1.2 Options Information

The conga-TS175 is currently available in seven variants. The table below shows the different configurations available.

Table 2 conga-TS175 Variants

Part-No. 045950 045951 045952 045953 045954

Processor Intel® Core™ i7-7820EQ Intel® Core™ i5-7440EQ Intel® Core™ i5-7442EQ Intel® Core™ i3-7100E Intel® Core™ i3-7102E
3.0 GHz Quad Core™ 2.9 GHz Quad core 2.1 GHz Quad Core™ 2.9 GHz Dual Core™ 2.1 GHz, Dual Core™
Max. Turbo Frequency 3.7 GHz 3.6 GHz 2.9 GHz N.A N.A
Chipset ®
Intel QM175 ®
Intel QM175 ®
Intel QM175 ®
Intel HM175 Intel® HM175
Intel Smart Cache
®
8 MB 6 MB 6 MB 3 MB 3 MB
Processor Graphics Intel® HD Graphics 630 Intel® HD Graphics 630 Intel® HD Graphics 630 Intel® HD Graphics 630 Intel® HD Graphics 630
(GT2) (GT2) (GT2) (GT2) (GT2)
GFX Base/Max. Dynamic Freq. 350 MHz / 1 GHz 350 MHz / 1 GHz 350 MHz / 1 GHz 350 MHz / 950 MHz 350 MHz / 950 MHz
Memory (DDR4) 2400 MT/s Dual Channel 2400 MT/s Dual Channel 2400 MT/s Dual Channel 2400 MT/s Dual Channel 2400 MT/s Dual Channel
LVDS Yes Yes Yes Yes Yes
DisplayPort (DP) Yes Yes Yes Yes Yes
HDMI Yes Yes Yes Yes Yes
Processor TDP (cTDP) 45 W (35 W) 45 W (35 W) 25 W (N.A) 35 W (N.A) 25 W (N.A)

Part-No. 045955 (ECC) 045956 (ECC)

Processor Intel® Xeon® E3-1505MV6 Intel® Xeon® E3-1505LV6
3.0 GHz Quad Core™ 2.2 GHz Quad Core™
Max. Turbo Frequency 4.0 GHz 3.0 GHz
Chipset ®
Intel CM238 Intel® CM238
Intel Smart Cache
®
8 MB 8 MB
Processor Graphics Intel® HD Graphics P630 Intel® HD Graphics P630
(GT2) (GT2)
GFX Base/Max. Dynamic Freq. 350 MHz / 1.1 GHz 350 MHz / 1 GHz
Memory (DDR4) 2400 MT/s Dual Channel (ECC) 2400 MT/s Dual Channel (ECC)
LVDS Yes Yes
DisplayPort (DP) Yes Yes
HDMI Yes Yes
Processor TDP (cTDP) 45 W (35 W) 25 W (N.A)

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2 Specifications
2.1 Feature List
Table 3 Feature Summary

Form Factor Based on COM Express™ standard pinout Type 6 Rev. 2.1 (Basic size 125 x 95 mm)
Processor 7th Generation Intel® Core i7,i5,i3, Celeron and Xeon mobile processors
Memory Two memory sockets (located on the top and bottom side of the conga-TS175). Supports
- SO-DIMM non-ECC DDR4 modules
- Data rates up to 2400 MT/s
- Maximum 32 GB capacity (16 GB each)
NOTE: Variants that feature the Intel CM238 chipset support ECC memory
Chipset Mobile Intel® 100 Series Chipset QM175, HM175 and CM238 PCH
Audio High definition audio interface with support for multiple codecs
Ethernet Gigabit Ethernet (Intel® i219-LM controller) with AMT 11.6 support
Graphics Options Next Generation Intel® HD (610/620). Supports:
- API (DirectX 12, OpenGL 4.4, OpenCL 2.1)
- Intel® QuickSync & Clear Video Technology HD (hardware accelerated video decode/encode/processing/transcode)
- Switchable/Hybrid graphics
- Up to 3 independent displays (must be two DDI’s (DP, HDMI/DVI) and one eDP/LVDS)
1x LVDS Optional Interface (assembly option):
1x VGA *3 - 1x eDP 1.4
1x PEG Gen 3 port (x16 lanes) NOTE:
Up to 3x DDIs with support for: *1 Requires an external level shifter on the carrier board.
- 3x DisplayPort++ (DisplayPort 1.2) *2 Requires a Level Shifter Protocol Converter (LSPCON) on the carrier board.
- 3x HDMI 1.4a*1 or HDMI 2.0 *1 *2 *3 The third DDI interface (port D) supports only HDMI/DVI if VGA is enabled
- 3x DVI port *1 in the BIOS menu.
- Resolutions up to 4K
Peripheral USB Interfaces: GPIOs
Interfaces - Up to 8x USB 2.0 LPC
- Up to 4x USB 3.0 I2C (fast mode, multi-master)
4x SATA (6 Gb/s with RAID 0/1/5 support)
®
SMB
8x PCI Express® Gen. 3 lanes *1 SPI
2x UART
BIOS AMI Aptio® V UEFI 2.x firmware, 8 or 16 MByte serial SPI with congatec Embedded BIOS features
Power ACPI 5.0 compliant with battery support. Also supports DeepSx and Suspend to RAM (S3)
Management
congatec Board Multi-stage watchdog, non-volatile user data storage, manufacturing and board information, board statistics, hardware monitoring, fan control, I²C bus,
Controller power loss control
Security Optional discrete Trusted Platform Module “TPM 1.2/2.0”; AES Instructions

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 Note
Some of the features mentioned in the above feature summary are optional.

2.2 Supported Operating Systems

The conga-TS175 supports the following operating systems.
• Microsoft® Windows® 10
• WindRiver® VxWorks® (VX7 or later)
• Linux
Note
1. The processor supports only 64-bit operating systems.

2. The CSM (Compatibility Support Module) is disabled in the BIOS setup menu by default because we recommend to operate the system
in native UEFI mode.

2.3 Mechanical Dimensions

• 125.0 mm x 95.0 mm
• Height approximately 18 or 21 mm (including heatspreader) depending on the carrier board connector that is used. If the 5 mm (height)
carrier board connector is used, then approximate overall height is 18 mm. If the 8mm (height) carrier board connector is used, then
approximate overall height is 21 mm.

Heatspreader

Module PCB

4.00

7.00 13.00
18.00
5.00 2.00±10%

4.50 All dimensions in millimeter

Carrier Board PCB

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2.4 Supply Voltage Standard Power
• 12V DC ± 5%
The dynamic range shall not exceed the static range.

12.60V Absolute Maximum

Dynamic Range
12.10V
12V Nominal Static Range
11.90V

11.40V Absolute Minimum

2.4.1 Electrical Characteristics

Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for
pinout Type 6 (dual connector, 440 pins).

Power Rail Module Pin Nominal Input Derated Max. Input Ripple Max. Module Input Assumed Max. Load
Current Capability Input Range Input (10Hz to 20MHz) Power (w. derated input) Conversion Power
(Amps) (Volts) (Volts) (Volts) (mV) (Watts) Efficiency (Watts)
VCC_12V 12 12 11.4-12.6 11.4 +/- 100 137 85% 116
VCC_5V-SBY 2 5 4.75-5.25 4.75 +/- 50 9
VCC_RTC 0.5 3 2.5-3.3 +/- 20

2.4.2 Rise Time

The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during
the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

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2.5 Power Consumption
The power consumption values were measured with the following setup:
• Input voltage +12 V
• conga-TS175 COM
• modified congatec carrier board
• conga-TS175 cooling solution
• Microsoft Windows 10 (64 bit)
Note

The CPU was stressed to its maximum workload.

Table 4 Measurement Description

The power consumption values were recorded during the following system states:

System State Description Comment

S0: Minimum value Lowest frequency mode (LFM) with minimum core voltage during desktop idle
S0: Maximum value Highest frequency mode (HFM/Turbo Boost) The CPU was stressed to its maximum frequency
S0: Peak current Highest current spike during the measurement of “S0: Maximum value”. This Consider this value when designing the system’s power supply to
state shows the peak value during runtime ensure that sufficient power is supplied during worst case scenarios
S3 COM is powered by VCC_5V_SBY
S5 COM is powered by VCC_5V_SBY

Note

1. The fan and SATA drives were powered externally.

2. All other peripherals except the LCD monitor were disconnected before measurement.

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 Table 5 Power Consumption Values

The table below provides additional information about the conga-TS175 power consumption. The values are recorded at various operating
mode.

Part Memory H.W BIOS OS CPU Current (A)

No. Size Rev. Rev. (64 bit) Variant Cores Freq /Max Turbo (GHz) S0: Min S0: Max S0:Peak S3 S5
045950 4 GB B.0 R004 Windows 10 Intel® Core™ i7-7820EQ 4 3.0 / 3.7 0.63 5.93 6.53 0.09 0.06
045951 4 GB B.0 R004 Windows 10 Intel® Core™ i5-7440EQ 4 2.9 / 3.6 0.63 5.66 5.91 0.09 0.06
045952 4 GB B.0 R004 Windows 10 Intel® Core™ i5-7442EQ 4 2.1 / 2.9 0.62 3.03 3.41 0.09 0.06
045953 4 GB B.0 R004 Windows 10 Intel® Core™ i3-7100E 2 2.9 / N.A 0.62 3.41 4.00 0.09 0.06
045954 4 GB B.0 R004 Windows 10 Intel® Core™ i3-7102E 2 2.1 / N.A 0.61 2.36 2.79 0.09 0.06
045955 4 GB B.0 R004 Windows 10 Intel® Xeon® E3-1505MV6 4 3.0 / 4.0 0.61 5.56 6.28 0.09 0.06
045956 4 GB B.0 R004 Windows 10 Intel® Xeon® E3-1505LV6 4 2.2 / 3.0 0.62 3.15 3.49 0.09 0.06

2.6 Supply Voltage Battery Power

Table 6 CMOS Battery Power Consumption

RTC @ Voltage Current

-10 C
o
3V DC 1.30 µA
20 C
o
3V DC 1.46 µA
70oC 3V DC 2.00 µA

Note

1. Do not use the CMOS battery power consumption values listed above to calculate CMOS battery lifetime.

2. Measure the CMOS battery power consumption of your application in worst case conditions (for example, during high temperature and
high battery voltage).

3. Consider the self-discharge of the battery when calculating the lifetime of the CMOS battery. For more information, refer to application
note AN9_RTC_Battery_Lifetime.pdf on congatec AG website at www.congatec.com/support/application-notes.

4. We recommend to always have a CMOS battery present when operating the conga-TS175.

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2.7 Environmental Specifications
Temperature Operation: 0° to 60°C Storage: -20° to +80°C

Humidity Operation: 10% to 90% Storage: 5% to 95%

Caution

The above operating temperatures must be strictly adhered to at all times. When using a congatec heatspreader, the maximum operating
temperature refers to any measurable spot on the heatspreader’s surface.

Humidity specifications are for non-condensing conditions.

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3 Block Diagram
COM Express COM Express
7th Gen. Intel® Core™ processor
Type 6 Type 6
Aux Channel
CPU Platform
A-B Connector C-D Connector
Turbo Boost 2.0 Technology TXT VT
HT Technology 64 Architecture AES-NI

AVX2 SSE 4.2 TSX

DP to VGA
Integrated Intel HD Graphics *1 DP/HDMI Port D
Display Interface DP/HDMI Port C
DisplayPort 1.2 HDMI 2.0 (3D, 4k) DP/HDMI Port B
PCIe Gen. 3 PEG x16
VGA
Hardware Graphics Accelerators
LVDS/eDP eDP to LVDS eDP
LVDS/eDP Bridge 3D Vector Graphics

2D DXVA2

Video Codecs APIs PECI

XDP
MPEG-2 OpenCL 2.1
2x SO-DIMM (X1/X2)
HEVC/H.265 OpenGL 4.4
VC1/WMV9 DirectX 12 Dual Channel DDR4

Multimedia Features
ASRC
SM Bus

DMI Gen3
PECI
HDA
HDA I/F Mobile Intel® 100 Series PCH-H USB 3.0 Port 0 - 3
USB 2.0
USB Port 0..7
PCIe Gen. 3 PCIe Gen. 3
PCIe lane 0 - 5 PCIe lane 6 - 7
Ethernet 10/100/1000 MGMNT
Ethernet Intel i219LM
I/O Interfaces
SPI Flash 0 SPI
PCIe LPC Bus HDA
congatec System (TX BC)
SPI Management congatec custom
SATA 6G SATA USB 2.0 USB 3.0 Controller
SATA Port 0 - 3
LPC
LPC Bus
TPM
SM Bus

SER0/1 UART0/1
GPIOs
LID#/SLEEP#
FAN control
I2C Bus

Note:

*1 DDI port D supports only HDMI if VGA is enabled

Copyright © 2017 congatec AG TSKLm15 18/72

4 Cooling Solutions
congatec AG offers the following cooling solutions for the conga-TS175 variants. The dimensions of the cooling solutions are shown in the
sub-sections. All measurements are in millimeters.

Table 7 Cooling Solution Variants

Cooling Solution Part No. Description

1 CSA 045930 Active cooling solution with integrated heat pipes and 2.7 mm bore-hole standoffs
045931 Active cooling solution with integrated heat pipes and M2.5 mm threaded standoffs
2 CSP 045932 Passive cooling solution with integrated heat pipes and 2.7 mm bore-hole standoffs
045933 Passive cooling solution with integrated heat pipes and M2.5 mm threaded standoffs
3 HSP 045934 Heatspreader with integrated heat pipes and 2.7 mm bore-hole standoffs
045935 Heatspreader with integrated heat pipes and M2.5 mm threaded standoffs

Note

1. We recommend a maximum torque of 0.4 Nm for carrier board mounting screws and 0.5 Nm for module mounting screws.

2. The gap pad material used on congatec heatspreaders may contain silicon oil that can seep out over time depending on the environmental
conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap
pad material manufacturer’s specification

Caution

1. The congatec heatspreaders/cooling solutions are tested only within the commercial temperature range of 0° to 60°C. Therefore, if your
application that features a congatec heatspreader/cooling solution operates outside this temperature range, ensure the correct operating
temperature of the module is maintained at all times. This may require additional cooling components for your final application’s thermal
solution.

2. For adequate heat dissipation, use the mounting holes on the cooling solution to attach it to the module. Apply thread-locking fluid on
the screws if the cooling solution is used in a high shock and/or vibration environment. To prevent the standoff from stripping or cross-
threading, use non-threaded carrier board standoffs to mount threaded cooling solutions.

3. For applications that require vertically-mounted cooling solution, use only coolers that secure the thermal stacks with fixing post. Without
the fixing post feature, the thermal stacks may move.

4. Do not exceed the recommended maximum torque. Doing so may damage the module or the carrier board, or both.
Copyright © 2017 congatec AG TSKLm15 19/72
4.1 CSA Dimensions

29
87 21 96.6

31 14.5 20 95

58.5

76
79

125
117

12.5
M2.5 x 13 mm F

15
threaded standoff
for threaded version

28
or
7,3 ±0,2
7,3

ø2.7 x 13 mm
non-threaded standoff
for borehole version

2.7 2.7 .3
R0

1.24°
0.62°

.9
R0

Copyright © 2017 congatec AG TSKLm15 20/72

4.2 CSP Dimensions
87 28

31 14.5 20 95

58.5

76
79

117

125
M2.5 x 13 mm
threaded standoff E
for threaded version

15

28
or
ø2.7 x 13 mm
non-threaded standoff
for borehole version
2.7 2.7
R0.3

1.24°
0.62°
.9
R0

Copyright © 2017 congatec AG TSKLm15 21/72

4.3 HSP Dimensions

87
11
56 4 95
41.5

58.5
76
79

125
117

M2.5 x 11 mm
threaded standoff
for threaded version
or
ø2.7 x 11 mm
non-threaded standoff
for borehole version

Copyright © 2017 congatec AG TSKLm15 22/72

4.4 Heatspreader Thermal Imagery
The conga-TS175 heatspreader solution features heat pipes. A heat pipe is a simple device that can quickly transfer heat from one point to
another. They are often referred to as the “superconductors” of heat as they possess an extra ordinary heat transfer capacity and rate with
almost no heat loss. The thermal image below provides a reference to where the heat is being transferred to on the heatspreader surface area.
System designers must ensure that the system’s cooling solution is designed to dissipate the heat from the hottest surface spots of the
heatspreader.

Copyright © 2017 congatec AG TSKLm15 23/72

5 Onboard Temperature Sensors
The conga-TS175 features two sensors on the top side of the module and two optional DRAM sensors (build-time) on the top and bottom side
of the module.

Top-Side (CPU Temperature & Board Temperature Sensor) :

The CPU temperature sensor (T00) is located in the CPU (U1). This sensor measures the CPU temperature and is defined in CGOS API as
CGOS_TEMP_CPU.

The board temperature sensor (T01) is located in the congatec Board Controller (U22). This sensor measures the board temperature and is
defined in CGOS API as CGOS_TEMP_BOARD.

The sensor locations are shown below:

Optional DRAM Sensor Location
(BOM option)

Board Controller Temp. Sensor

U8

T01
U22

CPU Temperature Sensor

T00
U1

Copyright © 2017 congatec AG TSKLm15 24/72

Bottom-Side (Optional DRAM Sensor):

The conga-TS175 offers an optional sensor on the bottom side of the module. This sensor measures the temperature of the DRAM module and
is defined in CGOS API as CGOS_TEMP_BOTDIMM_ENV.

The DRAM sensor location is shown below:

Optional DRAM Sensor Location

(BOM option)

Note

The optional DRAM sensors are not populated on conga-TS175 standard variants. The sensors are only available as assembly option.

Copyright © 2017 congatec AG TSKLm15 25/72

6 Connector Rows
The conga-TS175 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout). These connectors are broken
down into four rows. The primary connector consists of rows A and B while the secondary connector consists of rows C and D.

6.1 Primary and Secondary Connector Rows

The following subsystems can be found on the primary and secondary connector rows.

6.1.1 PCI Express™

The conga-TS175 offers six PCI Express™ lanes on the A–B connector and two lanes on the C–D connector. The lanes support:
• up to 8 GT/s (Gen 3) speed
• a 8 x1 link configuration
• other link configurations (requires a special/customized BIOS firmware)
• lane polarity inversion

6.1.2 PCI Express Graphics (PEG)

The conga-TS175 offers a PCI Express™ Graphics interface on the C–D connector. The interface supports the following:
• a 1 x16 (default), 2 x8 or 1 x8 + 2 x4 link configuration
• up to 8 GT/s (Gen 3) speed
• optional configuration to support graphics or non-graphic devices or both
• a x1, x2, x4 or x8 PCIe device
• up to three devices operating simultaneously on the PEG interface
• lane reversal

Copyright © 2017 congatec AG TSKLm15 26/72

 The possible configurations are 1 x16 link (default), 2 x8 links or 1 x8 + 2 x4 links as shown in the diagram below:

PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG PEG
LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE LANE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Single Link (1x16 Link)

Link 1

Double Links (2x8 Links)

Link 1 Link 2

Triple Links (1x8 + 2x4 Links)

Link 1 Link 2 Link 3

Note

The PEG lanes can not be linked together with the PCI Express lanes discussed in section 6.1.1 “PCI Express™”.

6.1.3 Digital Display Interface

The conga-TS175 supports the following:
• up to three Digital Display Interfaces (DDI1, DDI2 and DDI3, configurable as DisplayPort or HDMI/DVI
• dual mode DisplayPort (DP++)
• three independent displays (see table below)
• Aux channel for VGA interface

Copyright © 2017 congatec AG TSKLm15 27/72

 The table below shows the supported display combinations and resolutions.

Table 8 Maximum Supported Resolutions

Display 1 Display 2 Display 3

External Max. Resolution External Max. Resolution Internal/External Max. Resolution
Option 1 DP/ 4096x2304 @ 60Hz, 24 bpp/ DP/ 4096x2304 @ 60Hz, 24 bpp/ DP/ 4096x2304 @ 60Hz, 24 bpp/
HDMI 4096x2160 @ 30Hz, 24 bpp HDMI 4096x2160 @ 30Hz, 24 bpp HDMI 4096x2160 @ 30Hz, 24 bpp
Option 2 DP/ 4096x2304 @ 60Hz, 24 bpp/ DP/ 4096x2304 @ 60Hz, 24 bpp/ LVDS 1920x1200 @ 60Hz (dual LVDS mode)
HDMI 4096x2160 @ 30Hz, 24 bpp HDMI 4096x2160 @ 30Hz, 24 bpp eDP (BOM Option) 4096x2304 @ 60Hz, 24bpp
Option 3 DP/ 4096x2304 @ 60Hz, 24 bpp/ DP/ 4096x2304 @ 60Hz, 24 bpp/ VGA 1920x1200 @ 60Hz
HDMI 4096x2160 @ 30Hz, 24 bpp HDMI 4096x2160 @ 30Hz, 24 bpp
Option 4 DP/ 4096x2304 @ 60Hz, 24 bpp/ VGA 1920x1200 @ 60Hz LVDS 1920x1200 @ 60Hz (dual LVDS mode)
HDMI 4096x2160 @ 30Hz, 24 bpp eDP (BOM Option) 4096x2304 @ 60Hz, 24bpp

Note

1. The third DDI interface (DDI3) supports only HDMI/DVI if the VGA interface is enabled in the BIOS menu.

2. To enable VGA interface, go to the Advanced -> Graphics menu and set the value for Digital Display Interface 3 option to HDMI/DVI.

6.1.3.1 DisplayPort (DP)

The conga-TS175 supports the following features:

• up to three dual mode DP ports (DP++)
• VESA DisplayPort Standard versions 1.2 including Multi-Stream Transport (MST) for monitor daisy-chaining, stereoscopic 3D frame transport
and maximun bit rate of 5.4 Gb/s
• audio formats such as linear PCM, Dolby Digital (AC-3), Dolby TrueHD, DTS, DTS-HD Master Audio and up to 8 channels
• up to three independent DP displays
Note

A maximum of two independent DP displays are supported if the VGA interface is enabled.

Copyright © 2017 congatec AG TSKLm15 28/72

6.1.3.2 HDMI

The conga-TS175 supports the following:

• up to three HDMI ports
• HDMI 1.4 specification
• up to 4096x2160 resolutions at 30 Hz
• 3D, 4Kx2K@24Hz and Deep Color
• audio formats such as AC-3 Dolby Digital, Dolby Digital Plus, DTS-HD, LPCM, 192 kHz/24 bit, 8 channel, Dolby TrueHD, DTS-HD Master
Audio (Lossless Blu-Ray Disc Audio Format).
Note

HDMI 2.0 support is possible via a Level Shifter Protocol Converter (LSPCON) on the carrier board.

6.1.3.3 DVI

The conga-TS175 offers three DVI ports on the C–D connector. The DVI interfaces are multiplexed onto the Digital Display Interface of the
COM Express connector with support for maximum resolution of 1920x1200 at 60 Hz.

6.1.4 LVDS/eDP
The conga-TS175 offers an LVDS interface. The interface supports the following:
• optional eDP overlay on the A–B connector via a hardware change (assembly option)
• single or dual channel LVDS (color depths of 18 bpp or 24 bpp)
• integrated flat panel interface with clock frequency up to 112 MHz
• VESA and OpenLDI LVDS color mappings
• automatic panel detection via Embedded Panel Interface based on VESA EDIDTM 1.3
• resolution up to 1920x1200 in dual LVDS bus mode
Note

The LVDS/eDP interface supports either LVDS or eDP signals. Both interfaces are not supported simultaneously.

Copyright © 2017 congatec AG TSKLm15 29/72

6.1.5 VGA
The conga-TS175 offers a VGA interface via an eDP to VGA converter, connected to the upper two data lanes on the embedded DisplayPort.

Note

To enable VGA interface, set the Digital Display Interface 3 to HDMI/DVI from the BIOS menu.

6.1.6 SATA™
The conga-TS175 offers four SATA interfaces (SATA 0-3) on the A–B connector. The interfaces support:
• independent DMA operation
• data transfer rates up to 6.0 Gb/s
• AHCI mode using memory space and RAID mode
• Hot-plug detect

6.1.7 USB
The conga-TS175 offers eight USB 2.0 interfaces on the A–B connector and four SuperSpeed signals on the C–D connector. The xHCI host
controller supports:
• USB 3.0 specification
• SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling
• data transfers of up to 5 Gb/s
• supports USB debug port on all USB 3.0 capable ports
Note

The xHCI controller supports USB debug port on all USB 3.0 capable ports.

Copyright © 2017 congatec AG TSKLm15 30/72

6.1.8 Gigabit Ethernet
The conga-TS175 offers a Gigabit Ethernet interface via an onboard Intel® i219-LM Phy. The interface supports full-duplex operation at
10/100/1000 Mb/s and half-duplex operation at 10/100 Mb/s.
Note

1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation
of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#.

2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS175 module.

6.1.9 High Definition Audio (HDA) Interface

The conga-TS175 provides an interface that supports the connection of HDA audio codecs.

6.1.10 LPC Bus

The conga-TS175 offers the LPC (Low Pin Count) bus through the Intel® PCH-LP. For information about the decoded LPC addresses, see section
10.1.1.

6.1.11 I²C Bus

The I²C bus is implemented through the congatec board controller (Texas Instruments Tiva™ TM4E1231H6ZRB) and accessed through the
congatec CGOS driver and API. The controller provides a fast-mode multi-master I²C bus that has the maximum I²C bandwidth.

6.1.12 ExpressCard™
The conga-TS175 supports the implementation of ExpressCards, which requires the dedication of one USB 2.0 port or a x1 PCI Express link for
each ExpressCard used.

Copyright © 2017 congatec AG TSKLm15 31/72

6.1.13 General Purpose Serial Interface
The conga-TS175 offers two UART interfaces via the congatec Board Controller. These interfaces support up to 1 Mb/s and can operate in low-
speed, full-speed and high-speed modes. The UART interfaces are routed to the A–B connector. They do not support hardware handshake
and flow control.

The UART interfaces require congatec device driver to function.

6.1.14 GPIOs
The conga-TS175 offers General Purpose Input/Output signals on the A–B connector. The GPIO signals are controlled by the congatec Board
controller.

6.1.15 Power Control

PWR_OK

Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module
can start its onboard power sequencing.

Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low
at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier
board power rails are up, to ensure a stable system.

A sample screenshot is shown below:

Copyright © 2017 congatec AG TSKLm15 32/72

Note

The module is kept in reset as long as the PWR_OK is driven by carrier board hardware.

Copyright © 2017 congatec AG TSKLm15 33/72

The conga-TS175 PWR_OK input circuitry is implemented as shown below:

+V12.0_S0

R1%47k5S02 R1%10kS02

R1%1k00S02
To Module Power Logic
PWR_OK

R1%20k0S02 R1%47k5S02
TBC847

The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also makes it possible to use the module on carrier
board designs that do not drive the PWR_OK signal. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it
is strongly recommended that the carrier board hardware drives the signal low until it is safe to let the module boot-up.

When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be
only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specification but this
can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when
the carrier board hardware is ready to boot.

The three typical usage scenarios for a carrier board design are:
• Connect PWR_OK to the “power good” signal of an ATX type power supply.
• Connect PWR_OK to the last voltage regulator in the chain on the carrier board.
• Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.
With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.
Copyright © 2017 congatec AG TSKLm15 34/72
 The conga-TS175 supports the controlling of ATX-style power supplies. If you do not use an ATX power supply, do not connect the conga-TS175
pins SUS_S3/PS_ON, 5V_SB, and PWRBTN#.

SUS_S3#/PS_ON#

The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an
ATX-style power supply. To accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and is
located on the carrier board.

PWRBTN#

When using ATX-style power supplies, PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary‑contact, active-low
debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up
to 3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this
signal from the system may vary as a result of modifications made in BIOS settings or by system software.

Standard 12V Power Supply Implementation Guidelines

12 volt input power is the sole operational power source for the conga-TS175. The remaining necessary voltages are generated internally on
the module using onboard voltage regulators.

A carrier board designer should be aware of the following important information when designing a power supply for a conga-TS175 application:
• We noticed that occasionally problems occur when using a 12 V power supply that produces non monotonic voltage when powered up. The
problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals when the supply voltage
exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a
malfunction. This problem is rare but has been observed in some mobile power supply applications. To ensure that this problem does not
occur, observe the power supply rise waveform with an oscilloscope to determine if the rise is indeed monotonic and does not have any
dips. Do this during the power supply qualification phase to ensure that the above mentioned problem does not occur in the application.
For more information, see the “Power Supply Design Guide for Desktop Platform Form Factors” document at www.intel.com.

Copyright © 2017 congatec AG TSKLm15 35/72

6.1.16 Power Management
ACPI

The conga-TS175 supports Advanced Configuration and Power Interface (ACPI) specification, revision 5.0. It also supports Suspend to RAM
(S3). For more information, see section 8.2 “ACPI Suspend Modes and Resume Events”.

DEEP Sx

The Deep Sx is a lower power state employed to minimize the power consumption while in S3/S4/S5. In the Deep Sx state, the system entry
condition determines if the system context is maintained or not. All power is shut off except for minimal logic which supports limited set of
wake events for Deep Sx. The Deep Sx on resumption, puts system back into the state it is entered from. In other words, if Deep Sx state was
entered from S3 state, then the resume path will place system back into S3.

Copyright © 2017 congatec AG TSKLm15 36/72

7 Additional Features
7.1 congatec Board Controller (cBC)
The conga-TS175 is equipped with Texas Instruments Tiva™ TM4E123GH6ZRBI7R microcontroller. This onboard microcontroller plays an
important role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features such as system
monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even
when the x86 processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all
congatec modules.

The board controller supports the following features:

7.1.1 Board Information

The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and firmware revisions,
and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

7.1.2 General Purpose Input/Output

The conga-TS175 offers general purpose inputs and outputs for custom system design. These GPIOs are controlled by the cBC.

7.1.3 Watchdog
The conga-TS175 is equipped with a multi-stage watchdog solution that is triggered by software. For more information about the Watchdog
feature, see the application note AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.

Note

The conga-TS175 module does not support the watchdog NMI mode.

7.1.4 I2C Bus

The conga-TS175 supports I2C bus. Thanks to the I2C host controller in the cBC, the I2C bus is multi-master capable and runs at fast mode.

Copyright © 2017 congatec AG TSKLm15 37/72

7.1.5 Power Loss Control
The cBC has full control of the power-up of the module and therefore can be used to specify the behavior of the system after an AC power loss
condition. Supported modes are “Always On”, “Remain Off” and “Last State”.

7.1.6 Fan Control

The conga-TS175 has additional signals and functions to further improve system management. One of these signals is an output signal called
FAN_PWMOUT that allows system fan control using a PWM (Pulse Width Modulation) output. Additionally, there is an input signal called
FAN_TACHOIN that provides the ability to monitor the system’s fan RPMs (revolutions per minute). This signal must receive two pulses per
revolution in order to produce an accurate reading. For this reason, a two pulse per revolution fan or similar hardware solution is recommended.

Note

1. A four wire fan must be used to generate the correct speed readout.

2. For the correct fan control (FAN_PWMOUT, FAN_TACHIN) implementation, see the COM Express Design Guide.

7.2 OEM BIOS Customization

The conga-TS175 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI firmware. The
congatec Embedded BIOS allows system designers to modify the BIOS. For more information about customizing the congatec Embedded
BIOS, refer to the congatec System Utility user’s guide CGUTLm1x.pdf on the congatec website at www.congatec.com or contact technical
support.

The customization features supported are described below:

7.2.1 OEM Default Settings

This feature allows system designers to create and store their own BIOS default configuration. Customized BIOS development by congatec for
OEM default settings is no longer necessary because customers can easily perform this configuration by themselves using the congatec system
utility CGUTIL. See congatec application note AN8_Create_OEM_Default_Map.pdf on the congatec website for details on how to add OEM
default settings to the congatec Embedded BIOS.

Copyright © 2017 congatec AG TSKLm15 38/72

7.2.2 OEM Boot Logo
This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo. Customized
BIOS development by congatec for OEM Boot Logo is no longer necessary because customers can easily perform this configuration by
themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_And_Add_Bootlogo.pdf on the congatec
website for details on how to add OEM boot logo to the congatec Embedded BIOS.

7.2.3 OEM POST Logo

This feature allows system designers to replace the congatec POST logo displayed in the upper left corner of the screen during BIOS POST
with their own BIOS POST logo. Use the congatec system utility CGUTIL 1.5.4 or later to replace/add the OEM POST logo.

7.2.4 OEM BIOS Code/Data

With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process. The congatec
Embedded BIOS first calls the OEM code before handing over control to the OS loader.

Except for custom specific code, this feature can also be used to support, Windows 7, Windows 8 OEM activation (OA3.0), verb tables for HDA
codecs, PCI/PCIe OpROMs, bootloaders, rare graphic modes and Super I/O controller initialization.

Note

The OEM BIOS code of the new UEFI based firmware is only called when the CSM (Compatibility Support Module) is enabled in the BIOS
setup menu. Contact congatec technical support for more information on how to add OEM code.

7.2.5 OEM DXE Driver

This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS. Contact congatec technical support for more
information on how to add an OEM DXE driver.

Copyright © 2017 congatec AG TSKLm15 39/72

7.3 congatec Battery Management Interface
To facilitate the development of battery powered mobile systems based on embedded modules, congatec AG defined an interface for the
exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to
the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable
operating system (for example, charge state of the battery, information about the battery, alarms/events for certain battery states and so on)
without the need for additional modifications to the system BIOS.

In addtion to the ACPI-Compliant Control Method Battery mentioned above, the latest versions of the conga-TS175 BIOS and board controller
firmware also support LTC1760 battery manager from Linear Technology and a battery only solution (no charger). All three battery solutions are
supported on the I2C bus and the SMBus. This gives the system designer more flexibility when choosing the appropriate battery sub-system.

For more information about this subject visit the congatec website and view the following documents:
• congatec Battery Management Interface Specification
• Battery System Design Guide
• conga-SBM3 User’s Guide

7.4 API Support (CGOS)

In order to benefit from the above mentioned non-industry standard feature set, congatec provides an API that allows application software
developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming
Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux.
The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules.
All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software
developers guide, available on the congatec website.

7.5 Security Features

The conga-TS175 can be equipped optionally with a “Trusted Platform Module“ (TPM 1.2/2.0). This TPM 1.2/2.0 includes coprocessors to
calculate efficient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive
applications like gaming and e-commerce will benefit also with improved authentication, integrity and confidence levels.

7.6 Suspend to Ram

The conga-TS175 supports Suspend to RAM feature.
Copyright © 2017 congatec AG TSKLm15 40/72
8 conga Tech Notes
The conga-TS175 has some technological features that require additional explanation. The following section will give the reader a better
understanding of some of these features.

8.1 Intel® Processor Features

8.1.1 Adaptive Thermal Monitor and Catastrophic Thermal Protection

Intel® Xeon, Core™ i7/i5/i3 and Celeron® processors have a thermal monitor feature that helps to control the processor temperature. The
integrated TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation
temperature that the Intel® Thermal Monitor uses to activate the TCC can be slightly modified via TCC Activation Offset in BIOS setup
submenu “CPU submenu”.

The Adaptive Thermal Monitor controls the processor temperature using two methods:
• Adjusting the processor’s operating frequency and core voltage (EIST transitions)
• Modulating (start/stop) the processor’s internal clocks at a duty cycle of 25% on and 75% off
When activated, the TCC causes both processor core and graphics core to reduce frequency and voltage adaptively. The Adaptive Thermal
Monitor will remain active as long as the package temperature remains at its specified limit. Therefore, the Adaptive Thermal Monitor will
continue to reduce the package frequency and voltage until the TCC is de-activated. Clock modulation is activated if frequency and voltage
adjustments are insufficient. Additional hardware, software drivers, or operating system support is not required.

Note

1. For THERMTRIP# to switch off the system automatically, use an ATX style power supply

2. The maximum operating temperature for Intel® Xeon, Core™ i7/i5/i3 and Celeron® processors is 100°C

3. To ensure that the TCC is active for only short periods of time, thus reducing the impact on processor performance to a minimum, it is
necessary to have a properly designed thermal solution. The Intel® Xeon, Core™ i7/i5/i3 and Celeron® processor’s respective datasheet
can provide you with more information about this subject.

Copyright © 2017 congatec AG TSKLm15 41/72

8.1.2 Intel® Turbo Boost Technology
Intel® Turbo Boost Technology allows processor cores to run faster than the base operating frequency if it’s operating below power, current, and
temperature specification limits. Intel® Turbo Boost Technology is activated when the Operating System (OS) requests the highest processor
performance state. The maximum frequency of Intel® Turbo Boost Technology is dependent on the number of active cores. The amount of time
the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment. Any of the following
can set the upper limit of Intel® Turbo Boost Technology on a given workload:
• Number of active cores
• Estimated current consumption
• Estimated power consumption
• Processor temperature
When the processor is operating below these limits and the user’s workload demands additional performance, the processor frequency will
dynamically increase by 100 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of
active cores is reached. For more information about Intel® Turbo Boost 2 Technology visit the Intel® website.

Note

Only conga-TS175 variants that feature the Xeon, Core™ i7 and i5 processors support Intel® Turbo Boost 2 Technology. Refer to the power
consumption tables in section 2.5 “Power Consumption” for information about the maximum turbo frequency available for each variant of
the conga-TS175.

8.1.3 Intel® Virtualization Technology

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. With this technology,
multiple, independent operating systems can run simultaneously on a single system. The technology components support virtualization of
platforms based on Intel architecture microprocessors and chipsets. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture
(Intel® VT-x) added hardware support in the processor to improve the virtualization performance and robustness.

RTS Real-Time Hypervisor supports Intel VT and is verified on all current congatec x86 hardware.

Note

congatec supports RTS Hypervisor.

Copyright © 2017 congatec AG TSKLm15 42/72

8.1.4 Thermal Management
ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the
operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands
put on the CPU by the application.

The conga-TS175 supports Critical Trip Point. This cooling policy ensures that the operating system shuts down properly if the temperature in
the thermal zone reaches a critical point, in order to prevent damage to the system as a result of high temperatures. Use the “critical trip point”
setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system.
The Automatic Critical Trip Point BIOS setting shuts down the system 5°C above the maximum specified temperature of the processor.

To cool the processor passively, use the Thermal Control Circuit (TCC ) Activation Offset setting in the CPU configuration setup sub-menu. The
TCC in the processor is activated at 100°C by default but can be lowered by the Activation Offset - for example, setting 10 activates TCC at
90°C. ACPI OS support is not required.

Note

Use the setup nodes in the BIOS setup program to establish the appropriate trip points.

8.1.5 Processor Performance Control

Intel® processors found on the conga-TS175 run at different voltage/frequency states (performance states), which is referred to as Enhanced
Intel® SpeedStep® technology (EIST). Operating systems that support performance control take advantage of microprocessors that use several
different performance states in order to efficiently operate the processor when it’s not being fully used. The operating system will determine
the necessary performance state that the processor should run at so that the optimal balance between performance and power consumption
can be achieved during runtime.

The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that the
power scheme setting you choose has the ability to support Enhanced Intel® SpeedStep® technology.

The 7th Generation Intel® Core™ processor family supports Intel Speed Shift, a new and energy efficient method for frequency control. This
feature is also referred to as Hardware-controlled Performance States (HWP). It is a hardware implementation of the ACPI defined Collaborative
Processor Performance Control (CPPC2) and is supported by newer operating systems (Win 8.1 or newer).

With this feature enabled, the processor autonomously selects performance states based on workload demand and thermal limits while also
considering information provided by the OS e.g., the performance limits and workload history.

Copyright © 2017 congatec AG TSKLm15 43/72

8.2 ACPI Suspend Modes and Resume Events
The conga-TS175 BIOS supports S3 (Suspend to RAM). The BIOS does not support S4 (Suspend to Disk) even though the following operating
systems support it (S4_OS = Hibernate):
• Windows 10, Linux.
Table 9 Wake Events

The table below lists the events that wake the system from S3.

Wake Event Conditions/Remarks

Power Button Wakes unconditionally from S3-S5.
Onboard LAN Event Device driver must be configured for Wake On LAN support.
SMBALERT# Wakes unconditionally from S3-S5.
PCI Express WAKE# Wakes unconditionally from S3-S5.
WAKE# Wakes unconditionally from S3.
PME# Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On
PME# to Enabled in the Power setup menu.
USB Mouse/Keyboard Event When Standby mode is set to S3, USB hardware must be powered by standby power source.
Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program).
In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the
computer out of standby’.
RTC Alarm Activate and configure Resume On RTC Alarm in the Power setup menu. Only available in S5.
Watchdog Power Button Event Wakes unconditionally from S3-S5.

8.3 DDR4 Memory

The conga-TS175 supports DDR4 memory modules up to 2400 MT/s. The DDR4 memory modules have lower voltage requirements with higher
data rate transfer speeds. They operate at a voltage of 1.2V. With this low voltage system memory interface on the processor, the conga-TS175
offers a system optimized for lowest possible power consumption. The reduction in power consumption due to lower voltage subsequently
reduces the heat generated.

Note

Use memory modules with same specifications, same type and model.

Copyright © 2017 congatec AG TSKLm15 44/72

9 Signal Descriptions and Pinout Tables
The following section describes the signals found on COM Express™ Type VI connectors used for congatec AG modules. The pinout of the
modules complies with COM Express Type 6 Rev. 2.1.

Table 3 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express™
module pull-up or pull-down resistor has been used. If the field entry area in this column for the signal is empty, then no pull-up or pull-down
resistor has been implemented by congatec.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When
“#” is not present, the signal is asserted when at a high voltage level.
Note

The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs
implemented by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to
the respective chip’s datasheet.

Table 10 Signal Tables Terminology Descriptions

Term Description
PU congatec implemented pull-up resistor
PD congatec implemented pull-down resistor
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
I/O 3.3VSB Input 3.3V tolerant active in standby state
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
OD Open drain output
P Power Input/Output
DDC Display Data Channel
PCIE In compliance with PCI Express Base Specification, Revision 2.0
PEG PCI Express Graphics
SATA In compliance with Serial ATA specification Revision 2.6 and 3.0.
REF Reference voltage output. May be sourced from a module power plane.
PDS Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal
module capabilities (pinout type) to the Carrier Board.

Copyright © 2017 congatec AG TSKLm15 45/72

9.1 Connector Signal Descriptions
Table 11 Connector A–B Pinout

Pin Row A Pin Row B Pin Row A Pin Row B

A1 GND (FIXED) B1 GND (FIXED) A56 PCIE_TX4- B56 PCIE_RX4-
A2 GBE0_MDI3- B2 GBE0_ACT# A57 GND B57 GPO2
A3 GBE0_MDI3+ B3 LPC_FRAME# A58 PCIE_TX3+ B58 PCIE_RX3+
A4 GBE0_LINK100# B4 LPC_AD0 A59 PCIE_TX3- B59 PCIE_RX3-
A5 GBE0_LINK1000# B5 LPC_AD1 A60 GND (FIXED) B60 GND (FIXED)
A6 GBE0_MDI2- B6 LPC_AD2 A61 PCIE_TX2+ B61 PCIE_RX2+
A7 GBE0_MDI2+ B7 LPC_AD3 A62 PCIE_TX2- B62 PCIE_RX2-
A8 GBE0_LINK# B8 LPC_DRQ0# A63 GPI1 B63 GPO3
A9 GBE0_MDI1- B9 LPC_DRQ1# A64 PCIE_TX1+ B64 PCIE_RX1+
A10 GBE0_MDI1+ B10 LPC_CLK A65 PCIE_TX1- B65 PCIE_RX1-
A11 GND (FIXED) B11 GND (FIXED) A66 GND B66 WAKE0#
A12 GBE0_MDI0- B12 PWRBTN# A67 GPI2 B67 WAKE1#
A13 GBE0_MDI0+ B13 SMB_CK A68 PCIE_TX0+ B68 PCIE_RX0+
A14 GBE0_CTREF (*) B14 SMB_DAT A69 PCIE_TX0- B69 PCIE_RX0-
A15 SUS_S3# B15 SMB_ALERT# A70 GND (FIXED) B70 GND (FIXED)
A16 SATA0_TX+ B16 SATA1_TX+ A71 eDP_TX2+/LVDS_A0+ B71 LVDS_B0+
A17 SATA0_TX- B17 SATA1_TX- A72 eDP_TX2-/LVDS_A0- B72 LVDS_B0-
A18 SUS_S4# B18 SUS_STAT# A73 eDP_TX1+/LVDS_A1+ B73 LVDS_B1+
A19 SATA0_RX+ B19 SATA1_RX+ A74 eDP_TX1-/LVDS_A1- B74 LVDS_B1-
A20 SATA0_RX- B20 SATA1_RX- A75 eDP_TX0+/LVDS_A2+ B75 LVDS_B2+
A21 GND (FIXED) B21 GND (FIXED) A76 eDP_TX0-/LVDS_A2- B76 LVDS_B2-
A22 SATA2_TX+ B22 SATA3_TX+ A77 eDP/LVDS_VDD_EN B77 LVDS_B3+
A23 SATA2_TX- B23 SATA3_TX- A78 LVDS_A3+ B78 LVDS_B3-
A24 SUS_S5# B24 PWR_OK A79 LVDS_A3- B79 eDP/LVDS_BKLT_EN
A25 SATA2_RX+ B25 SATA3_RX+ A80 GND (FIXED) B80 GND (FIXED)
A26 SATA2_RX- B26 SATA3_RX- A81 eDP_TX3+/LVDS_A_CK+ B81 LVDS_B_CK+
A27 BATLOW# B27 WDT A82 eDP_TX3-/LVDS_A_CK- B82 LVDS_B_CK-
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 (*) A83 eDP_AUX+/LVDS_I2C_CK B83 eDP/LVDS_BKLT_CTRL
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 A84 eDP_AUX-/LVDS_I2C_DAT B84 VCC_5V_SBY
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 A85 GPI3 B85 VCC_5V_SBY
A31 GND (FIXED) B31 GND (FIXED) A86 RSVD B86 VCC_5V_SBY
A32 AC/HDA_BITCLK B32 SPKR A87 eDP_HPD B87 VCC_5V_SBY
A33 AC/HDA_SDOUT B33 I2C_CK A88 PCIE0_CK_REF+ B88 BIOS_DIS1#
A34 BIOS_DIS0# B34 I2C_DAT A89 PCIE0_CK_REF- B89 VGA_RED
A35 THRMTRIP# B35 THRM# A90 GND (FIXED) B90 GND (FIXED)
A36 USB6- B36 USB7- A91 SPI_POWER B91 VGA_GRN

Copyright © 2017 congatec AG TSKLm15 46/72

Pin Row A Pin Row B Pin Row A Pin Row B
A37 USB6+ B37 USB7+ A92 SPI_MISO B92 VGA_BLU
A38 USB_6_7_OC# B38 USB_4_5_OC# A93 GPO0 B93 VGA_HSYNC
A39 USB4- B39 USB5- A94 SPI_CLK B94 VGA_VSYNC
A40 USB4+ B40 USB5+ A95 SPI_MOSI B95 VGA_I2C_CK
A41 GND (FIXED) B41 GND (FIXED) A96 TPM_PP B96 VGA_I2C_DAT
A42 USB2- B42 USB3- A97 TYPE10# (*) B97 SPI_CS#
A43 USB2+ B43 USB3+ A98 SER0_TX B98 RSVD
A44 USB_2_3_OC# B44 USB_0_1_OC# A99 SER0_RX B99 RSVD
A45 USB0- B45 USB1- A100 GND (FIXED) B100 GND (FIXED)
A46 USB0+ B46 USB1+ A101 SER1_TX B101 FAN_PWMOUT
A47 VCC_RTC B47 EXCD1_PERST# A102 SER1_RX B102 FAN_TACHIN
A48 EXCD0_PERST# B48 EXCD1_CPPE# A103 LID# B103 SLEEP#
A49 EXCD0_CPPE# B49 SYS_RESET# A104 VCC_12V B104 VCC_12V
A50 LPC_SERIRQ B50 CB_RESET# A105 VCC_12V B105 VCC_12V
A51 GND (FIXED) B51 GND (FIXED) A106 VCC_12V B106 VCC_12V
A52 PCIE_TX5+ B52 PCIE_RX5+ A107 VCC_12V B107 VCC_12V
A53 PCIE_TX5- B53 PCIE_RX5- A108 VCC_12V B108 VCC_12V
A54 GPI0 B54 GPO1 A109 VCC_12V B109 VCC_12V
A55 PCIE_TX4+ B55 PCIE_RX4+ A110 GND (FIXED) B110 GND (FIXED)

Note

The signals marked with asterisk symbol (*) are not connected on the conga-TS175.

Copyright © 2017 congatec AG TSKLm15 47/72

Table 12 Connector C–D Pinout

Pin Row C Pin Row D Pin Row C Pin Row D

C1 GND (FIXED) D1 GND (FIXED) C56 PEG_RX1- D56 PEG_TX1-
C2 GND D2 GND C57 TYPE1# D57 TYPE2#
C3 USB_SSRX0- D3 USB_SSTX0- C58 PEG_RX2+ D58 PEG_TX2+
C4 USB_SSRX0+ D4 USB_SSTX0+ C59 PEG_RX2- D59 PEG_TX2-
C5 GND D5 GND C60 GND (FIXED) D60 GND (FIXED)
C6 USB_SSRX1- D6 USB_SSTX1- C61 PEG_RX3+ D61 PEG_TX3+
C7 USB_SSRX1+ D7 USB_SSTX1+ C62 PEG_RX3- D62 PEG_TX3-
C8 GND D8 GND C63 RSVD D63 RSVD
C9 USB_SSRX2- D9 USB_SSTX2- C64 RSVD D64 RSVD
C10 USB_SSRX2+ D10 USB_SSTX2+ C65 PEG_RX4+ D65 PEG_TX4+
C11 GND (FIXED) D11 GND (FIXED) C66 PEG_RX4- D66 PEG_TX4-
C12 USB_SSRX3- D12 USB_SSTX3- C67 RSVD D67 GND
C13 USB_SSRX3+ D13 USB_SSTX3+ C68 PEG_RX5+ D68 PEG_TX5+
C14 GND D14 GND C69 PEG_RX5- D69 PEG_TX5-
C15 DDI1_PAIR6+ (*) D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED) D70 GND (FIXED)
C16 DDI1_PAIR6- (*) D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+ D71 PEG_TX6+
C17 RSVD D17 RSVD C72 PEG_RX6- D72 PEG_TX6-
C18 RSVD D18 RSVD C73 GND D73 GND
C19 PCIE_RX6+ D19 PCIE_TX6+ C74 PEG_RX7+ D74 PEG_TX7+
C20 PCIE_RX6- D20 PCIE_TX6- C75 PEG_RX7- D75 PEG_TX7-
C21 GND (FIXED) D21 GND (FIXED) C76 GND D76 GND
C22 PCIE_RX7+ D22 PCIE_TX7+ C77 RSVD D77 RSVD
C23 PCIE_RX7- D23 PCIE_TX7- C78 PEG_RX8+ D78 PEG_TX8+
C24 DDI1_HPD D24 RSVD C79 PEG_RX8- D79 PEG_TX8-
C25 DDI1_PAIR4+ (*) D25 RSVD C80 GND (FIXED) D80 GND (FIXED)
C26 DDI1_PAIR4- (*) D26 DDI1_PAIR0+ C81 PEG_RX9+ D81 PEG_TX9+
C27 RSVD D27 DDI1_PAIR0- C82 PEG_RX9- D82 PEG_TX9-
C28 RSVD D28 RSVD C83 RSVD D83 RSVD
C29 DDI1_PAIR5+ (*) D29 DDI1_PAIR1+ C84 GND D84 GND
C30 DDI1_PAIR5- (*) D30 DDI1_PAIR1- C85 PEG_RX10+ D85 PEG_TX10+
C31 GND (FIXED) D31 GND (FIXED) C86 PEG_RX10- D86 PEG_TX10-
C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+ C87 GND D87 GND
C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2- C88 PEG_RX11+ D88 PEG_TX11+
C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL C89 PEG_RX11- D89 PEG_TX11-
C35 RSVD D35 RSVD C90 GND (FIXED) D90 GND (FIXED)
C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ C91 PEG_RX12+ D91 PEG_TX12+
C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- C92 PEG_RX12- D92 PEG_TX12-
C38 DDI3_DDC_AUX_SEL D38 RSVD C93 GND D93 GND

Copyright © 2017 congatec AG TSKLm15 48/72

Pin Row C Pin Row D Pin Row C Pin Row D
C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ C94 PEG_RX13+ D94 PEG_TX13+
C40 DDI3_PAIR0- D40 DDI2_PAIR0- C95 PEG_RX13- D95 PEG_TX13-
C41 GND (FIXED) D41 GND (FIXED) C96 GND D96 GND
C42 DDI3_PAIR1+ D42 DDI2_PAIR1+ C97 RVSD D97 RSVD
C43 DDI3_PAIR1- D43 DDI2_PAIR1- C98 PEG_RX14+ D98 PEG_TX14+
C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14- D99 PEG_TX14-
C45 RSVD D45 RSVD C100 GND (FIXED) D100 GND (FIXED)
C46 DDI3_PAIR2+ D46 DDI2_PAIR2+ C101 PEG_RX15+ D101 PEG_TX15+
C47 DDI3_PAIR2- D47 DDI2_PAIR2- C102 PEG_RX15- D102 PEG_TX15-
C48 RSVD D48 RSVD C103 GND D103 GND
C49 DDI3_PAIR3+ D49 DDI2_PAIR3+ C104 VCC_12V D104 VCC_12V
C50 DDI3_PAIR3- D50 DDI2_PAIR3- C105 VCC_12V D105 VCC_12V
C51 GND (FIXED) D51 GND (FIXED) C106 VCC_12V D106 VCC_12V
C52 PEG_RX0+ D52 PEG_TX0+ C107 VCC_12V D107 VCC_12V
C53 PEG_RX0- D53 PEG_TX0- C108 VCC_12V D108 VCC_12V
C54 TYPE0# D54 PEG_LANE_RV# C109 VCC_12V D109 VCC_12V
C55 PEG_RX1+ D55 PEG_TX1+ C110 GND (FIXED) D110 GND (FIXED)

Note

The signals marked with an asterisk symbol (*) are not supported on the conga-TS175.

Copyright © 2017 congatec AG TSKLm15 49/72

Table 13 PCI Express Signal Descriptions (general purpose)

Signal Pin # Description I/O PU/PD Comment

PCIE_RX0+ B68 PCI Express channel 0, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX0- B69
PCIE_TX0+ A68 PCI Express channel 0, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX0- A69
PCIE_RX1+ B64 PCI Express channel 1, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX1- B65
PCIE_TX1+ A64 PCI Express channel 1, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX1- A65
PCIE_RX2+ B61 PCI Express channel 2, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX2- B62
PCIE_TX2+ A61 PCI Express channel 2, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX2- A62
PCIE_RX3+ B58 PCI Express channel 3, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX3- B59
PCIE_TX3+ A58 PCI Express channel 3, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX3- A59
PCIE_RX4+ B55 PCI Express channel 4, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX4- B56
PCIE_TX4+ A55 PCI Express channel 4, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX4- A56
PCIE_RX5+ B52 PCI Express channel 5, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX5- B53
PCIE_TX5+ A52 PCI Express channel 5, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX5- A53
PCIE_RX6+ C19 PCI Express channel 6, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX6- C20
PCIE_TX6+ D19 PCI Express channel 6, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX6- D20
PCIE_RX7+ C22 PCI Express channel 7, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_RX7- C23
PCIE_TX7+ D22 PCI Express channel 7, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0
PCIE_TX7- D23
PCIE_CLK_REF+ A88 PCI Express Reference Clock output for all PCI Express O PCIE A PCI Express Gen2/3 compliant clock buffer chip must be
PCIE_CLK_REF- A89 and PCI Express Graphics Lanes. used on the carrier board if the design involves more than one
PCI Express device.

Copyright © 2017 congatec AG TSKLm15 50/72

Table 14 PCI Express Signal Descriptions (x16 Graphics)

Signal Pin # Description I/O PU/PD Comment

PEG_RX0+ C52 PCI Express Graphics Receive Input differential pairs. I PCIE
PEG_RX0- C53 Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known
PEG_RX1+ C55 as PCIE_RX[16-31] + and -.
PEG_RX1- C56
PEG_RX2+ C58
PEG_RX2- C59
PEG_RX3+ C61
PEG_RX3- C62
PEG_RX4+ C65
PEG_RX4- C66
PEG_RX5+ C68
PEG_RX5- C69
PEG_RX6+ C71
PEG_RX6- C72
PEG_RX7+ C74
PEG_RX7- C75
PEG_RX8+ C78
PEG_RX8- C79
PEG_RX9+ C81
PEG_RX9- C82
PEG_RX10+ C85
PEG_RX10- C86
PEG_RX11+ C88
PEG_RX11- C89
PEG_RX12+ C91
PEG_RX12- C92
PEG_RX13+ C94
PEG_RX13- C95
PEG_RX14+ C98
PEG_RX14- C99
PEG_RX15+ C101
PEG_RX15- C102

Copyright © 2017 congatec AG TSKLm15 51/72

Signal Pin # Description I/O PU/PD Comment
PEG_TX0+ D52 PCI Express Graphics Transmit Output differential pairs. O PCIE
PEG_TX0- D53 Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31
PEG_TX1+ D55 known as PCIE_TX[16-31] + and -.
PEG_TX1- D56
PEG_TX2+ D58
PEG_TX2- D59
PEG_TX3+ D61
PEG_TX3- D62
PEG_TX4+ D65
PEG_TX4- D66
PEG_TX5+ D68
PEG_TX5- D69
PEG_TX6+ D71
PEG_TX6- D72
PEG_TX7+ D74
PEG_TX7- D75
PEG_TX8+ D78
PEG_TX8- D79
PEG_TX9+ D81
PEG_TX9- D82
PEG_TX10+ D85
PEG_TX10- D86
PEG_TX11+ D88
PEG_TX11- D89
PEG_TX12+ D91
PEG_TX12- D92
PEG_TX13+ D94
PEG_TX13- D95
PEG_TX14+ D98
PEG_TX14- D99
PEG_TX15+ D101
PEG_TX15- D102
PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane I PU 10k 3.3V PEG_LAN_RV# is a boot strap
order. signal (see note below)

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 9.2 “Boot Strap Signals”.

Copyright © 2017 congatec AG TSKLm15 52/72

Table 15 DDI Signal Description

Signal Pin # Description I/O PU/PD Comment

DDI1_PAIR0+ D26 Multiplexed with DP1_LANE0+ and TMDS1_DATA2+. O PCIE
DDI1_PAIR0- D27 Multiplexed with DP1_LANE0- and TMDS1_DATA2-.
DDI1_PAIR1+ D29 Multiplexed with DP1_LANE1+ and TMDS1_DATA1+. O PCIE
DDI1_PAIR1- D30 Multiplexed with DP1_LANE1- and TMDS1_DATA1-.
DDI1_PAIR2+ D32 Multiplexed with DP1_LANE2+ and TMDS1_DATA0+. O PCIE
DDI1_PAIR2- D33 Multiplexed with DP1_LANE2- and TMDS1_DATA0-.
DDI1_PAIR3+ D36 Multiplexed with DP1_LANE3+ and TMDS1_CLK+. O PCIE
DDI1_PAIR3- D37 Multiplexed with DP1_LANE3- and TMDS1_CLK-.
DDI1_PAIR4+ C25 Multiplexed with SDVO1_INT+. Not supported
DDI1_PAIR4- C26 Multiplexed with SDVO1_INT-.
DDI1_PAIR5+ C29 Multiplexed with SDVO1_TVCLKIN+. Not supported
DDI1_PAIR5- C30 Multiplexed with SDVO1_TVCLKIN-.
DDI1_PAIR6+ C15 Multiplexed with SDVO1_FLDSTALL+. Not supported
DDI1_PAIR6- C16 Multiplexed with SDVO1_FLDSTALL-.
DDI1_HPD C24 Multiplexed with DP1_HPD and HDMI1_HPD. I 3.3V PD 1M
DDI1_CTRLCLK_AUX+ D15 Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK. PD100k
DP AUX+ function if DDI1_DDC_AUX_SEL is no connect. I/O PCIE
HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high I/O OD 3.3V
DDI1_CTRLDATA_AUX- D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA. PU 100k 3.3V DDI1_CTRLDATA_AUX- is a boot
DP AUX- function if DDI1_DDC_AUX_SEL is no connect. I/O PCIE strap signal (see note below).
HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I/O OD 3.3V DDI enable strap already
populated.
DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-. I 3.3V PD 1M
This pin shall have a IM pull-down to logic ground on the module. If this
input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-
high, the AUX pair contains the CTRLCLK and CTRLDATA signals.
DDI2_PAIR0+ D39 Multiplexed with DP2_LANE0+ and TMDS2_DATA2+. O PCIE
DDI2_PAIR0- D40 Multiplexed with DP2_LANE0- and TMDS2_DATA2-.
DDI2_PAIR1+ D42 Multiplexed with DP2_LANE1+ and TMDS2_DATA1+. O PCIE
DDI2_PAIR1- D43 Multiplexed with DP2_LANE1- and TMDS2_DATA1-.
DDI2_PAIR2+ D46 Multiplexed with DP2_LANE2+ and TMDS2_DATA0+. O PCIE
DDI2_PAIR2- D47 Multiplexed with DP2_LANE2- and TMDS2_DATA0-.
DDI2_PAIR3+ D49 Multiplexed with DP2_LANE3+ and TMDS2_CLK+. O PCIE
DDI2_PAIR3- D50 Multiplexed with DP2_LANE3- and TMDS2_CLK-.
DDI2_HPD D44 Multiplexed with DP2_HPD and HDMI2_HPD. I 3.3V PD 1M
DDI2_CTRLCLK_AUX+ C32 Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK. PD 100k
DP AUX+ function if DDI2_DDC_AUX_SEL is no connect. I/O PCIE
HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high I/O OD 3.3V

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Signal Pin # Description I/O PU/PD Comment
DDI2_CTRLDATA_AUX- C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA. PU 100k 3.3V DDI2_CTRLDATA_AUX- is a boot
DP AUX- function if DDI2_DDC_AUX_SEL is no connect. I/O PCIE strap signal (see note below).
HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high. I/O OD 3.3V DDI enable strap already
populated.
DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-. I 3.3V
This pin shall have a IM pull-down to logic ground on the module. If this
input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-
high, the AUX pair contains the CTRLCLK and CTRLDATA signals
DDI3_PAIR0+ C39 Multiplexed with DP3_LANE0+ and TMDS3_DATA2+. O PCIE
DDI3_PAIR0- C40 Multiplexed with DP3_LANE0- and TMDS3_DATA2-.
DDI3_PAIR1+ C42 Multiplexed with DP3_LANE1+ and TMDS3_DATA1+. O PCIE
DDI3_PAIR1- C43 Multiplexed with DP3_LANE1- and TMDS3_DATA1-.
DDI3_PAIR2+ C46 Multiplexed with DP3_LANE2+ and TMDS3_DATA0+. O PCIE
DDI3_PAIR2- C47 Multiplexed with DP3_LANE2- and TMDS3_DATA0-.
DDI3_PAIR3+ C49 Multiplexed with DP3_LANE3+ and TMDS3_CLK+. O PCIE
DDI3_PAIR3- C50 Multiplexed with DP3_LANE3- and TMDS3_CLK-.
DDI3_HPD C44 Multiplexed with DP3_HPD and HDMI3_HPD. I 3.3V PD 1M
DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK. PD 100k
DP AUX+ function if DDI3_DDC_AUX_SEL is no connect. I/O PCIE
HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I/O OD 3.3V
DDI3_CTRLDATA_AUX- C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA. PU 100k 3.3V
DP AUX- function if DDI3_DDC_AUX_SEL is no connect. I/O PCIE
HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high. I/O OD 3.3V
DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-. I 3.3V
This pin shall have a IM pull-down to logic ground on the module. If this
input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-
high, the AUX pair contains the CTRLCLK and CTRLDATA signals

Note

1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For
more information refer to section 9.2 “Boot Strap Signals”.

2. The Digital Display Interface (DDI) signals are multiplexed with HDMI and DisplayPort (DP). The signals for these interfaces are routed to
the DDI interface of the COM Express connector. Refer to the HDMI and DisplayPort signal description tables in this section for information
about the signals routed to the DDI interface of the COM Express connector.

Copyright © 2017 congatec AG TSKLm15 54/72

Table 16 HDMI Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

TMDS1_CLK + D36 HDMI/DVI TMDS Clock output differential pair. O PCIE
TMDS1_CLK - D37 Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
TMDS1_DATA0+ D32 HDMI/DVI TMDS differential pair. O PCIE
TMDS1_DATA0- D33 Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
TMDS1_DATA1+ D29 HDMI/DVI TMDS differential pair. O PCIE
TMDS1_DATA1- D30 Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-..
TMDS1_DATA2+ D26 HDMI/DVI TMDS differential pair. O PCIE
TMDS1_DATA2- D27 Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
HDMI1_HPD C24 HDMI/DVI Hot-plug detect. I PCIE PD 1M
Multiplexed with DDI1_HPD.
HDMI1_CTRLCLK D15 HDMI/DVI I2C Control Clock I/O OD 3.3V PD 100k
Multiplexed with DDI1_CTRLCLK_AUX+
HDMI1_CTRLDATA D16 HDMI/DVI I2C Control Data I/O OD 3.3V PU 100k HDMI1_CTRLDATA is a boot strap signal (see note below).
Multiplexed with DDI1_CTRLDATA_AUX- 3.3V HDMI enable strap already populated
TMDS2_CLK + D49 HDMI/DVI TMDS Clock output differential pair.. O PCIE
TMDS2_CLK - D50 Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-.
TMDS2_DATA0+ D46 HDMI/DVI TMDS differential pair. O PCIE
TMDS2_DATA0- D47 Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-.
TMDS2_DATA1+ D42 HDMI/DVI TMDS differential pair. O PCIE
TMDS2_DATA1- D43 Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-.
TMDS2_DATA2+ D39 HDMI/DVI TMDS differential pair. O PCIE
TMDS2_DATA2- D40 Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-..
HDMI2_HPD D44 HDMI/DVI Hot-plug detect. I PCIE PD 1M
Multiplexed with DDI2_HPD
HDMI2_CTRLCLK C32 HDMI/DVI I2C Control Clock I/O OD 3.3V PD 100k
Multiplexed with DDI2_CTRLCLK_AUX+
HDM12_CTRLDATA C33 HDMI/DVI I2C Control Data I/O OD 3.3V PU 100k HDMI2_CTRLDATA is a boot strap signal (see note below).
Multiplexed with DDI2_CTRLDATA_AUX- 3.3V HDMI enable strap is already populated.
TMDS3_CLK + C49 HDMI/DVI TMDS Clock output differential pair.. O PCIE
TMDS3_CLK - C50 Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.
TMDS3_DATA0+ C46 HDMI/DVI TMDS differential pair. O PCIE
TMDS3_DATA0- C47 Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.
TMDS3_DATA1+ C42 HDMI/DVI TMDS differential pair. O PCIE
TMDS3_DATA1- C43 Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-..
TMDS3_DATA2+ C39 HDMI/DVI TMDS differential pair. O PCIE
TMDS3_DATA2- C40 Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.
HDMI3_HPD C44 HDMI/DVI Hot-plug detect. I PCIE PD 1M
Multiplexed with DDI3_HPD.
HDMI3_CTRLCLK C36 HDMI/DVI I2C Control Clock I/O OD 3.3V PD 100K
Multiplexed with DDI3_CTRLCLK_AUX+

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Signal Pin # Description I/O PU/PD Comment
HDMI3_CTRLDATA C37 HDMI/DVI I2C Control Data I/O OD 3.3V PU 100k HDMI3_CTRLDATA is a boot strap signal (see note below).
Multiplexed with DDI3_CTRLDATA_AUX- 3.3V HDMI enable strap is already populated.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 9.2 “Boot Strap Signals”.

Table 17 DisplayPort (DP) Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

DP1_LANE3+ D36 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP1_LANE3- D37 Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
DP1_LANE2+ D32 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP1_LANE2- D33 Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
DP1_LANE1+ D29 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP1_LANE1- D30 Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.
DP1_LANE0+ D26 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP1_LANE0- D27 Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
DP1_HPD C24 Detection of Hot Plug / Unplug and notification of the link layer. I 3.3V PD 1M
Multiplexed with DDI1_HPD.
DP1_AUX+ D15 Half-duplex bi-directional AUX channel for services such as link configuration or I/O PCIE PD 100k
maintenance and EDID access.
DP1_AUX- D16 Half-duplex bi-directional AUX channel for services such as link configuration or I/O PCIE PU 100k DP1_AUX- is a boot strap signal (see note
maintenance and EDID access. 3.3V below).
DP enable strap is already populated.
DP2_LANE3+ D49 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP2_LANE3- D50 Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-
DP2_LANE2+ D46 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP2_LANE2- D47 Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-
DP2_LANE1+ D42 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP2_LANE1- D43 Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-
DP2_LANE0+ D39 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP2_LANE0- D40 Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0-
DP2_HPD D44 Detection of Hot Plug / Unplug and notification of the link layer. I 3.3V PD 1M
Multiplexed with DDI2_HPD.
DP2_AUX+ C32 Half-duplex bi-directional AUX channel for services such as link configuration or I/O PCIE PD 100k
maintenance and EDID access.
DP2_AUX- C33 Half-duplex bi-directional AUX channel for services such as link configuration or I/O PCIE PU 100k DP2_AUX- is a boot strap signal (see note
maintenance and EDID access. 3.3V below). DP enable strap already populated.

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Signal Pin # Description I/O PU/PD Comment
DP3_LANE3+ C49 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP3_LANE3- C50 Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.
DP3_LANE2+ C46 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP3_LANE2- C47 Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.
DP3_LANE1+ C42 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP3_LANE1- C43 Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-.
DP3_LANE0+ C39 Uni-directional main link for the transport of isochronous streams and secondary data. O PCIE
DP3_LANE0- C40 Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.
DP3_HPD C44 Detection of Hot Plug / Unplug and notification of the link layer. I 3.3V PD 1M
Multiplexed with DDI3_HPD.
DP3_AUX+ C36 Half-duplex bi-directional AUX channel for services such as link configuration or I/O PCIE PD 100k
maintenance and EDID access.
DP3_AUX- C37 Half-duplex bi-directional AUX channel for services such as link configuration or I/O PCIE PU 100k DP3_AUX- is a boot strap signal (see note
maintenance and EDID access. 3.3V below). DP enable strap already populated

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 9.2 “Boot Strap Signals”.

Table 18 Embedded DisplayPort Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

eDP_TX3+ A81 eDP differential pairs AC coupled off module
eDP_TX3- A82
eDP_TX2+ A71
eDP_TX2- A72
eDP_TX1+ A73
eDP_TX1- A74
eDP_TX0+ A75
eDP_TX0- A76
eDP_VDD_EN A77 eDP power enable O 3.3V PD 10k
eDP_BKLT_EN B79 eDP backlight enable O 3.3V PD 10k
eDP_BKLT_CTRL B83 eDP backlight brightness control O 3.3V
eDP_AUX+ A83 eDP AUX+ AC coupled off module
eDP_AUX- A84 eDP AUX- AC coupled off module
eDP_HPD A87 Detection of Hot Plug / Unplug and notification of the link layer I 3.3V

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Table 19 CRT Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VGA_RED B89 Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load O Analog PD 150R Optional
VGA_GRN B91 Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent O Analog PD 150R Optional
load
VGA_BLU B92 Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load O Analog PD 150R Optional
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V Optional
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V Optional
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify VGA monitor capabilities) I/O OD 5V PU 1k2 3.3V Optional
VGA_I2C_DAT B96 DDC data line I/O OD 5V PU 1k2 3.3V Optional

Table 20 LVDS Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

LVDS_A0+ A71 LVDS Channel A differential pairs O LVDS
LVDS_A0- A72
LVDS_A1+ A73
LVDS_A1- A74
LVDS_A2+ A75
LVDS_A2- A76
LVDS_A3+ A78
LVDS_A3- A79
LVDS_A_CK+ A81 LVDS Channel A differential clock O LVDS
LVDS_A_CK- A82
LVDS_B0+ B71 LVDS Channel B differential pairs O LVDS
LVDS_B0- B72
LVDS_B1+ B73
LVDS_B1- B74
LVDS_B2+ B75
LVDS_B2- B76
LVDS_B3+ B77
LVDS_B3- B78
LVDS_B_CK+ B81 LVDS Channel B differential clock O LVDS
LVDS_B_CK- B82
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 10k
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V PD 10k
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V for LVDS support (default)
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V for LVDS support (default)

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Table 21 Serial ATA Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SATA0_RX+ A19 Serial ATA channel 0, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0
SATA0_RX- A20
SATA0_TX+ A16 Serial ATA channel 0, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0
SATA0_TX- A17
SATA1_RX+ B19 Serial ATA channel 1, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0
SATA1_RX- B20
SATA1_TX+ B16 Serial ATA channel 1, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0
SATA1_TX- B17
SATA2_RX+ A25 Serial ATA channel 2, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0
SATA2_RX- A26
SATA2_TX+ A22 Serial ATA channel 2, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0
SATA2_TX- A23
SATA3_RX+ B25 Serial ATA channel 3, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0
SATA3_RX- B26
SATA3_TX+ B22 Serial ATA channel 3, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0
SATA3_TX- B23
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. I/O 3.3v

Table 22 USB 2.0 Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

USB0+ A46 USB Port 0, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB0- A45 USB Port 0, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB1+ B46 USB Port 1, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB1- B45 USB Port 1, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB2+ A43 USB Port 2, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB2- A42 USB Port 2, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB3+ B43 USB Port 3, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB3- B42 USB Port 3, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB4+ A40 USB Port 4, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB4- A39 USB Port 4, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB5+ B40 USB Port 5, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB5- B39 USB Port 5, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB6+ A37 USB Port 6, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB6- A36 USB Port 6, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB7+ B37 USB Port 7, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1
USB7- B36 USB Port 7, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

Copyright © 2017 congatec AG TSKLm15 59/72

Signal Pin # Description I/O PU/PD Comment
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be I 3.3VSB PU 10k Do not pull this line high on the carrier board.
present on the module. An open drain driver from a USB current monitor 3.3VSB
on the carrier board may drive this line low.
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be I 3.3VSB PU 10k Do not pull this line high on the carrier board.
present on the module. An open drain driver from a USB current monitor 3.3VSB
on the carrier board may drive this line low. .
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be I 3.3VSB PU 10k Do not pull this line high on the carrier board.
present on the module. An open drain driver from a USB current monitor 3.3VSB
on the carrier board may drive this line low.
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be I 3.3VSB PU 10k Do not pull this line high on the carrier board.
present on the module. An open drain driver from a USB current monitor 3.3VSB
on the carrier board may drive this line low.

Table 23 USB 3.0 Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

USB_SSRX0+ C4 Additional receive signal differential pairs for the Superspeed USB data path I
USB_SSRX0- C3 I
USB_SSTX0+ D4 Additional transmit signal differential pairs for the Superspeed USB data path O
USB_SSTX0- D3 O
USB_SSRX1+ C7 Additional receive signal differential pairs for the Superspeed USB data path I
USB_SSRX1- C6 I
USB_SSTX1+ D7 Additional transmit signal differential pairs for the Superspeed USB data path O
USB_SSTX1- D6 O
USB_SSRX2+ C10 Additional receive signal differential pairs for the Superspeed USB data path I
USB_SSRX2- C9 I
USB_SSTX2+ D10 Additional transmit signal differential pairs for the Superspeed USB data path O
USB_SSTX2- D9 O
USB_SSRX3+ C13 Additional receive signal differential pairs for the Superspeed USB data path I
USB_SSRX3- C12 I
USB_SSTX3+ D13 Additional transmit signal differential pairs for the Superspeed USB data path O
USB_SSTX3- D12 O

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Table 24 Gigabit Ethernet Signal Descriptions

Gigabit Pin # Description I/O PU/PD Comment

Ethernet
GBE0_MDI0+ A13 Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate I/O Twisted pair
GBE0_MDI0- A12 in 1000, 100, and 10Mb/sec modes. Some pairs are unused in some modes according to the following: Analog signals for
GBE0_MDI1+ A10 1000 100 10 external
GBE0_MDI1- A9 transformer.
GBE0_MDI2+ A7 MDI[0]+/- B1_DA+/- TX+/- TX+/-
GBE0_MDI2- A6 MDI[1]+/- B1_DB+/- RX+/- RX+/-
GBE0_MDI3+ A3 MDI[2]+/- B1_DC+/-
GBE0_MDI3- A2 MDI[3]+/- B1_DD+/-
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mb/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mb/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is Not
determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The connected
reference voltage output shall be current limited on the module. In the case in which the reference is
shorted to ground, the current shall be limited to 250mA or less.

Note

1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation
of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#.

2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS175 module.

Table 25 Intel® High Definition Audio Link Signals Descriptions

Signal Pin # Description I/O PU/PD Comment

AC/HDA_RST# A30 Intel® High Definition Audio Reset: This signal is the master hardware reset to O 3.3VSB AC’97 codecs are not supported.
external codec(s).
AC/HDA_SYNC A29 Intel® High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync O 3.3VSB AC’97 codecs are not supported.
to the codec(s). It is also used to encode the stream number.
AC/HDA_BITCLK A32 Intel® High Definition Audio Bit Clock Output: This signal is a 24.000MHz serial O 3.3VSB AC’97 codecs are not supported.
data clock generated by the Intel® High Definition Audio controller.
AC/HDA_SDOUT A33 Intel® High Definition Audio Serial Data Out: This signal is the serial TDM data O 3.3VSB AC’97 codecs are not supported.
output to the codec(s). This serial output is double-pumped for a bit rate of 48 AC/HDA_SDOUT is a boot strap signal
Mb/s for Intel® High Definition Audio. (see note below)

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Signal Pin # Description I/O PU/PD Comment
AC/HDA_SDIN[1:0] B29-B30 Intel® High Definition Audio Serial Data In [0]: These signals are serial TDM I 3.3VSB Pin B28 (HDA_SDIN2) is not connected.
data inputs from the three codecs. The serial input is single-pumped for a bit
rate of 24 Mb/s for Intel® High Definition Audio.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 9.2 “Boot Strap Signals”.

Table 26 ExpressCard Support Pins Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

EXCD0_CPPE# A49 ExpressCard capable card request. I 3.3V PU 10k 3.3VSB
EXCD1_CPPE# B48
EXCD0_PERST# A48 ExpressCard Reset O 3.3V PU 10k 3.3V
EXCD1_PERST# B47

Table 27 LPC Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ[0:1]# B8-B9 LPC serial DMA request I 3.3V PU 10k 3.3V
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 10k 3.3V
LPC_CLK B10 LPC clock output - 24 MHz nominal O 3.3V

Table 28 SPI BIOS Flash Interface Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Carrier shall pull to SPI_POWER when
external SPI is provided but not used.
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB

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Signal Pin # Description I/O PU/PD Comment
SPI_POWER A91 Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to power + 3.3VSB
SPI BIOS flash on the carrier only.
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K Carrier shall be left as no-connect.
3.3VSB
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K Carrier shall be left as no-connect
3.3VSB

Table 29 Miscellaneous Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

I2C_CK B33 General purpose I²C port clock output/input I/O 3.3V PU 2K2 3.3VSB
I2C_DAT B34 General purpose I²C port data I/O line I/O 3.3V PU 2K2 3.3VSB
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPEAKER is a boot strap signal (see
note below)
WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V PD 10K
FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control O OD
the fan’s RPM. 3.3V
FAN_TACHIN B102 Fan tachometer input. I OD PU 10K 3.3V Requires a fan with a two pulse output.
TPM_PP A96 Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip has I 3.3V Trusted Platform Module chip is
an internal pull‑down. This signal is used to indicate Physical Presence to the TPM. optional.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 9.2 “Boot Strap Signals”.

Table 30 General Purpose I/O Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

GPO0 A93 General purpose output pins. O 3.3V
Shared with SD_CLK. Output from COM Express, input to SD
GPO1 B54 General purpose output pins. O 3.3V
Shared with SD_CMD. Output from COM Express, input to SD
GPO2 B57 General purpose output pins. O 3.3V
Shared with SD_WP. Output from COM Express, input to SD
GPO3 B63 General purpose output pins. O 3.3V
Shared with SD_CD. Output from COM Express, input to SD

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Signal Pin # Description I/O PU/PD Comment
GPI0 A54 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
Shared with SD_DATA0. Bidirectional signal
GPI1 A63 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
Shared with SD_DATA1. Bidirectional signal
GPI2 A67 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
Shared with SD_DATA2. Bidirectional signal
GPI3 A85 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
Shared with SD_DATA3. Bidirectional signal.

Note

The conga-TS175 provides GPIO signals on the COM Express connector by default.

Table 31 Power and System Management Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB
Note: For proper detection, assert a pulse width of at least 16 ms.
SYS_RESET# B49 Reset button input. Active low input. Edge triggered. I 3.3VSB PU 10k 3.3VSB
System will not be held in hardware reset while this input is kept low.
Note: For proper detection, assert a pulse width of at least 16 ms.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module chipset and may result O 3.3V PD 100k
from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the
minimum specification, a watchdog timeout, or may be initiated by the module software.
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is good. I 3.3V Set by resistor divider
to accept 3.3V.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on O 3.3VSB
the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a
typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB Not supported
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB
WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 1k 3.3VSB
WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or I 3.3VSB PU 10k 3.3VSB
mouse activity.
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that the system I 3.3VSB PU 8k2 3.3VSB
battery is low, or may be used to signal some other external power-management event.
THRM# B35 Input from off-module temp sensor indicating an over-temp situation. I 3.3V PU 10k 3.3V
THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V PU 10k 3.3V
SMB_CK B13 System Management Bus bidirectional clock line. I/O 3.3VSB PU 2k2 3.3VSB

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Signal Pin # Description I/O PU/PD Comment
SMB_DAT# B14 System Management Bus bidirectional data line. I/O OD PU 2k2 3.3VSB
3.3VSB
SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System I 3.3VSB PU 2k2 3.3VSB
Management Interrupt) or to wake the system.
LID# A103 Lid button. Used by the ACPI operating system for a LID switch. I OD 3.3V PU 10k 3.3VSB
Note: For proper detection, assert a pulse width of at least 16 ms.
SLEEP# B103 Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake I OD 3.3V PU 10k 3.3VSB
it up again.
Note: For proper detection, assert a pulse width of at least 16 ms.

Table 32 General Purpose Serial Interface Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SER0_TX A98 General purpose serial port transmitter O 3.3V
SER1_TX A101 General purpose serial port transmitter O 3.3V
SER0_RX A99 General purpose serial port receiver I 3.3V PU 47k 3.3V
SER1_RX A102 General purpose serial port receiver I 3.3V PU 47k 3.3V

Table 33 Module Type Definition Signal Description

Signal Pin # Description I/O Comment

TYPE0# C54 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on PDS TYPE[0:2]# signals are
TYPE1# C57 the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X). available on all modules
TYPE2# D57 TYPE2# TYPE1# TYPE0# following the Type 2-6
Pinout standard.
X X X Pinout Type 1
NC NC NC Pinout Type 2 The conga-TS175 is based
NC NC GND Pinout Type 3 (no IDE) on the COM Express Type
NC GND NC Pinout Type 4 (no PCI) 6 pinout therefore the pins
NC GND GND Pinout Type 5 (no IDE, no PCI) 0 and 1 are not connected
GND NC NC Pinout Type 6 (no IDE, no PCI) and pin 2 is connected to
The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off GND.
(e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The
Carrier Board logic may also implement a fault indicator such as an LED.

Copyright © 2017 congatec AG TSKLm15 65/72

Signal Pin # Description I/O Comment
TYPE10# A97 Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev. PDS Not connected to indicate
1.0/2.0 module is installed. “Pinout R2.0”.
TYPE10#
NC Pinout R2.0
PD Pinout Type 10 pull down to ground with 4.7k resistor
12V Pinout R1.0
This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin
is defined as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0
module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor.

Table 34 Power and GND Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VCC_12V A104-A109 Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) P
B104-B109 shall be used.
C104-C109
D104-D109
VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY P
pins on the connector(s) shall be used. Only used for standby and suspend functions.
May be left unconnected if these functions are not used in the system design.
VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P
GND A1, A11, A21, A31, A41, A51, Ground - DC power and signal and AC signal return path. P
A57, A60, A66, A70, A80, All available GND connector pins shall be used and tied to Carrier Board GND plane.
A90, A100, A110, B1, B11,
B21, B31, B41, B51, B60, B70,
B80, B90, B100, B110
C1, C2, C5, C8, C11, C14,
C21, C31, C41, C51, C60,
C70,C73, C76, C80, C84, C87,
C90, C93, C96, C100, C103,
C110, D1, D2, D5, D8, D11,
D14, D21, D31, D41, D51,
D60, D67, D70, D73, D76,
D80, D84, D87, D90, D93,
D96, D100, D103, D110

Copyright © 2017 congatec AG TSKLm15 66/72

9.2 Boot Strap Signals
Table 35 Boot Strap Signal Descriptions

Signal Pin # Description of Boot Strap Signal I/O PU/PD Comment

AC/HDA_SDOUT A33 High Definition Audio Serial Data Out: This signal is the serial TDM data O 3.3VSB PU 1k AC/HDA_SDOUT is a boot strap signal
output to the codec(s). This serial output is double-pumped for a bit rate of 3.3VSB (see caution statement below)
48 Mb/s for High Definition Audio.
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPKR is a boot strap signal (see caution
statement below)
PEG_LAN_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carier board 13.3V PU 10k PEG_LAN_RV# is a boot strap signal
to reverse lane order. 3.3V (see note below)
DDI1_CTRLDATA_AUX- D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA. PU100k DDI1_CTRLDATA_AUX- is a boot strap
DP1_AUX- DP AUX- function if DDI1_DDC_AUX_SEL is no connect. I/O PCIE 3.3V signal (see note below).
HDMI_CTRLDATA HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high. I/O OD 3.3V
DDI2_CTRLDATA_AUX- C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA. PU100k DDI2_CTRLDATA_AUX- is a boot strap
DP2_AUX- DP AUX- function if DDI2_DDC_AUX_SEL is no connect. I/O PCIE 3.3V signal (see note below).
HDM2_CTRLDATA HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high. I/O OD 3.3V
DDI3_CTRLDATA_AUX- C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA. I/O PCIE PU 100k DDI3_CTRLDATA_AUX- is a boot strap
DP3_AUX- DP AUX- function if DDI3_DDC_AUX_SEL is no connect. I/O OD 3.3V 3.3V signal (see note below)
HDM2_CTRLDATA HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.

Caution

1. The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are
inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented
resistors that are located on the module.

2. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals listed in the above table.
External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or cause irreparable
damage to the module.

Copyright © 2017 congatec AG TSKLm15 67/72

10 System Resources
10.1 I/O Address Assignment
The I/O address assignment of the conga-TS175 module is functionally identical with a standard PC/AT.

Note

The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume
I/O resources in that area.

10.1.1 LPC Bus

On the conga-TS175 the PCIExpress Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded
to the PCI Bus not the LPC Bus. Only specified I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS the following I/O
address ranges are sent to the LPC Bus:
2Eh – 2Fh
4Eh – 4Fh
60h, 64h
A00h – A1Fh
E00h - EFFh (always used internally)
Parts of these ranges are not available if a Super I/O is used on the carrier board. If a Super I/O is not implemented on the carrier board
then these ranges are available for customer use. If you require additional LPC Bus resources other than those mentioned above, or more
information about this subject, contact congatec technical support for assistance.

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10.2 PCI Configuration Space Map
Table 36 PCI Configuration Space Map

Bus Number (hex) Device Number (hex) Function Number (hex) Description
00h 00h 00h HOST and DRAM Controller
00h 01h 00h PCI Express Graphic Root Port 0
00h 01h 01h PCI Express Graphic Root Port 1
00h 01h 02h PCI Express Graphic Root Port 2
00h 02h 00h Integrated Graphics Device
00h 08h 00h Gaussian Mixture Model Device
00h 14h 00h USB 3.0 xHCI Controller
00h 14h 02h Thermal Subsystem
00h ( Note1) 16h 00h Management Engine (ME) Interface 1
00h ( Note1) 16h 01h Intel ME Interface 2
00h ( Note1) 16h 02h ME IDE Redirection (IDE-R) Interface
00h ( Note1) 16h 03h ME Keyboard and Text (KT) Redirection
00h ( Note1) 16h 04h Intel ME Interface 3
00h 17h 00h SATA Controller
00h 1Ch 00h Not connected (PCI Express Root Port)
00h (Note2) 1Ch 04h PCI Express Root Port 0
00h (Note2) 1Ch 05h PCI Express Root Port 1
00h (Note2) 1Ch 06h PCI Express Root Port 2
00h (Note2) 1Ch 07h PCI Express Root Port 3
00h (Note2) 1Dh 00h PCI Express Root Port 4
00h (Note2) 1Dh 01h PCI Express Root Port 5
00h (Note2) 1Dh 02h PCI Express Root Port 6
00h (Note2) 1Dh 03h PCI Express Root Port 7
00h 1Fh 00h PCI to LPC Bridge
00h 1Fh 02h Power Management Controller
00h 1Fh 03h Intel® High Definition Audio (Intel® HD Audio)
00h 1Fh 04h SMBus Controller
00h 1Fh 06h GbE Controller
01h (Note3) 00h 00h PEG Port 0
02h (Note3) 00h 00h PEG Port 1

Copyright © 2017 congatec AG TSKLm15 69/72

 03h (Note3) 00h 00h PEG Port 2
04h (Note3) 00h 00h PCI Express Port 0
05h (Note3) 00h 00h PCI Express Port 1
06h (Note3) 00h 00h PCI Express Port 2
07h (Note3) 00h 00h PCI Express Port 3
08h (Note3) 00h 00h PCI Express Port 4
09h (Note3) 00h 00h PCI Express Port 5
0Ah (Note3) 00h 00h PCI Express Port 6
0Bh (Note3) 00h 00h PCI Express Port 7

Note

1. In the standard configuration, the Intel Management Engine (ME) related devices are partly present or not present at all.

2. The PCI Express Ports are visible only if a device is attached to the PCI Express Slot on the carrier board.

3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus
numbers will change based on actual hardware configuration.

4. Internal PCI devices not connected to the conga-TS175 are not listed.

10.3 I2C
There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

10.4 SM Bus
System Management (SM) bus signals are connected to the Intel® chipset. The SM bus is not intended to be used by off-board non-system
management devices. For more information about this subject, contact congatec technical support.

Copyright © 2017 congatec AG TSKLm15 70/72

11 BIOS Setup Description
The BIOS setup description of the conga-TS175 can be viewed without having access to the module. However, access to the restricted area of
the congatec website is required in order to download the necessary tool (CgMlfViewer) and Menu Layout File (MLF).

The MLF contains the BIOS setup description of a particular BIOS revision. The MLF can be viewed with the CgMlfViewer tool. This tool offers
a search function to quickly check for supported BIOS features. It also shows where each feature can be found in the BIOS setup menu.

For more information, read the application note “AN42 - BIOS Setup Description” available at www.congatec.com.

Note

If you do not have access to the restricted area of the congatec website, contact your local congatec sales representative.

11.1 Navigating the BIOS Setup Menu

The BIOS setup menu shows the features and options supported in the congatec BIOS. To access and navigate the BIOS setup menu, press
the <DEL> or <F2> key during POST.

The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options
and the possible impacts when changing the selected option in the left frame.

11.2 BIOS Versions

The BIOS displays the BIOS project name and the revision code during POST, and on the main setup screen. The initial production BIOS for
conga-TS175 is identified as BHKLR1xx or BQKLR1xx, where:
• R is the identifier for a BIOS ROM file,
• 1 is the feature number and
• xx is the major and minor revision number.
The BHKL binary size is 16 MB and the BQKL binary size is 8 MB.

Copyright © 2017 congatec AG TSKLm15 71/72

11.3 Updating the BIOS
BIOS updates are recommeded to correct platform issues or enhance the feature set of the module. The conga-TS175 features a congatec/AMI
AptioEFI firmware on an onboard flash ROM chip. You can update the firmware with the congatec System Utility. The utility has five versions—
UEFI shell, DOS based command line1, Win32 command line, Win32 GUI, and Linux version.

For more information about “Updating the BIOS” refer to the user’s guide for the congatec System Utility “CGUTLm1x.pdf” on the congatec
website at www.congatec.com.

Note
1.
Deprecated

Caution

The DOS command line tool is not officially supported by congatec and therefore not recommended for critical tasks such as firmware
updates. We recommend to use only the UEFI shell for critical updates.

11.4 Recovering from External Flash

The following congatec documents describe how to recover a congatec module from external flash. You can find these documents on the
congatec website:
• AN1_BIOS_Update.pdf
• AN5_BIOS_Update_And_Write_Protection.pdf
• AN7_External_BIOS_Update.pdf

11.5 Supported Flash Devices

The conga-TS175 supports the following flash devices:
• Winbond W25Q128JVSIQ (16 MB)
• Winbond W25Q64JVSSIQ (8 MB)
The flash devices listed above can be used on the carrier board to support external BIOS. For more information about external BIOS support,
refer to the Application Note “AN7_External_BIOS_Update.pdf” on the congatec website at http://www.congatec.com.

Copyright © 2017 congatec AG TSKLm15 72/72