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SN 74 LVC 07 A

The SN74LVC07A is a hex buffer and driver designed for operation between 1.65 V to 5.5 V, featuring open-drain outputs that can accept voltages up to 5.5 V. It has a maximum propagation delay of 2.6 ns at 5 V and supports various applications including AV receivers, Blu-ray players, and solid-state drives. The document includes detailed specifications, pin configurations, and thermal information relevant to the device.

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0% found this document useful (0 votes)
21 views38 pages

SN 74 LVC 07 A

The SN74LVC07A is a hex buffer and driver designed for operation between 1.65 V to 5.5 V, featuring open-drain outputs that can accept voltages up to 5.5 V. It has a maximum propagation delay of 2.6 ns at 5 V and supports various applications including AV receivers, Blu-ray players, and solid-state drives. The document includes detailed specifications, pin configurations, and thermal information relevant to the device.

Uploaded by

Iulian Oprescu
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Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016

SN74LVC07A Hex Buffer and Driver With Open-Drain Outputs


1 Features 3 Description

1 Operates From 1.65 V to 5 V The SN74LVC07A device is a hex buffer and driver
that is designed for 1.65-V to 5.5-V VCC operation.
• Inputs and Open-Drain Outputs Accept Voltages
Up to 5.5 V Device Information(1)
• Max tpd of 2.6 ns at 5 V PART NUMBER PACKAGE BODY SIZE (NOM)
• Latch-Up Performance Exceeds 250 mA SN74LVC07AD SOIC (14) 8.65 mm × 3.91 mm
Per JESD 17 SN74LVC07ADB SSOP (14) 6.20 mm × 5.30 mm
• Ioff Supports Live Insertion, Partial-Power-Down SN74LVC07ADGV TVSOP (14) 3.60 mm × 4.40 mm
Mode, and Back-Drive Protection SN74LVC07APW TSSOP (14) 5.00 mm × 4.40 mm
SN74LVC07ANS SO (14) 10.30 mm × 5.30 mm
2 Applications SN74LVC07ARGY VQFN (14) 3.50 mm × 3.50 mm
• AV Receiver (1) For all available packages, see the orderable addendum at
• Audio Dock: Portable the end of the data sheet.
• Blu-ray Player and Home Theater
• MP3 Player or Recorder
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD, Digital, and High-Definition (HDTV)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse
Simplified Schematic

A Y

Copyright © 2016 Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 12
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 12
3 Description ............................................................. 1 8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4 9 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
6 Specifications......................................................... 5
9.2 Typical Application ................................................. 13
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5 10 Power Supply Recommendations ..................... 14
6.3 Recommended Operating Conditions ...................... 5 11 Layout................................................................... 14
6.4 Thermal Information .................................................. 6 11.1 Layout Guidelines ................................................. 14
6.5 Electrical Characteristics—DC Limit Changes.......... 6 11.2 Layout Example .................................................... 15
6.6 Switching Characteristics .......................................... 6 12 Device and Documentation Support ................. 16
6.7 Operating Characteristics.......................................... 7 12.1 Documentation Support ........................................ 16
6.8 Typical Characteristics .............................................. 7 12.2 Receiving Notification of Documentation Updates 16
7 Parameter Measurement Information .................. 8 12.3 Community Resources.......................................... 16
7.1 VCC = 1.8 V ± 0.15 V................................................. 8 12.4 Trademarks ........................................................... 16
7.2 VCC = 2.5 V ± 0.2 V................................................... 9 12.5 Electrostatic Discharge Caution ............................ 16
7.3 VCC = 2.7 and 3.3 V ± 0.3 V ................................... 10 12.6 Glossary ................................................................ 16
7.4 VCC = 5 V ± 0.5 V.................................................... 11 13 Mechanical, Packaging, and Orderable
8 Detailed Description ............................................ 12 Information ........................................................... 16

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision V (May 2015) to Revision W Page

• Changed Pin Functions table ................................................................................................................................................ 4


• Added Junction temperature to the Absolute Maximum Ratings table .................................................................................. 5
• Reformatted the Electrical Characteristics and the Switching Characteristics tables ........................................................... 6
• Changed Typical Application Diagram ................................................................................................................................ 13
• Added Receiving Notification of Documentation Updates section ...................................................................................... 16

Changes from Revision U (June 2014) to Revision V Page

• Changed Handling Ratings table to ESD Ratings table ........................................................................................................ 5


• Added industry standard terms to package designators in the Thermal Information table .................................................... 6
• Changed from "High" to "High-Z" in the Function Table ..................................................................................................... 12

Changes from Revision T (February 2011) to Revision U Page

• Updated document to new TI data sheet format .................................................................................................................... 1


• Removed Ordering Information table ..................................................................................................................................... 1
• Added Applications ................................................................................................................................................................. 1
• Added Ioff Features bullet........................................................................................................................................................ 1
• Added Device Information table ............................................................................................................................................. 1
• Added Handling Ratings table. ............................................................................................................................................... 5
• Changed MAX operating free-air temperature from 85°C to 125°C....................................................................................... 5
• Updated Thermal Information table. ...................................................................................................................................... 6
• Added –40°C TO +125°C temperature range to Electrical Characteristics table................................................................... 6
• Added Switching Characteristics table for –40°C TO 125°C temperature range................................................................... 6
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• Added Typical Characteristics ................................................................................................................................................ 7

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5 Pin Configuration and Functions

D, DB, DGV, NS, PW Package


14-Pin SOIC, SSOP, TVSOP, SO, TSSOP
Top View

RGY Package
14-Pin VQFN
Top View

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1A I Input 1
2 1Y O Output 1
3 2A I Input 2
4 2Y O Output 2
5 3A I Input 3
6 3Y O Output 3
7 GND — Ground pin
8 4Y O Output 4
9 4A I Input 4
10 5Y O Output 5
11 5A I Input 5
12 6Y O Output 6
13 6A I Input 6
14 VCC — Power pin

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Output voltage –0.5 6.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tj Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings


VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions


over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 2.7 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 2.7 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 5.5 V
VCC = 1.65 V 4
VCC = 2.3 V 12
IOL Low-level output current VCC = 2.7 V 12 mA
VCC = 3 V 24
VCC = 4.5 V 24
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

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6.4 Thermal Information


SN74LVC07A
D DB DGV NS PW RGY
THERMAL METRIC (1) UNIT
(SOIC) (SSOP) (TVSOP) (SO) (TSSOP) (VQFN)
14 PINS
RθJA Junction-to-ambient thermal resistance 177.4 135.1 157.7 120.3 160.3 80.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 75.4 86.7 78.3 76.3 84.4 97.0 °C/W
RθJB Junction-to-board thermal resistance 70.6 82.4 90.8 79.0 102.1 56.7 °C/W
ψJT Junction-to-top characterization parameter 34.7 43.7 21.0 36.2 24.3 16.7 °C/W
ψJB Junction-to-board characterization parameter 70.4 81.9 90.1 78.7 101.4 56.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a 35.8 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics—DC Limit Changes


TA = –40°C to +125°C, unless otherwise noted
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOL = 100 µA 1.65 V to 5.5 V 0.2
IOL = 4 mA 1.65 V 0.45
VOL 2.3 V 0.7 V
IOL = 12 mA
2.7 V 0.4
IOL = 24 mA 3V 0.55
II VI = 5.5 V or GND 3.6 V ±5 µA
Ioff VI or VO = 5.5 V 0V ±10 µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 µA
One input at VCC – 0.6 V,
ΔICC 2.7 V to 3.6 V 500 µA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 5.0 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Switching Characteristics


over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6)
FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
VCC = 1.8 V ± 0.15 V 1 5.6
VCC = 2.5 V ± 0.2 V 1 3.4
–40°C to 85°C VCC = 2.7 V 1 3.3
VCC = 3.3 V ± 0.3 V 1 3.6
VCC = 5 V ± 0.5 V 1 2.6
tpd A Y ns
VCC = 1.8 V ± 0.15 V 1 6.1
VCC = 2.5 V ± 0.2 V 1 3.9
–40°C to 125°C VCC = 2.7 V 1 3.8
VCC = 3.3 V ± 0.3 V 1 4.1
VCC = 5 V ± 0.5 V 1 3.1

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6.7 Operating Characteristics


TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Power dissipation capacitance
Cpd f = 10 MHz 1.8 2 2.5 3.78 pF
per buffer and driver

6.8 Typical Characteristics

2.5 2.5

2 2

1.5 1.5
TPD - ns

TPD - ns
1 1

0.5 0.5

TPD in ns TPD in ns
0 0
0 1 2 3 4 5 6 -100 -50 0 50 100 150
VCC - V D001
Temperature (qC) D002

Figure 1. TPD vs VCC Figure 2. TPD vs Temperature

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7 Parameter Measurement Information


7.1 VCC = 1.8 V ± 0.15 V
2 × VCC
1 kΩ S1 Open
From Output
TEST S1
Under Test GND
tPZL (see Note F) 2 × VCC
CL = 30 pF
1 kΩ tPLZ (see Note G) 2 × VCC
(see Note A)
tPHZ/tPZH 2 × VCC

LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ


Output VCC
VCC
Waveform 2 VCC − 0.15 V
Output VCC/2 VCC/2 VCC/2
S1 at 2 × VCC
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS


PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.


B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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7.2 VCC = 2.5 V ± 0.2 V


2 × VCC
500 Ω S1 Open
From Output
TEST S1
Under Test GND
tPZL (see Note F) 2 × VCC
CL = 30 pF
500 Ω tPLZ (see Note G) 2 × VCC
(see Note A)
tPHZ/tPZH 2 × VCC

LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ


Output VCC
VCC
Waveform 2 VCC − 0.15 V
Output VCC/2 VCC/2 VCC/2
S1 at 2 × VCC
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS


PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.


B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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7.3 VCC = 2.7 and 3.3 V ± 0.3 V


6V
500 Ω S1 Open
From Output TEST S1
Under Test GND
tPZL (see Note F) 6V
CL = 50 pF tPLZ (see Note G) 6V
500 Ω
(see Note A)
tPHZ/tPZH 6V

LOAD CIRCUIT
tw
2.7 V
2.7 V Input 1.5 V 1.5 V
Timing
1.5 V 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
2.7 V Output
Data 2.7 V
1.5 V 1.5 V Control
Input
0V (low-level 1.5 V 1.5 V
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output
2.7 V 3V
Waveform 1
Input 1.5 V 1.5 V S1 at 6 V 1.5 V VOL + 0.3 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ


Output 3V
3V
Waveform 2 2.7 V
Output 1.5 V 1.5 V 1.5 V
S1 at 6 V
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS


PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.


B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at 1.5 V.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 5. Load Circuit and Voltage Waveforms

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7.4 VCC = 5 V ± 0.5 V


2 x VCC
500 Ω
2 x VCC
2 x VCC
500 Ω 2 x VCC

Output
Waveform 1
S1 at 2 x VCC
(see Note B)

Output
Waveform 2
S1 at 2 x VCC 0.3 V
(see Note B)

NOTES: A. CL includes probe and jig capacitance.


B. Waveform 1 is for an output with internal connections such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal connections such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 6. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as translators in a mixed-system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

A Y

Copyright © 2016 Texas Instruments Incorporated

8.3 Feature Description


• Wide operating voltage range
– Operates from 1.65 V to 5.5 V
• Allows up or down voltage translation
– Inputs and outputs accept voltages to 5.5 V
• Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V

8.4 Device Functional Modes


Table 1 lists the functional modes of the SN74LVC07A.

Table 1. Function Table


INPUT OUTPUT
A Y
H Hi-Z
L L

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information


The SN74LVC07A device is a high-drive, open-drain CMOS device that can be used for a multitude of buffer-
type functions. It can produce 24 mA of drive current at 3.3 V. Therefore, this device is ideal for driving multiple
inputs and for high-speed applications up to 100 MHz. The inputs and outputs are 5.5-V tolerant allowing the
device to translate up to 5.5 V or down to VCC.

9.2 Typical Application

Buffer Function Basic LED Driver


VPU VPU

Wired OR
µC or Logic µC or Logic µC or Logic
LVC07A LVC07A

µC or Logic
LVC07A

Copyright © 2016 Texas Instruments Incorporated

Figure 7. Typical Application Diagram

9.2.1 Design Requirements


This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads;
therefore, routing and load conditions must be considered to prevent ringing.

9.2.2 Detailed Design Procedure


1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions

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Typical Application (continued)


– Load currents must not exceed 25 mA per output and 50 mA total for the part.
– Outputs must not be pulled above 5.5 V.

9.2.3 Application Curve


1600
ICC 1.8 V
1400 ICC 2.5 V
ICC 3.3 V
1200 ICC 5 V

1000
TPD - ns

800

600

400

200

0
0 20 40 60 80
VCC - V D003

Figure 8. ICC vs Frequency

10 Power Supply Recommendations


The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µf is recommended; if there are multiple VCC pins, then 0.01 µf or 0.022 µf is recommended for each power
pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µf and a 1 µf
are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for
best results.

11 Layout

11.1 Layout Guidelines


When using multiple bit logic devices inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the
part is a transceiver.

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11.2 Layout Example


Vcc
Input

Unused Input Output Output


Unused Input

Input

Figure 9. Layout Diagram

Copyright © 1997–2016, Texas Instruments Incorporated Submit Documentation Feedback 15


Product Folder Links: SN74LVC07A
SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016 www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation


For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004.
• Semiconductor and IC Package Thermal Metrics, SPRA953.

12.2 Receiving Notification of Documentation Updates


To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

16 Submit Documentation Feedback Copyright © 1997–2016, Texas Instruments Incorporated

Product Folder Links: SN74LVC07A


PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC07AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07ADE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07ADGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07ADRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07ADRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07ADT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07ANSR ACTIVE SOP NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples

SN74LVC07APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWE4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWRG3 ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07APWTG4 ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples

SN74LVC07ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC07A Samples

SN74LVC07ARGYRG4 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC07A Samples

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC07A :

• Automotive : SN74LVC07A-Q1
• Enhanced Product : SN74LVC07A-EP

NOTE: Qualified Version Definitions:

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC07ADBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LVC07ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LVC07ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74LVC07ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADT SOIC D 14 250 180.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ANSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC07APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWRG3 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC07ADBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LVC07ADGVR TVSOP DGV 14 2000 356.0 356.0 35.0
SN74LVC07ADR SOIC D 14 2500 353.0 353.0 32.0
SN74LVC07ADR SOIC D 14 2500 356.0 356.0 35.0
SN74LVC07ADRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74LVC07ADRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74LVC07ADRG4 SOIC D 14 2500 340.5 336.1 32.0
SN74LVC07ADT SOIC D 14 250 210.0 185.0 35.0
SN74LVC07ANSR SOP NS 14 2000 356.0 356.0 35.0
SN74LVC07APWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC07APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC07APWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC07APWT TSSOP PW 14 250 356.0 356.0 35.0
SN74LVC07ARGYR VQFN RGY 14 3000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74LVC07AD D SOIC 14 50 506.6 8 3940 4.32
SN74LVC07ADE4 D SOIC 14 50 506.6 8 3940 4.32
SN74LVC07APW PW TSSOP 14 90 530 10.2 3600 3.5
SN74LVC07APWE4 PW TSSOP 14 90 530 10.2 3600 3.5
SN74LVC07APWG4 PW TSSOP 14 90 530 10.2 3600 3.5

Pack Materials-Page 3
MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE


24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN


0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.


6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM


(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM


(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM


(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
RGY 14 VQFN - 1 mm max height
3.5 x 3.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4231541/A

www.ti.com
PACKAGE OUTLINE
RGY0014A SCALE 3.200
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.65 B
A
3.35

PIN 1 INDEX AREA


3.65
3.35

1 MAX C

SEATING PLANE
0.05
0.00 0.08

2.05 0.1

2X 1.5 (0.2) TYP


7 8

6
9

2X
2

8X 0.5

2
13
0.30
14X
0.18
1 14 0.1 C A B
PIN 1 ID 0.05
(OPTIONAL) 0.5
14X
0.3

4219040/A 09/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
RGY0014A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 2.05)
2X (1.5)

SYMM
1 14

14X (0.6)

2 13

14X (0.24)

SYMM
(3.3)

(0.775)

8X (0.5)
9
6

( 0.2) VIA
TYP

7 8
(0.775)
(R0.05) TYP
(3.3)

LAND PATTERN EXAMPLE


SCALE:20X

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

METAL SOLDER MASK


OPENING

SOLDER MASK METAL UNDER


OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS


4219040/A 09/2015

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
EXAMPLE STENCIL DESIGN
RGY0014A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (1.5)
4X ( 0.92)
1 14

14X (0.6)

2 13

14X (0.24)

SYMM (3.3)

(0.56)

8X (0.5)
9
6

METAL
TYP

7 SYMM 8

(R0.05) TYP
(0.56)

(3.3)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X

4219040/A 09/2015

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM


1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE


SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK


METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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