SN 74 LVC 07 A
SN 74 LVC 07 A
SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016
A Y
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC07A
SCAS595W – OCTOBER 1997 – REVISED OCTOBER 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 12
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 12
3 Description ............................................................. 1 8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4 9 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
6 Specifications......................................................... 5
9.2 Typical Application ................................................. 13
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5 10 Power Supply Recommendations ..................... 14
6.3 Recommended Operating Conditions ...................... 5 11 Layout................................................................... 14
6.4 Thermal Information .................................................. 6 11.1 Layout Guidelines ................................................. 14
6.5 Electrical Characteristics—DC Limit Changes.......... 6 11.2 Layout Example .................................................... 15
6.6 Switching Characteristics .......................................... 6 12 Device and Documentation Support ................. 16
6.7 Operating Characteristics.......................................... 7 12.1 Documentation Support ........................................ 16
6.8 Typical Characteristics .............................................. 7 12.2 Receiving Notification of Documentation Updates 16
7 Parameter Measurement Information .................. 8 12.3 Community Resources.......................................... 16
7.1 VCC = 1.8 V ± 0.15 V................................................. 8 12.4 Trademarks ........................................................... 16
7.2 VCC = 2.5 V ± 0.2 V................................................... 9 12.5 Electrostatic Discharge Caution ............................ 16
7.3 VCC = 2.7 and 3.3 V ± 0.3 V ................................... 10 12.6 Glossary ................................................................ 16
7.4 VCC = 5 V ± 0.5 V.................................................... 11 13 Mechanical, Packaging, and Orderable
8 Detailed Description ............................................ 12 Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
RGY Package
14-Pin VQFN
Top View
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1A I Input 1
2 1Y O Output 1
3 2A I Input 2
4 2Y O Output 2
5 3A I Input 3
6 3Y O Output 3
7 GND — Ground pin
8 4Y O Output 4
9 4A I Input 4
10 5Y O Output 5
11 5A I Input 5
12 6Y O Output 6
13 6A I Input 6
14 VCC — Power pin
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Output voltage –0.5 6.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tj Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
2.5 2.5
2 2
1.5 1.5
TPD - ns
TPD - ns
1 1
0.5 0.5
TPD in ns TPD in ns
0 0
0 1 2 3 4 5 6 -100 -50 0 50 100 150
VCC - V D001
Temperature (qC) D002
LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL
LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL
LOAD CIRCUIT
tw
2.7 V
2.7 V Input 1.5 V 1.5 V
Timing
1.5 V 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
2.7 V Output
Data 2.7 V
1.5 V 1.5 V Control
Input
0V (low-level 1.5 V 1.5 V
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output
2.7 V 3V
Waveform 1
Input 1.5 V 1.5 V S1 at 6 V 1.5 V VOL + 0.3 V
0V (see Note B) VOL
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
Output
Waveform 2
S1 at 2 x VCC 0.3 V
(see Note B)
8 Detailed Description
8.1 Overview
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as translators in a mixed-system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
A Y
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Wired OR
µC or Logic µC or Logic µC or Logic
LVC07A LVC07A
µC or Logic
LVC07A
1000
TPD - ns
800
600
400
200
0
0 20 40 60 80
VCC - V D003
11 Layout
Input
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 2-Dec-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN74LVC07AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07ADE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07ADGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07ADRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07ADRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07ADT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07ANSR ACTIVE SOP NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC07A Samples
SN74LVC07APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWE4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWRG3 ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07APWTG4 ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC07A Samples
SN74LVC07ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC07A Samples
SN74LVC07ARGYRG4 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC07A Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 2-Dec-2024
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive : SN74LVC07A-Q1
• Enhanced Product : SN74LVC07A-EP
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 2-Dec-2024
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Dec-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Dec-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Dec-2024
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
MECHANICAL DATA
0,23
0,40 0,07 M
0,13
24 13
0,16 NOM
4,50 6,60
4,30 6,20
Gage Plane
0,25
0°–8°
0,75
1 12
0,50
A
Seating Plane
0,15
1,20 MAX 0,08
0,05
PINS **
14 16 20 24 38 48 56
DIM
4073251/E 08/00
C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1
2X
6.5
3.9
5.9
NOTE 3
7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4
0.25
0.09
SEE DETAIL A
2 MAX
0.25
GAGE PLANE
DETAIL A
A 15
TYPICAL
4220762/A 05/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
1 (R0.05) TYP
14X (0.45) 14
SYMM
12X (0.65)
7 8
(7)
4220762/A 05/2024
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
12X (0.65)
7 8
(7)
4220762/A 05/2024
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1
2X
5.1 3.9
4.9
NOTE 3
4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220202/B 12/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
12X (0.65)
7 8
(5.8)
4220202/B 12/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
12X (0.65)
7 8
(5.8)
4220202/B 12/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGY 14 VQFN - 1 mm max height
3.5 x 3.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4231541/A
www.ti.com
PACKAGE OUTLINE
RGY0014A SCALE 3.200
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.65 B
A
3.35
1 MAX C
SEATING PLANE
0.05
0.00 0.08
2.05 0.1
6
9
2X
2
8X 0.5
2
13
0.30
14X
0.18
1 14 0.1 C A B
PIN 1 ID 0.05
(OPTIONAL) 0.5
14X
0.3
4219040/A 09/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0014A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.05)
2X (1.5)
SYMM
1 14
14X (0.6)
2 13
14X (0.24)
SYMM
(3.3)
(0.775)
8X (0.5)
9
6
( 0.2) VIA
TYP
7 8
(0.775)
(R0.05) TYP
(3.3)
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0014A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.5)
4X ( 0.92)
1 14
14X (0.6)
2 13
14X (0.24)
SYMM (3.3)
(0.56)
8X (0.5)
9
6
METAL
TYP
7 SYMM 8
(R0.05) TYP
(0.56)
(3.3)
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219040/A 09/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
C
6.2
TYP SEATING PLANE
5.8
A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1
8.75 2X
8.55 7.62
NOTE 3
7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4
0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE
0.25
0 -8 1.27 0.10
0.40
DETAIL A
TYPICAL
4220718/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (0.6)
12X (1.27)
SYMM
7 8
(R0.05)
TYP
(5.4)
4220718/A 09/2016
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
1
14
14X (0.6)
12X (1.27)
SYMM
7 8
(5.4)
4220718/A 09/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated