Chapter 6 Design for Testability and BuiltBuilt-In Self-Test Self-

Jin-Fu Li Advanced Reliable Systems (ARES) Lab Lab. Department of Electrical Engineering National Central University Jungli, Taiwan

Outline
Basics Design-for-Testability (DFT) Techniques
Ad Hoc DFT Structural Methods
Scan Partial Scan BIST Boundary Scan Syndrome-Testable Design C-Testable Design g

Built-In Self-Test (BIST) Techniques

Signature Analysis Pseudorandom Pattern Generator (PRPG) Built-In Logic Block Observer (BILBO)

Summary S
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Definitions
Definition
A fault is testable if there exists a well-specified procedure to expose it which is implementable with it, a reasonable cost using current technologies. A circuit is testable with respect to a fault set when each and every fault in this set is testable h h d f lt i thi t i t t bl

Definition
Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective

Electronic systems contain three types of components: (a) digital logic, (b) memory blocks, blocks and (c) analog or mixed signal circuits mixed-signal In this chapter, we discuss DFT techniques for digital logic
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

Ad Hoc DFT Guidelines

Partition large circuits into smaller subcircuits to reduce test generation cost ( g (using MUXed g and/or scan chains)
T1 T2

Mode

T1 T2
0 0 1 0 1 0

C1
1 0

C2

Normal Test C1 Test C2

Advanced Reliable Systems (ARES) Lab.

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Ad Hoc DFT Guidelines

Insert test points to enhance controllability & observability y
Test points: control points & observation points
OP C1 C2 CP1 CP2 C2
0 1

CP3

CP4

Advanced Reliable Systems (ARES) Lab.

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Ad Hoc DFT Guidelines

Design circuits to be easily initializable Provide logic to break global feedback paths Partition large counter into smaller ones Avoid the use of redundant logic Keep analog and digital circuits physically apart Avoid the use of asynchronous logic Consider tester requirements ( d (pin l limitation, etc) Etc

Advanced Reliable Systems (ARES) Lab.

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Scan Design Approaches

They are effective for circuit partitioning They provide controllability and observability of internal state variables for testing They turn the sequential test problem into a combinational one Four major approaches
Shift-register modification Scan path Level-sensitive scan design (LSSD) Random access

Circuit is designed using pre-specified design rules. rules

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Scan Design Approaches

Consider a representation of sequential circuits
(primary inputs) (primary outputs)

X
(present state) y

Combinational Logic

Z Y (next state)

clk

state

To make elements of state vector controllable and observable, we add observable

A A A A TEST mode pin (T) SCAN IN pin (SI) SCAN-IN SCAN-OUT pin (SO) MUX (switch) in front of each FF (M)
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Advanced Reliable Systems (ARES) Lab.

Adding Scan Structure

PI Combinational logic SFF SFF SFF PO SCAN-OUT

T SCAN-IN
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Scan Test Generation & Design Rules

Test pattern generation
Use combinational ATPG to obtain tests for all testable faults in the combinational logic Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test

Scan design rules

Use only clocked D-type of flip-flops for all state variables At l least one PI pin must be available for t t more t i tb il bl f test; pins, if available, can be used All clocks must be controlled from PIs Clocks must not feed data inputs of flip-flops

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Correcting a Rule Violation

All clocks must be controlled from PIs
Comb. logic D1 D2 CK FF Q Comb. Comb logic

Comb. logic D1 D2 CK
Jin-Fu Li, EE, NCU

Q FF Comb. logic
11

Advanced Reliable Systems (ARES) Lab.

Correcting a Rule Violation

Adding a scan FF and a mux allows a feedback loop to be opened for testing
1 1 1 0

A A B T
0

FF CK Test

Testing derived clocks requires the use of a mux to bypass the division stages yp g
CK Freq. Divider q FF CK Freq. Divider FF

FF
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Test

FF
12

Correcting a Rule Violation

The AND gates keep the bus drivers from being activated by the normal logic during testing

FF

FF

FF

FF

Test

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Scan Test Procedure

Step 1: Switch to the shift-register mode and check the SR operation by shifting in an p y g alternating sequence of 1s and 0s, e.g., 00110 (functional test) Step 2: Initialize the SR---load the first pattern Step 3: Return to the normal mode and apply the test pattern Step 4: Switch to the SR mode and shift out the final state while setting the starting state g g for the next test. Go to Step 3

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Combining Test Vectors

PI SCAN IN SCAN-IN T Presen t state

I1

I2 Combinational logic

O1

O2

PO

SCAN-OUT SCAN OUT Next t t state

S1

S2

N1

N2

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Combining Test Vectors

PI SCAN-IN T I1 I2

Dont care or random bits

S1

S2

0000000 1 0000000 1 0000000

PO

O1

O2

SCAN-OUT

N1

N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors nsff = number of scan fli fl b f flip-flops
Jin-Fu Li, EE, NCU Advanced Reliable Systems (ARES) Lab. 16

Testing Scan Register

Scan register must be tested prior to application of scan test sequences A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC 0) produces 00 01, (TC=0) 00, 01 ff 11 and 10 transitions in all flip-flops and observes the result at SCAN-OUT output p Total scan test length: (ncomb+2)nsff+ncomb+4 clock periods 2)n n 4 Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks Multiple scan registers reduce test length
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

Multiple Scan Registers

Scan flip-flops can be distributed among any number of shift registers, each having a separate SCAN-IN and SCAN-OUT pin Test sequence length is determined by the longest scan shift register Just one test control (TC) pin is essential
T SCAN-IN1 SCAN IN1 SCAN-IN1 Scan Registe 1 Register Scan Register 2 SCAN-OUT1 SCAN OUT1 SCAN-OUT2

SCAN-INK

Scan Register 3

SCAN-OUTK

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Hierarchical Scan
Scan flip-flops are chained within subnetworks before chaining subnetworks Advantages:
Automatic scan insertion in netlist Circuit hierarchy preserved helps in debugging and design changes

Disadvantage: Non-optimum chip layout

Scanin SFF1 SFF4 Scanout Scanin SFF2 SFF3 SFF1 SFF3 Scanout SFF4 SFF2

Hierarchical netlist
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

Flat layout Fl t l t
19

Optimum Scan Layout

X IO pad FlipFli flop cell Y SFF cell SCANIN X

Y Y

SCAN OUT

Routing channels Interconnects Active areas: XY and XY

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

Automated Scan Design

Rule violations i l ti
Behavior, RTL, and logic Design and verification g Scan design rule audits

Gate-level netlist Scan hardware insertion

Combinational ATPG Combinational vectors Scan sequence S and test program generation Scan chain order Design and test D i dt t data for manufacturing

Scan netlist
Chip layout: S Chi l t Scanchain optimization, timing verification

Test program

Mask data

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An Example of DFT Compiler Flow

compile -scan
ScanReady Synthesis

check_test
Pre-Scan DRC

insert_scan
Insert Scan

check_test
Post-Scan DRC Preview Coverage g

HDL

Constraints: Scan style, speed, area p ,

Technology Library: p p Gates, flip-flops, scan equivalents

Constraint-Based Scan Synthesis: Routing, balancing, gate-level optimization Source: H.-J. Huang, CIC

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Shift Registers
Scan added:
SHFT_IN SI SHFT_OUT/ SO

DFF

DFF

DFF

CLK SE

Revised:
SHIFT_IN SI SE CLK SHIFT_OUT

DFF

DFF

DFF

Source: H.-J. Huang, CIC

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

Lockup Latch Insertion

F1

F2

latch

F3

CLK_RTZ_1

tINV

CLK_RTZ_2

clk1 clk2

clk1 clk2

OK!

Big Problem !! Rearrange clock domain or insert lockup latch

Source: H.-J. Huang, CIC

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Random Access Scan

Uses addressable latches Provides random access to FFs via multiplexingaddress selection

X C SI
L L

C/L

SO

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Random Access Scan

Random access scan cell
DI CK1 SI C=CK1&CK2 +L

CK2 Addr

SO

Advantages
Fast; i i F t minimal i l impact on normal path t l th Fast for testingrandom access Ability to watch a node in normal operation mode

Disadvantages
Hardware cost i l H d t is large; more pins added i dd d
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Random Access Architecture

Combinational/Logic

clocks and controls y-address Y decode r

Si Addressable dd essab e storage . . . elements ... X decoder x address x-address Sout

Sin SCK

During normal operation the storage cells operate in their parallel-load mode parallel load To scan in a bit, the appropriate cell is addressed, the data are applied to sin
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

Test Procedure
1. Set test input to all test points 2.Apply 2 Apply the master reset signal to initialize all memory elements 3.Set scan in 3 Set scan-in address and data and then apply the scan data, clock 4.Repeat 4 Repeat step 3 until all internal test inputs are scanned in 5.Clock 5 Clock once for normal operation 6.Check states of the output points 7.Read the scan-out states of all memory elements by applying appropriate X-Y signals
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

Scan-Hold FFs (SHFFs)

HOLD=0 Q & Q are fixed
SO D SI TC CK SFF Q Q

HOLD

The control input HOLD keeps the output steady at previous state of flip-flop Applications
Reduce power dissipation during scan, etc.
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Scan Enters the Nanometer Era

Trend in flip flop count with design size

[Source: EE Times]
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Scan Enters the Nanometer Era

Adaptive scan architecture

[Source: EE Times] [S Ti ]
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Syndrome-Testable Design
Definition
S( f )

The syndrome of a Boolean function f is , where k is the number of 1s (minterms) in f and n is the number of independent input variables A typical syndrome testing set up set-up
(Counter) CUT Exhaustive patterns Syndrome register
Reference syndrome

k( f ) 2n

Comparator C t Go/No-go

0 S( f ) 1

y A circuit is syndrome testable iff fault , S ( f ) S ( f ) Syndromes of logic gates

Gate

S
Advanced Reliable Systems (ARES) Lab.

ANDn 1 / 2n

ORn 1 (1 / 2 n )

XORn 1/2

NOT 1/2
32

Jin-Fu Li, EE, NCU

Syndrome Computation
Consider a circuit having 2 blocks, f and g, with unshared inputs p
O/P Gate

OR S f + Sg S f Sg

AND XOR NAND S f S g S f + S g 2 S f S g 1 S f Sg

NOR 1 S f Sg + S f Sg

Example
Calculate the syndrome of the following circuit
S1 = 1 1/4 = 3/4 1-1/4 S2 = 1-1/4 = 3/4 S3 = 1/8 S4 = 1- S2 - S3 + S2S3 = 7/32 S = S1S4 = 21/128

S1 S2 S4 S3
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Syndrome-Testable Design
Consider the function f = xz + y z . The circuit is syndrome untestable
If the circuit has a fault z / 0 , then the corresponding syndrome of the faulty circuit is S'f =1/ 2 Thus the circuit is syndrome untestable

S f = 1/ 2

A realization C of a function f is said to be syndrome-testable if no single stuck-at fault causes the circuit to have the same syndrome as the fault-free circuit Syndrome is a property of function, not of implementation
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

Syndrome-Testable Design
Definition
A logic function is unate in a variable xi if it can be g represented as an SOP or POS expression in which the variable xi appears either only in an uncomplemented form or only in a complemented form For example:

in x1

f ( x1 , x 2 ) = x1 x 2 + x1 x 2 no unate f ( x1, x2 , x3 ) = x1 x2 + x2 x3 + x1x3 unate in x2 , x3 , not unate

Theorem
A 2-level irredundant circuit realizing a unate l l d d l function in all its variables is syndrome testable
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

Syndrome-Testable Design
Theorem
Any 2-level irredundant circuit can be made y syndrome-testable by adding control inputs to the AND gates

For example
The function f = xz + y z is syndrome untestable Now add a control input c f = cxz + y z , where 1 when in normal operation mode C normal i/ l i/p when in test mode h i t t d S = 3 / 8, f = y , and S = 1 / 2 S Syndrome testable

Drawbacks
Only for combinational logic Exhaustive; modification doubles test set size
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Easily Testable Circuits

Regularly structured circuits consists of an array of identical cells
They may be arranged in one-, two- or threedimensional arrays

(i, j )
i 1

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Iterative Logic Arrays

Combinational regular structures are usually referred to as iterative logic arrays (ILAs) For example
N-bit comparators are often organized in a onedimension array and each compares the corresponding bit from two numbers A parity tree consists of cells and every cell is realized with a two-input XOR

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C-Testability
Definition
A C-testable array is an array testable with constant number of test patterns i d t t b ft t tt independent of the d t f th size of the array

A cell is a combinational machine ( , , f ) , where f : is the cell function and = {0,1}I and = {0,1}O for I , O N Definition
), A cell function is injective if (i1, j1) (i2, j2 ) f (i1, j1) f (i2, j2 ) . If a function is injective and = , then the function is bijective.

Theorem
A k -dimensional ILA with a bijective cell function is C-testable
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Design for C-Testability

A 2complement array multiplier
a
b

s
a

s
c

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Jin-Fu Li, EE, NCU

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Design for C-Testability

Modified the multiplier such that the inputs of the AND gate can be fully controlled g y
a
b

a
b

z
w

s
a

s
c

s
a

s
b c
41

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

Design for C-Testability

Truth table of the multiplier cell Truth table of the modified multiplier cell

a
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

z
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

s c
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

a b s c
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1

a
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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z
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

s c
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

a b s c
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
42

Advanced Reliable Systems (ARES) Lab.

Test Pattern Application

Test application
( , (Ii,Ji) are all p possible combinations Thus we only need apply (Ii,Ji), the array can be tested regardless of the array size
J1

J
I2

I1
J
2

I3
J3
J
4

I4

I2
J3

I3

(i, j )
J

I4
4

I5

I3
J

I4

I5

J5

I6

J5

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Introduction to Built-In Self-Test

Built-in self-test (BIST):
The capability of a circuit (chip/board/system) to test itself lf

Advantages of BIST
Test patterns generated on chip controllability on-chip increased ( (Compressed) response evaluated on-chip p ) p p observability increased Test can be on-line (concurrent) or off-line Test can run at circuit speed more realistic; shorter test time; easier delay testing External test equipment g q p greatly simplified, or even y p , totally eliminated Easily adopting to engineering changes
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Introduction to Built-In Self-Test

On-line BIST
Concurrent (EDAC, NMR, totally self-checking ( , , y g checkers, etc.):
Coding or modular redundancy techniques (fault tolerance)
Module 1 Module 2

Voter

Output

Module N

N-Modular Redundancy (NMR)

Instantaneous correction of errors caused by temporary or permanent faults

Nonconcurrent (diagnostic routines):

Carried out while a system is in an idle state y
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Introduction to Built-In Self-Test

Off-line BIST
A typical BIST architecture
Functional Circuit (Circuit U d (Ci it Under Test) T t)

PG

RA

Go/No Go Go/No-Go

Controller BIST

Test generation
Prestored TPG, e.g., ROM or shift register Exhaustive TPG, e.g., binary counter , g, y Pseudo-exhaustive TPG, e.g., constant-weight counter, combined LFSR and SR Pseudo-random pattern gene ato e g Pse do andom patte n generator, e.g., LFSR
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Introduction to Built-In Self-Test

Response analysis
Check-sum Ones counting Transition counting Parity h ki P it checking Syndrome analysis Etc. Etc

Linear feedback shift register (LFSR) can be both the test generator and response analyzer We need a gold unit to generate the good signature or a simulator

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Signature Analysis
A compression technique based on the concept of cyclic redundancy checking (CRC) and realized i hardware using li li d in h d i linear f db k feedback shift registers Definition D fi iti
A function f(x1,x2,,xn) is said to be linear if it can be expressed in the form

f = a 0 a1 x1 a 2 x 2
,n

an xn

where a i {0,1} i = 0,1,

There are 2n+1 linear functions of n variables Linear operations: modulo addition, module scalar multiplication, & delay Nonlinear operations: AND, OR, NAND, NOR, etc.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48

Linear Feedback Shift Register

Definition
A linear feedback shift register is a shift g register with feedback paths which consist only of unit delays and XOR operators

Let M=fault-free circuit response, B=faulty circuit response, and E=error syndrome (Hamming), where E M B th (H i ) h E=M thus M B E M=B and B=M E
We W need a circuit to take B as input and d i it t t k i t d compact it but still be able to tell if M!=B

LFSR is considered as a popular approach for conside ed pop la app oach fo test response compaction
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49

Structures of LFSR
Two types of generic standard LFSRs

C1

C2

CN-1

CN

D FF
Y1

D FF
Y2 YN-1

D FF
YN

C1

C2

CN-1

CN

D FF
Y1

D FF
Y2
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D FF
YN-1 YN
50

Advanced Reliable Systems (ARES) Lab.

Mathematical Foundation of LFSR

As a function of time, Yj can be expressed as Y j (t ) = Y j 1 (t 1) for j 0 Hence Y j (t ) = Y0 (t j ) H

If we denote the translation operator as Xk, where k i the time translation unit h is th ti t l ti it Y j (t ) = Y0 (t ) X j On the Nth h d O th other hand, Y0(t) can b expressed as be d Then Th
Y0 (t ) = C jY j (t )
j =1

Y0 (t ) = C jY0 (t ) X j for 1 j N
j =1

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Mathematical Foundation of LFSR

We can rewrite the Y0( ) as h (t)
Y0 (t ) = Y0 (t ) C j X
j =1 N j =1 N j

j Also, Also Y 0 ( t )( C j X + 1) = 0

We can rewrite this expression as Y0 (t ) PN ( X ) = 0

For nontrivial solution, Y0 (t ) 0 , we must have P (X ) = 0 N (X

where PN ( X ) = 1 + C j X j
j =1

PN (X ) is called the characteristic polynomial of the LFSR

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52

LFSR for Signature Analysis

A serial input stream mn, mn-1,, m1, m0 entering the LFSR can be considered as the coefficients of a polynomial ffi i t f l i l
m ( X ) = mn X n + mn 1 X n 1 +
C0 C1

+ m1 X + m0
C2 Cr-1 Cr

D FF
m(X) s1

D FF
s2 sr-1

D FF

q( ) q(X) sr

The LFSR is said to have a characteristic polynomial defined as follows

c( X ) = cr X r + cr 1 X r 1 +
Advanced Reliable Systems (ARES) Lab.

+ c1 X + c0
53

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LFSR for Signature Analysis

Assume that the initial state of the LFSR is Di=0, i=0,,r-1, then the LFSR effectively divides di id any m(X) b c(X), i (X) by (X) i.e.,
m ( X ) = q( X ) C ( X ) + s( X )

The Th quotient q(X) appears serially at the i (X) i ll h output of the SR. The remainder s(X) is in the SR after n+1 shifts:
s ( X ) = sr X r + sr 1 X r 1 + + s1 X + s0

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An Example
The following LFSR divides any m(X) by c(X)=X5+X4+X2+1

m(X)

D0

D1

D2

D3

D3

q(X)

Suppose m(x)=X7+X6+X5+X4+X2+1 then +1, q(X)=X2+1, and s(X)=X4+X2

I/P 10101111 101 10 1 Advanced Reliable Systems (ARES) Lab.

D0 D1 D2 D3 D4 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1

O/P 1 01 101
55

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Signature Analysis
Let m(X) be the input polynomial of degree k-1, q(X) the quotient, and s(X) the signature (remainder). Then m(X)=q(X)c(X)+s(X) The error syndrome can be represented as a polynomial e(X) E.g., le m(X)=X4+X3+1(11001), and an erroneous m(X) X input b(X)=X3+X+1(01011), then the error syndrome is 11001 01011=10010, and is represented b e(X)=X4+X t d by (X) X In general, an erroneous input polynomial can be represented by B(X)=m(X)+e(X)

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Signature Analysis
Theorem1: Input streams m(X) and b(X) have the same signature iff e(X) is a multiple of c(X)
Proof: an error is not detected when m(X) and b(X) have the same signature, i.e., b(x)=q(X)c(X)+s(X). Since m(X)=q(X)c(X)+s(X), we obtain e(X)=m(X)+b(X)=c(X)(q(X)-q(X)) (X) (X) b(X) (X)( (X) (X))

Theorem2: Undetected errors correspond to error patterns which are multiples of c(X) Theorem3: If c(X) has 2 or more nonzero , coefficientsi.e., at least 1 feedback termthen it can detect all single-bit errors
Proof: all nonzero multiples of c(X) must have at least 2 nonzero coefficients. Therefore, any error with only 1 ffi i t Th f ith l nonzero coefficient cannot be a multiple of c(X) and must be detectable.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57

Aliasing Probability
Theorem4: for a k-bit response sequence, if all possible error patterns are equally likely, then the probability p obabilit of failing to detect an error (i.e., the e o (i e aliasing probability) by the LFSR of length r is 2 k r 1 Pal = k 2 1 Proof: For a k-bit response, deg(m(X))=k-1, and k bit deg(m(X)) k 1, deg(e(X))<=k-1. Therefore, the number of possible error polynomial is represented by e(X)=c(X)p(X) for fo some nonzero p(X). Since deg(c(X)) non e o p(X) deg(c(X))=r, the number of possible p(X)s is 2k-r-1. Thus
2 k r 1 Pal = k 2 1

For a long sequence, k>>r Pal~1/2r g q , /

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 58

Multiple-Input Signature Register

The structure of multiple-input signature register (MISR)
D0 D1 Dr-2 Dr-1

D FF

D FF

D FF

Cr

Cr-1

C2

C1

The mathematical theory is a direct extension of the results shown above For equally likely error patterns and long data streams, the aliasing probability for an MISR of r stages also is P 1/ 2r.
al
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 59

Response Compaction
Usually, we think of data compression as a process that preserves data integrity. This is why we given more attention here to data compaction, which may result in some losses There are several compaction testing techniques Parity testing One counting Transition counting Syndrome calculation Signature analysis

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Parity Testing
This is the simplest of all techniques but also the most lossy The parity of responses to the test patterns is calculated as i=L P = i =1 ri , where L is the length of the test and ri is the response for the ith test pattern The response of the circuit under test (CUT) to pattern i and the partial product Pi-1 is illustrated as below

Test Patterns
Advanced Reliable Systems (ARES) Lab.

CUT

ri

Pi 1
D FF
61

Jin-Fu Li, EE, NCU

One Counting
The number of 1s in the response stream is calculated and compared to the number of 1s in the fault-free esponses fa lt f ee responses Consider the circuit shown below
a b c
11110000 11001100 11101010 10101010 11000000

If we have a test of length L and the fault free count fault-free is m, the possibility of aliasing is [C(L,m)-1] patterns out of a total number of possible strings of length L, p g g , (2L-1)

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

62

Transition Counting
In transition counting compaction, it is only the number of transition 0 1 and 1 0 that are counted. Thus Th s the signature is given by signat e gi en b i = L1 i=1 ri ri+1 , where the summation is ordinary addition and is XOR operation The compaction scheme is shown below

ri
Test Patterns

CUT

D FF

ri 1

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

63

Pseudorandom Pattern Generator

Logic BIST uses mostly pseudorandom (PR) tests. They are usually much longer than deterministic tests, but a e definitel tests b t are definitely less costly to generate costl gene ate PR tests are generated using a LFSR or cellular automata By means of a simple circuit called an autonomous linear feedback shift register (ALFSR) g ( ) Definition: an ALFSR is a LFSR with no external inputs Faults that are hard to detect with PR tests are called random pattern resistant faults

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

64

Pseudorandom Pattern Generator (PRPG)

Example: the following ALFSR generates the pseudorandom sequence shown in the table below

Q1

Q2

Q3

Q4

output

State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15=0
Q1 Q2 Q3 Q4 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0

The output sequence is 000111101011001, which repeats after 15(2n-1) clocks p g Max period for an n-stage ALFSR=2n-1 All-0 state of the register cannot occur in the max-length cycle
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 65

Mathematical Foundation of PRPG

A generic structure of ALFSR

C1

C2

Cn-2

Cn-1

Cn

am

Q1

am 1

Q2

am 2

Qn-1

amn+1 n

Qn

am n m

A sequence of bits {am}=a0,a1,,am, can be associated with a polynomialits generation function:

G ( X ) a0 + a1 X +

+ am X +
m

= m = 0 a m X m

In th I the above figure, assume that the current state of Qi i b fi th t th t t t f is am-i, i=1,2,,n, and the initial state of Qi is a-i=0, n i=1,2,,n, but a-n=1, then am = i =1 ci ami
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 66

Mathematical Foundation of PRPG

G(X ) =

m =0

am X
i

m =0 i

(
+ +
+

i =1

cia m i ) X
1

i =1

ci X

m =0 m i

a m i X

m i

= =
=

i =1

ci X [a i X ci X [a i X
ci X i [a i X
i

+ a 1 X + a 1 X
+ a 1 X
n

+ +

m =i

a m i X am X
m

i =1

m =0
1

+ G ( X )]
i

i =1

= 1+

i =1

ci X G ( X ) + ci X G ( X ) =
i

i =1

ci X i ( a i X ci X i ( a i X
i n

+ +

+ a 1 X + a 1 X
1

i =1

i =1

G(X ) =

n i =1

ci X i ( a i X 1+

+
i

+ a 1 X

c X i =1 i

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

67

Mathematical Foundation of PRPG

Now c( X ) = 1 + i =1 ci X i is the characteristic polynomial of the LFSR as defined above. Since a-1=0, i=1,2,,n-1, and a-n=1 we have =1,
n

The sequence {am} is cyclic with the period assumed cyclic, to be p

G(X ) = 1 = ( a 0 + a1 X + + a p 1 X p 1 ) c( X ) + X p ( a 0 + a1 X + + a p 1 X
+ X
+
2p p 1

1 G(X ) = = c( X )

m =0

) )
p

( a 0 + a1 X +

+ a p 1 X
p 1
p 1

p 1

= ( a 0 + a1 X +
= ( a 0 + a1 X + 1 X
+ a p 1 X

+ a p 1 X
+ a p 1 X
p
p 1

)( 1 + X
)

+ X

2p

1 X p = a 0 + a1 X + c( X )
Advanced Reliable Systems (ARES) Lab.

i.e., c(X) evenly divides into 1-Xp 1X

68

Jin-Fu Li, EE, NCU

Theorems
Theorem: If the initial state of an n-stage LFSR is a-i=0, i=1,2,,n-1, and a-n=1, then the LFSR sequence {am} is i periodic with a period th t i th smallest i t i di ith i d that is the ll t integer p for which c(X) divides 1-Xp
The period p<=2n-1 p< 2 1 For a given n, we want to find a c(X) that maximizes p

Definition: The sequences produced by max-length LFSRs are called pseudorandom sequences or msequences. The characteristic polynomial associated with an m-sequence is called a primitive polynomial polynomial. An irreducible polynomial is one that cannot be factored
Pseudorandom sequences (or m-sequences) are not really random since they are produced by a fixed circuit.

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

69

Theorems
Theorem: An irreducible polynomial c(X) satisfies the following 2 conditions:
It has an odd number of terms including the constant h dd b ft i l di th t t term If its degree n>3, then c(X) must divide 1+Xp, where g , ( ) p=2n-1

Theorem: A primitive polynomial is irreducible if the smallest positive integer p that allows the polynomial to divide evenly into 1+Xp occurs for p=2n-1, where n is the degree of the p y g polynomial

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

70

Built-In-Logic-Block-Observer (BILBO)
A BILBO is a multi-purpose test module which serves as a test generator or a signature analyzer. It is composed of a row of FFs and some additional gates for shift and feedback operation
Z1 B1 B2 SI
0 1

Z2

Z3

Z4

B1 B2
0 1 0 1 1 1 0 0

Function
All FFs are reset Behaves as separate latchesnormal mode A linear shift registerSR mode MISR/PRPGtest mode
Jin-Fu Li, EE, NCU 71

Advanced Reliable Systems (ARES) Lab.

STUMPS Architecture
Logic BIST with STUMPS architecture
PRPG

PIs
Test T t control signal

CUT BSR

POs

MISR

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

72

Summary
Design-for-testability techniques
Ad-hoc techniques q Scan LSSD Random access scan Syndrome-testable C-testability

Scan is a popular DFT technique in modern IC design DFT can increase the controllability and observability of the circuit under test

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

73

Summary
Built-in self-test methodology is more and more important for deep submicron designs p p g Two key components of BIST
Test pattern g p generator
E.g., LFSR

Response evaluator
E.g., BILBO

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

74