Computer Organization and

Software Systems

Contact Session 5 Dr. Lucy J. Gudino

 Associative Mapping

• A main memory block can load into any line of cache

• Memory address is interpreted as tag and word
• Tag uniquely identifies block of memory
• Every line’s tag is examined for a match
• Cache searching gets expensive
Associative Cache Organization
 Associative Mapping Summary

• Address length = (s + w) bits

• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in cache = undetermined
• Size of tag = s bits
 Problem 7

•Given :
• Cache of 128KByte, Cache block of 8 bytes
• 32 MBytes main memory
•Find out
a) Number of bits required to address the memory

b) Number of blocks in main memory

c) Number of cache lines

d) Number of bits required to identify a word (byte) in a block?

e) Tag, Word
 Problem 8
•Cache of 64KByte, Cache block of 4 bytes , 16 M Bytes main memory and
associative mapping.
Fill in the blanks:

Number of bits in main memory address = _____

Number of lines in the cache memory = ______

Word bits = _________

Tag bits = ________

 Problem 9

• 16 Bytes main memory, Memory block size is 4 bytes, Cache of 8

Byte (cache is 2 lines of 4 bytes each ) and associative mapping.
Block access sequence :
0 2 0 2 2 0 0 2 0 0 0 2 1
Find out hit ratio.

0 2 0 2 2 0 0 2 0 0 0 2 1
 Set Associative Mapping
• Cache is divided into a number of sets (v sets each with k lines)
• m=v*k
• i = j modulo v
where i = cache set number
j = main memory block number
v = number of sets in the cache
• Each set contains ‘k’ number of lines
• A given block maps to any line in a given set
- e.g. Block B can be in any line of set i
• m-way set associative cache
- 2 way set associative mapping  2 lines per set
- A given block can be in one of 2 lines in only one set
 Example
• 16 Bytes main memory,
Block Size is 2 Bytes,
• Cache of 8 Bytes, 2 way set
associative cache i = j modulo v Set #
• # address bits 0%2
• Cache line size 1%2
• # main memory blocks 2%2
• # Number of cache lines 3%2
• # lines per set
4%2
• # of sets
5%2
6%2
7%2
Two-Way Set Associative Cache Organization
 Set Associative Mapping Summary

• Address length = (s + w) bits

• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2d
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (s – d) bits
 Problem 1
• A set-associative cache
consists of 64 lines, or slots,
divided into four-line sets.
Main memory contains 4K
blocks of 128 bytes each.
Find out
• Total main memory capacity
• Total cache memory capacity
• Total number of sets in the
cache
• Number of bits for TAG, SET
and word
 Problem 2: Home work

• A computer has an 8 GByte memory with 64 bit word sizes. Each block of
memory stores 16 words. The computer has a direct-mapped cache of 128
blocks. The computer uses word level addressing. What is the address
format? If we change the cache to a 4- way set associative cache, what is
the new address format?
 Replacement Algorithms (1/3)

Direct mapped cache

• No choice
• Each block maps to one line and replace that line
 Replacement Algorithms (2/3)

• Needed in Associative & Set Associative mapped cache

• Hardware implemented algorithm (speed)
• Methods:
- Least Recently Used (LRU)
- Least Frequently Used (LFU)
- First In First Out (FIFO)
- Random
 Replacement Algorithms (3/3)

• Least Recently used (LRU): Replace the block that has been in
the cache longest with no reference to it
- e.g. 2 way set associative
- Uses “USE” bits
- Most effective method

• Least frequently used: Replace block which has had fewest hits
- Uses counter with each line

• First in first out (FIFO): Replace block that has been in cache
longest
- Round robin or circular buffer technique

• Random
 Problem 3

• Consider a reference pattern that accesses the sequence of blocks 0, 4, 0, 2, 1, 8,

0, 1, 2, 3, 0, 4. Assuming that the cache uses associative mapping, find the hit
ratio for a cache with four lines
a) LRU
b) LFU
c) FIFO
Problem 2 - LRU
Ref 0 4 0 2 1 8 0 1 2 3 0 4

time 0 1 2 3 4 5 6 7 8 9 10 11

L0

L1

L2

L3

H/M
 Problem 2 - LFU
Ref 0 4 0 2 1 8 0 1 2 3 0 4

L0

L1

L2

L3

H/M
Problem 2 - FIFO
Ref 0 4 0 2 1 8 0 1 2 3 0 4

time 0 1 2 3 4 5 6 7 8 9 10 11

L0

L1

L2

L3

H/M
Issues with Writes
• Multiple copies of data exist:
• L1, L2, L3, Main Memory, Disk
• What to do on a write-hit?
• Write-through (write immediately to memory)
• Write-back (defer write to memory until replacement of line)
• Need a dirty bit (line different from memory or not)
Intel Core i7 Cache Hierarchy
Intel Core i7 Cache Hierarchy
 Performance Impact of Cache Parameters
• Associativity :
• higher associativity  more complex hardware
• Higher Associativity  Lower miss rate
• Higher Associativity  reduces average memory access time (AMAT)
• Cache Size
• Larger the cache size  Lower miss rate
• Larger the cache size  reduces average memory access time (AMAT)
• Block Size:
• Smaller blocks do not take maximum advantage of spatial locality.
Revisiting Locality of reference

Does this function

have good locality?

N=8
Address 0 1 2 3 4 5 6 7
Contents V[0] V[1] V[2] V[3] V[4] V[5] V[6] V[7]
Access Order 1 2 3 4 5 6 7 8
Stride k – Byte Addressable
memory and word
reference pattern length is 1 byte

i Address i Address
0 0000 0 0000
Stride 1
1 0001 1 0001
2 0002 2 0002 Stride 2
3 0003 3 0003
4 0004 4 0004
Address difference
5 0005 5 0005
Stride=----------------------
6 0006 Word Length 6 0006
7 0007 7 0007
8 0008 8 0008
9 0009 9 0009
10 000A 10 000A
11 000B 11 000B
12
26 000C 12 000C
Stride k – reference pattern
Byte Addressable
memory and word
length is 2 bytes
i Address i Address
0 0000 0 0000
Stride 1
1 0002 1 0002 Stride 2
2 0004 2 0004
3 0006 3 0006
4 0008 4 0008
Address difference
5 000A 5 000A
Stride=----------------------
6 000C Word Length 6 000C
7 000E 7 000E
8 0010 8 0010
9 0012 9 0012
10 0014 10 0014
11 0016 11 0016
12
27 0018 12 0018