Chapter IV CAO
Chapter IV CAO
College (ATTC)
Menschen fuer Menschen Foundation
CHAPTER 4
MEMORY SYSTEM DESIGN
BY
Mr. Chala Tesfaye
❑ Main Memory
❖ SRAM
❖ DRAM
❑ Organization of a Memory Chip
❑ Cache Memory
▪ Access time is constant and does not depend on location or previous access.
▪ Example: Cache memory in CPUs quickly finds frequently used data without
searching by address.
1. CHARACTERISTICS OF A MEMORY SYSTEM
❑ Performance of Memory Systems
▪ Access Time: The time taken from the moment a request is made until the memory
provides valid data.
• Example: How long it takes for a computer to find and open a file when you search for
it.
• Cycle Time: The total time it takes for the memory to complete one operation, which
includes the time to access the data and the time needed to get ready for the next operation.
• Formula: Cycle Time = Access Time + Recovery Time
• Example: How long it takes for a memory chip to give data and then be ready to give
more.
• Transfer Rate: The speed at which data can be moved or transferred from one place to
another within the system.
• Example: The speed at which data is transferred from your computer to a USB drive.
1. CHARACTERISTICS OF A MEMORY SYSTEM
❑ Physical Types of Memory
• Semiconductor Memory: Uses electronic circuits to store data.
• Non-Volatile: Memory that retains its data even when the power is turned off
(e.g., ROM, Hard Drives).
• Erasable / Non-Erasable
• Erasable: Memory that can have its data erased and rewritten (e.g., RAM, CD-RW).
• Low Power: Memory that uses less electricity (e.g., Flash memory).
• Memory is organized into bits (the smallest units of data) grouped together into
words (larger units of data).
• The way these bits and words are organized can affect how the memory is accessed
and used, but the organization is not always obvious or straightforward.
2. MEMORY HIERARCHY
❑ Memory design is governed by three questions:
How Large? How much data does the memory need to store?
How Fast? How quickly does the memory need to provide data to the system?
How Much? How much should the memory cost to implement?
❑ To balance speed, size, and cost, memory systems are arranged in levels, with each type
of memory serving a different purpose.
• Fast and Small: Cache memory (expensive, quick).
• Large and Slow: Hard drives (inexpensive, slower).
• Balanced: RAM (middle ground between speed and size).
2. MEMORY HIERARCHY
❑ Memory hierarchy is the organization of memory in a computer system based on speed,
cost, and capacity.
❑ Faster memory is expensive but small in size, while slower memory is cheaper and larger.
❖ During the execution of a program, memory references for instructions and data tend
to cluster.
❖ Keeping the current cluster in the faster memory level allows faster memory access.
3. MAIN MEMORY
❑ Relatively Large and Fast: Main memory is large enough to store the programs and data the
CPU is currently using, and it provides quick access to this information.
❑ Used for Program and Data Storage During Operation: It temporarily holds the operating
system, applications, and data that are actively being used by the computer.
❑ Based on Semiconductor ICs: The technology behind main memory relies on semiconductor
integrated circuits (ICs), which make it small, fast, and reliable.
❑ Usually Referred to as RAM (Random Access Memory): Main memory is often called
RAM because it allows random access to any memory location, meaning the CPU can
directly access data from any location without needing to follow a sequence.
❑ More Accurate Name – Read/Write Memory (R/W Memory): A more precise description
of this memory type would be Read/Write Memory because data can both be read from and
written to main memory
3. MAIN MEMORY
❑ RAM (Random Access Memory)
• Read and Write Operations: RAM allows both reading data from and writing data to
memory, enabling the CPU to access and update data as needed.
• Performed Electrically: Both read and write operations in RAM are carried out using
electrical signals.
• Volatile: RAM is volatile, meaning it loses its stored data when the power is turned off.
• It is used only for temporary storage while the computer is running.
• Temporary Storage: Since RAM is volatile, it is used to store data and instructions
only while the computer is operating. Once the power is lost, all data in RAM is erased.
• Two Main Varieties:
• Static RAM (SRAM): Faster and more reliable.
• Stores data using flip-flops (no need to refresh), but is more expensive and consumes
more power.
• Dynamic RAM (DRAM): Slower than SRAM but cheaper and more common.
• Stores data in capacitors, which need to be periodically refreshed to retain the data.
3. MAIN MEMORY
Dynamic RAM (DRAM)
❑
❖ Used for Main Memory: DRAM is the primary memory in most computer systems
due to its affordability and large capacity.
❖ Inexpensive: It is cheaper than Static RAM (SRAM), making it ideal for high-capacity
memory needs.
❖ Uses One Transistor per Bit: Data is stored as an electrical charge in capacitors.
• This design allows for high-density memory storage.
❖ Destructive Read:
▪ When data is read from DRAM, the charge in the capacitor is drained.
▪ The data must be rewritten immediately after reading to prevent loss.
3. MAIN MEMORY
❑ Dynamic RAM (DRAM)
❖ Charge Decay: The electrical charge stored in the capacitor naturally fades over time.
❖ Need for Refreshing: DRAM must be refreshed periodically, even when powered, to
prevent data loss.
❖ Refreshing Process: The memory controller reads and rewrites each word every few
milliseconds to restore the charge.
❖ Refresh Rate: The frequency at which DRAM is refreshed to maintain data integrity.
❖ Power Usage in Suspended Mode: In laptops, during standby mode, power is primarily
used for DRAM refresh to keep data intact.
3. MAIN MEMORY
❑ Static RAM (SRAM)
• Stores data using flip-flops, which are tiny circuits that hold binary information (0s
and 1s).
• No need for refreshing because the data stays as long as power is on.
• Non-destructive read, meaning reading the data doesn’t erase it.
• More complex design, making it larger in size and less dense (stores less data per
chip).
• More expensive than other types of memory.
• Faster than other types of RAM.
Main Use: SRAM is mostly used for Cache Memory, which is a small, super-fast
memory that helps speed up processing.
3. MAIN MEMORY
Feature SRAM (Static RAM) DRAM (Dynamic RAM)
Storage Cell
More complex (flip-flop) Simpler (capacitor & transistor)
Complexity
Density Less dense Denser (more bits per unit area)
Cost More expensive Less expensive
Power Consumption Higher Lower
Speed Faster Slower
Retains data as long as power is
Data Retention Requires frequent refreshing
supplied
Extra Circuitry No need for refresh mechanism Needs refresh circuitry
Cache memory (CPU caches, Main memory (RAM in
Primary Use
high-speed applications) computers)
Key Takeaways:
• DRAM is preferred for main memory due to its higher density and lower cost.
• SRAM is used in cache memory where speed is critical despite its higher cost and larger cell size.
3. MAIN MEMORY
SRAM CHIP
ORGANIZATION
3. MAIN MEMORY
❑ Read-Only Memory (ROM)
• Can only be read, not written to (data is fixed).
• Non-volatile, meaning it keeps its data even when power is off.
• Used for:
Manufactured with data permanently stored, so there’s no room for mistakes once
written, it cannot be changed.
3. MAIN MEMORY
ROM STRUCTURE
3. MAIN MEMORY
❑ Programmable ROM (PROM)
• Non-volatile → Data stays even when power is off.
• Write Once, Read Forever → Can be programmed only once; no changes allowed
afterward.
• Uses Fuses Instead of Diodes → Programming burns specific fuses with a high-
voltage pulse (10–30V) to store data.
❑ Used for permanent data storage in devices like firmware, security keys, and
hardware configurations.
3. MAIN MEMORY
❑ Erasable PROM (EPROM)
• Non-volatile → Data stays even when power is off.
• Uses floating-gate MOS transistors → These transistors store data that changes
behavior when exposed to ultraviolet (UV) light.
• Programmed electrically → Data is written electrically, but it can be erased and
reprogrammed using UV light.
• Erasing → Erasing takes about 20 minutes and can be done up to 100,000 times.
• Before writing → All cells must be erased first by exposure to UV light.
❑ Used in applications where you might need to update or modify data, like firmware
updates and development.
3. MAIN MEMORY
❑ Electrically Erasable PROM (EEPROM)
• Non-volatile → Data is retained even when power is off.
• Uses floating-gate transistors with thinner insulating material compared to EPROM.
• Inversion with voltage → Its operation can be reversed using electrical voltage,
allowing for writing and erasing.
• Can be written to anytime → You can modify data without erasing the existing
contents. Only the specific bytes addressed are changed.
• Write time → Writing data takes about 100 microseconds per byte.
• Erasing limit → Can be erased around 10,000 times.
• Updatable in place → Data can be updated without needing to remove the chip.
• More expensive and less dense than EPROM → Costs more and stores less data per
chip.
❑ Used in situations where data needs to be updated occasionally, like in BIOS, firmware,
and small data storage.
3. MAIN MEMORY
❑ Flash Memory
• Called "flash" because it can be re-programmed very quickly, with the whole chip
being erased in 1-2 seconds.
• Uses electrical erasure technology → The entire chip or specific blocks of data can be
erased quickly, but it doesn’t support erasing individual bytes.
• One transistor per bit → This allows for very high density, meaning it can store a lot
of data in a small space.
• Cost → Flash memory is less expensive than EEPROM but more expensive than
EPROM.
• Non-volatile → Data is retained even when the power is turned off.
❑ Used in USB drives, SSDs, memory cards, and devices that require fast, reliable, and high-
capacity storage.
4. ORGANIZATION OF A MEMORY CHIP
❑ The basic element of a semiconductor memory is the memory cell.
❖ There are different types, but they all share some common properties:
We will apply 9 wires to the row selectors and 9 to the column selectors
The outputs of the chips are combined together to form the 8 bit output of the system.
ORGANIZATION OF THE 256 K
BYTE SYSTEM
What if the size of the system is not the same as the chips?
Some of the address wires will have to be used for selecting different rows of chips.
ORGANIZATION OF THE 1 M BYTE SYSTEM
6. CACHE MEMORY
❑ Purpose of Cache Memory
• Provides high-speed access to frequently used data.
• Offers fast memory speed like the best available memory types.
• Helps achieve a large memory size at a lower cost by combining fast and slower
memory types efficiently.
❑ Characteristics of Cache Memory
❑ Cache memory improves processing speed by storing frequently accessed data, reducing
the need for slow main memory access.
CONCEPTUAL OPERATION
❑ Relatively large and slow main memory together with faster, smaller cache.
❑ Cache contains a copy of portions of main memory.
❑ When processor attempts to read a word from memory, a check is made to determine if
the word exists in cache.
If it is, the word is delivered to the processor.
If not, a block of main memory is read into the cache, then the word is delivered to
the processor.
Word Block
Transfer Transfer
CPU Cache
Memory
Main
Memory
HIT RATIO
❑ A measure of the efficiency of the cache structure.
When the CPU refers to memory and the word is found in the cache, this called a hit.
❑ Hit ratio is the total number of hits divided by the total number of access
attempts (hits + misses).
It has been shown practically that hit rations higher than 0.9 are possible.
CACHE VS. MAIN MEMORY STRUCTURE
0 ❑Main Memory consists of 2n addressable words.
1
❖ Each word has a unique n-bit address.
2 Block
(K words) ❑We can consider that main memory is made up of blocks of K words
each. Usually, K is about 16
❑ Mapping function
❑ Replacement algorithm
❑ Write policy
❑ Line size
❑ Number of caches
❑Cache Size
❖Small enough ---not to be costly or expensive
❖Large enough so overall average access time is small
❖Affected by the available chip and board area
ELEMENTS OF CACHE DESIGN...
❑ Mapping Function
Number of cache lines <<< Number of blocks in main memory
Mapping function needed
A method to map main memory blocks into cache lines
(224=16M)
DIRECT MAPPING
❑ Each block of main memory maps to only one cache line
i= j modulo m
i = cache line number,
❑ Map each block of memory into only one possible cache line.
❖ A block of main memory can only be brought into the same line of cache every time.
Cache Line Main memory blocks assigned
0 0, C, 2C, 3C, …
1 1, C+1, 2C+1, 3C+1, …
… …
Stored in the cache along with the data words of the line
No two blocks in the same line have the same Tag field
READING FROM A DIRECT MAPPED SYSTEM
❑ The processor produces a 24 bit address.
❑ The cache uses the middle 14 bits to identify one of its 16 K lines.
❑ The upper 8 bits of the address are matched to the tag field of the cache entry.
If they match, then the lowest order two bits of the address are used to access the word
in the cache line.
If not, address is used to fetch the block containing the specified word from main
memory to the cache.
ELEMENTS OF CACHE DESIGN...
❑ Direct Mapping Cache Organization
ELEMENTS OF CACHE DESIGN...
❑ Direct Mapping Summary
Simple.
Inexpensive to implement.
❑ Disadvantages.
If a program addresses words from two blocks mapped to the same line, the blocks
have to be swapped in and out of cache repeatedly.
ASSOCIATIVE MAPPING
❑ To improve the hit ratio of the cache, another mapping techniques is often utilized,
“associative mapping”.
❑ A block of main memory may be mapped into ANY line of the cache.
A block of memory is no longer restricted to a single line of cache.
• A main memory address is considered to be made up of two pieces:
Tag 22 2
Upper bits of the address
Tag Word
Word address within a block
Lower 2 bits of the address
❑ 16 Mbytes of memory.
❖ 24 bits in address.
❑ 4-byte blocks.
❖ 2 bits.
❑ Rest is used to identify the block mapped to the line.
ASSOCIATIVE MAPPING CACHE ORGANIZATION
❑ The processor produces a 24 bit address.
❑ The upper 22 bits of the address are matched to the tag field of EACH cache entry.
Advantages.
❖ Improves hit ratio for certain
situations.
Disadvantages.
❖ Requires very complicated
matching hardware for matching
the tag and the entries for each
line.
❖ Expensive.
SET ASSOCIATIVE MAPPING
❑ Set Associative Mapping helps reduce the complexity of the matching hardware for an
associative mapped cache.
❑ Cache is divided into a number of sets.
A block of main memory may map to ANY line in the given set.
A main memory address is considered to be made up of two pieces:
Tag.
Upper bits of the address.
Set number.
Middle bits of the address.
13 bits.
❑ Rest is used to identify the block mapped to the line.
❑ The cache uses the middle 13 bits to identify one of its 8 K sets.
❑ The upper 9 bits of the address are matched to the tag field of the cache entries that make
up the set.
The number of lines to match to is very limited.
Therefore, the matching hardware is much simpler.
SET ASSOCIATIVE MAPPING CACHE ORGANIZATION
SET ASSOCIATIVE MAPPING
❑ Advantages.
❑ Disadvantages.
Increasing the size of the set does not always improve the hit ratio.
2-way set associative has a much higher hit ratio than direct mapping.
❑ Direct mapping.
No choice.
Memory blocks map into certain cache lines.
The entry occupying that line must be swapped out.
❑ Associative & Set Associative:
Random.
First-in First-out (FIFO).
Least Recently Used (LRU).
Least Frequently Used (LFU).
The last three require additional bits for each entry to keep track of order, time or number of times used.
Usually, these algorithms are implemented in hardware for speed.
WRITING INTO CACHE
❑ Cache entries are supposed to be exact “copies” of what is in main memory.
What happens when the CPU wants to write into memory??
Disadvantage.
Memory write becomes slow.
❑ Write-Back
The update is done ONLY to the word in the cache and the block containing the word is
marked.
When the block is to be swapped out of cache, the word is written back to main memory.
Advantage.
Reduces memory traffic because a word may be updated several times while in cache.
Disadvantage.
Cache and memory will be out of sync.
NUMBER OF CACHES
❑ When a cache miss occurs, the system suffers through a large delay while the block is
read from main memory into the cache.
The transfer rate is limited by issues that may not be under our control.
We can insert an intermediate level of memory between cache and main memory.
CACHE LEVELS
❑ In most of today’s designs, cache sits on the same chip as the CPU. “On-chip cache”
Data travels a very short distance
❑ To reduce the penalty of a cache miss, a second level of cache is inserted between main
memory and the on-chip cache.
L2 cache
CACHE LEVELS
Memory System
Data
On Bus Bus
Off-Chip
CPU Chip
Cache
Main
Bus Cache
Memory
MPU Chip
On-Module Cache.
On-Mother-Board Cache.
Many blocks
❑ Data read and written through a magnetic head (coil) using induction
READ AND WRITE MECHANISMS
❑ Recording & retrieval via a conductive coil called ahead
❑ Write Process
High-frequency operation
❑ Constant Angular Velocity (CAV): The disk spins at a constant speed, but the data
transfer rate varies across tracks.
❑ Constant Linear Velocity (CLV): The disk adjusts its speed to keep the data transfer
rate the same across all tracks.
CHARACTERISTICS OF MAGNETIC DISKS
❖ Single or Double-Sided: Data can be stored on one or both sides of the disk.
❖ Removable or Fixed: The disk can be taken out or permanently installed in the device.
❖ Fixed or Movable Head: The head is either stationary or moves to read/write data.
❖ Single or Multiple Platters: The disk has one or more stacked platters for storing data.
❖ Head Mechanism: The part that moves the read/write head to the correct location on the
disk.
❖ Speed: How fast the disk spins, how quickly the head finds data, and how fast data is
transferred.
FIXED/MOVABLE HEAD DISK
❑ Fixed head
One read/write head per track
Heads mounted on a fixed arm
❑ Movable head
One read/write head per side
Mounted on a movable arm
FIXED/MOVABLE HEAD DISK
REMOVABLE OR NOT
❑ Removable disk
Can be removed from the drive and replaced with another disk
❑ Nonremovable disk
Total time
RAID (REDUNDANT ARRAY OF INDEPENDENT DISKS)
• RAID originally redundant array of inexpensive disks) is a way of storing the same
data in different places on multiple hard disks to protect data in the case of a drive
failure.
❑ Cons:
• Expensive for small runs → High cost if producing only a few copies.
• Slower than magnetic disks → Longer access time compared to hard drives.
• Can be “fixed”
DVD – WRITABLE
• Loads of trouble with standards