EE 309

VLSI Design
Jawar Singh
Indian Institute of Technology Patna
Key Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)
Key Properties of Complementary CMOS Gates
❑ Full rail-to-rail swing; high noise margins
❑ Logic levels not dependent upon the relative device
sizes; ratioless
❑ Always a path to Vdd or Gnd in steady state; low output
impedance
❑ Extremely high input resistance; nearly zero steady-state
input current
❑ No direct path steady state between power and ground;
no static power dissipation
❑ Propagation delay function of load capacitance and
resistance of transistors
Delay Definitions
Delay Definitions
RC Delay Models and Input Pattern Effect
❑ Delay is dependent
on the pattern of
Req
inputs A
A

❑ Low to high transition Rp

Rp Rp
▪ both inputs go low B
– delay is 0.69 Rp/2 CL A B Rp
▪ one input goes low A Rp Cint
– delay is 0.69 Rp CL Rn CL A
B Rn CL
❑ High to low transition A Rn Rn CL
Rn
▪ both inputs go high Cint
A B
– delay is 0.69 2Rn CL A
NOR2
NAND2 INV
Input Pattern Effect 3

2.5
❑ Delay is dependent
Rp Rp A=B=1→0
on the pattern of 2

inputs A B A=1, B=1→0

1.5

Rn 1 A=1 →0, B=1

CL
❑ Low to high transition

Voltage [V]
0.5
B
▪ both inputs go low 0
– delay is 0.69 Rp/2 CL Rn 0 100 200 300 400
Cint -0.5
▪ one input goes low A Input Data Delay
Pattern (psec)
– delay is 0.69 Rp CL
A=B=0→1 67

❑ High to low transition time [ps] A=1, B=0→1 64

NMOS = 0.5m/0.25 m
A= 0→1, B=1 61
▪ both inputs go high PMOS = 0.75m/0.25 m
– delay is 0.69 2Rn CL CL = 100 fF A=B=1→0 45

A=1, B=1→0 80

A= 1→0, B=1 81
RC Delay Models (Simplified)
Elmore Delay Model
Elmore Delay Model
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen to achieve effective
rise and fall resistances equal to a unit inverter (R).

Annotate gate and diffusion capacitances.

Fanout Example: 3-input NAND
Estimate worst-case rising and falling delay of 3-input NAND driving h
identical NOT gates.
Example: Complex Function
Estimate worst-case rising and falling delay of 3-input NAND driving h
identical NOT gates.

B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2
Fan-In and Fan-out Considerations
1250

A B C D 1000
quadratic
750
A CL
tpHL tp
500
B C3
250
C C2 Distributed RC model
linear
D
(Elmore delay) 0
C1 2 4 6 8 10 12 14 16

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Gates with a fan-in greater
Propagation delay deteriorates than 4 should be avoided.
rapidly as a function of fan-in –
quadratically in the worst case.
tp as a Function of Fan-Out
tpNOR2 tpNAND2 ❑ Fan-in: quadratic due to
increasing resistance and
tpINV
tp (psec)

capacitance
❑ Fan-out: each additional fan-
out gate adds two gate
capacitances to CL
2 4 6 8 10 12 14 16
eff. fan-out tp = a1FI + a2FI2 + a3FO
Slope is a function of “driving strength”
Complex Gates: Design Technique 1

❑ Transistor sizing
▪ as long as fan-out capacitance dominates
❑ Progressive sizing Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
output is the smallest)
In3 M3 C3
In2 M2 C2 Can reduce delay by more than
20%; decreasing gains as
In1 M1 C1 technology shrinks
Complex Gates: Design Technique 2
❑ Transistor ordering
critical path critical path

charged 0→1
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
0→1

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

Critical input is latest arriving signal

Place latest arriving signal (critical path) closest to the output
Complex Gates: Design Technique 3
❑ Alternative logic structures
F = ABCDEFGH

❑ Reduced fan-in -> deeper logic depth

❑ Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second
configuration).
❑ Tell which of the last two configurations is faster, lower power
Complex Gates: Design Technique 4
❑ Isolating fan-in from fan-out using buffer insertion
Gate delay:
CL CL
d=h+p
In Out effort delay Intrinsic
delay
1 2 N CL
Effort delay: h = g f
N
Delay =  ( pi + g i  f i ) (in units of tinv)
i =1 logical effort
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4 effective fanout = Cout/Cin
How to generalize this to any logic path?
Generalize Delay to any Logic Path
• Delay has two components: d = f + p
f: effort delay = gh (a.k.a. stage effort)
Again has two components
• g: logical effort
Measures relative ability of gate to deliver current
g = 1 for inverter
• h: electrical effort = Cout / Cin
Ratio of output to input capacitance
Sometimes called fanout
• p: parasitic delay
Represents delay of gate driving no load
Set by internal parasitic capacitance

❑ Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates
❑ Logical effort of a gate presents the ratio of its input capacitance to the inverter
capacitance when sized to deliver the same current
❑ Logical effort increases with the gate complexity
Example: Best Number of Stages
2-input NAND Gate
2-input NOR Gate
Logical effort of 2-input NAND and NOR gates
Logical Effort of Gates

2
=
p
3;
t pNAND

4/
5
Normalized delay (d)

=
g = 4/3 t pINV
p=

g
Normalized Delay

D:
p=2 1;

AN
d = (4/3)h+2
4 =
: g

tN
g=1 e r
ert

pu
3 v

in
p=1 In Effort

2-
d = h+1 Delay
2

F(Fan-in) 1
Intrinsic
1 2 3 4 5 6 7 Delay
Fan-out (h)
1 2 3 4 5
Fanout f
Multistage Networks Branching Effort
Example: Optimize Path

Assume we want to

– compute the propagation delay

– find the minimum propagation delay

– manually size the gates to achieve

minimum propagation delay

Example: Optimize Design (8-input AND)
Example: Optimize Design
Example: Optimize Design
How to size CMOS logic gates?
How to size CMOS logic gates?
Example: Sizing of NAND Gate
Example: Sizing of NOR Gate
Example: Sizing of INV Gate
Another Example
Another Example: Compute Key Quantities
Another Example: Calculate min. propagation delay
Another Example: Write dow the fan-outs
Another Example: Transistor Sizing
Another Example: Transistor Sizing
Another Example: Transistor Sizing
Another Example: Transistor Sizing
Example: Worst Case Delays
Example: Worst Case Delay-Falling
Example: Worst Case Delay-Falling
Example: Worst Case Delay-Falling