COMPUTER ORGANIZATION AND DESIGN 5th

Edition
The Hardware/Software Interface

Chapter 3
Arithmetic for Computers
 §3.1 Introduction
Arithmetic for Computers
 Operations on integers
 Addition and subtraction
 Multiplication and division
 Dealing with overflow
 Floating-point real numbers
 Representation and operations

Chapter 3 — Arithmetic for Computers — 2

 §3.2 Addition and Subtraction
Integer Addition
 Example: 7 + 6

 Overflow if result out of range

 Adding +ve and –ve operands, no overflow
 Adding two +ve operands
 Overflow if result sign is 1
 Adding two –ve operands
 Overflow if result sign is 0

Chapter 3 — Arithmetic for Computers — 3

Integer Subtraction
 Add negation of second operand
 Example: 7 – 6 = 7 + (–6)
+7: 0000 0000 … 0000 0111
–6: 1111 1111 … 1111 1010
+1: 0000 0000 … 0000 0001
 Overflow if result out of range
 Subtracting two +ve or two –ve operands, no overflow
 Subtracting +ve from –ve operand
 Overflow if result sign is 0
 Subtracting –ve from +ve operand
 Overflow if result sign is 1

Chapter 3 — Arithmetic for Computers — 4

Dealing with Overflow
 Some languages (e.g., C) ignore overflow
 Use MIPS addu, addui, subu instructions
 Other languages (e.g., Ada, Fortran)
require raising an exception
 Use MIPS add, addi, sub instructions
 On overflow, invoke exception handler
 Save PC in exception program counter (EPC)
register
 Jump to predefined handler address
 mfc0 (move from system control reg) instruction
can retrieve EPC value, to return after corrective
action
Chapter 3 — Arithmetic for Computers — 5
 §3.3 Multiplication
Multiplication
 Start with long-multiplication approach
multiplicand
1000
multiplier
× 1001
1000
0000
0000
1000
product 1001000

Length of product is
the sum of operand
lengths

Chapter 3 — Arithmetic for Computers — 6

Multiplication Hardware

Initially 0

Chapter 3 — Arithmetic for Computers — 7

Optimized Multiplier
 Perform steps in parallel: add/shift

 One cycle per partial-product addition

 That’s ok, if frequency of multiplications is low
Chapter 3 — Arithmetic for Computers — 8
Faster Multiplier
 Uses multiple adders
 Cost/performance tradeoff

 Following Figure is incomplete

 Can be pipelined
 Several multiplication performed in parallel
Chapter 3 — Arithmetic for Computers — 9
MIPS Multiplication
 Two 32-bit registers for product
 HI: most-significant 32 bits
 LO: least-significant 32-bits
 Instructions
 mult rs, rt / multu rs, rt
 64-bit product in HI/LO
 mfhi rd / mflo rd
 Move from HI/LO to rd
 Can test HI value to see if product overflows 32 bits
 mul rd, rs, rt
 Least-significant 32 bits of product –> rd

Chapter 3 — Arithmetic for Computers — 10

 §3.4 Division
Division
 Check for 0 divisor
 Long division approach
quotient  If divisor ≤ dividend bits
dividend  1 bit in quotient, subtract
1001  Otherwise
1000 1001010  0 bit in quotient, bring down next
-1000 dividend bit
divisor
10  Restoring division
101  Do the subtract, and if remainder
1010 goes < 0, add divisor back
-1000  Signed division
remainder 10
 Divide using absolute values
 Adjust sign of quotient and remainder
n-bit operands yield n-bit as required
quotient and remainder

Chapter 3 — Arithmetic for Computers — 11

Division Hardware
Initially divisor
in left half

Initially dividend

Chapter 3 — Arithmetic for Computers — 12

Division Example

Chapter 3 — Arithmetic for Computers — 13

Optimized Divider

 One cycle per partial-remainder subtraction

 Looks a lot like a multiplier!
 Same hardware can be used for both

Chapter 3 — Arithmetic for Computers — 14

Optimized Divider

Chapter 3 — Arithmetic for Computers — 15

Optimized Multiplier
Iteration Step Multiplicand Result / Multiplier
0 Init 0111 0000 0101
1 LSB =1, Add 0111 0111 0101
RS 0111 0011 1010
2 LSB =0, Pass 0111 0011 1010
RS 0111 0001 1101
3 LSB =1, Add 0111 1000 1101
RS 0111 0100 0110
4 LSB =0, Pass 0111 0100 0110
RS 0111 0010 0011

Chapter 3 — Arithmetic for Computers — 16

MIPS Division
 Use HI/LO registers for result
 HI: 32-bit remainder
 LO: 32-bit quotient
 Instructions
 div rs, rt / divu rs, rt
 No overflow or divide-by-0 checking
 Software must perform checks if required
 Use mfhi, mflo to access result
 Q in LO, R in HI

Chapter 3 — Arithmetic for Computers — 17

 §3.5 Floating Point
Floating Point
 Representation for non-integral numbers
 Including very small and very large numbers
 Like scientific notation
 –2.34 × 1056 normalized

 +0.002 × 10–4 not normalized

 +987.02 × 109
 In binary
 ±1.xxxxxxx2 × 2yyyy
 Types float and double in C
Chapter 3 — Arithmetic for Computers — 18
Floating Point Standard
 Defined by IEEE Std 754-1985
 Developed in response to divergence of
representations
 Portability issues for scientific code
 Now almost universally adopted
 Two representations
 Single precision (32-bit)
 Double precision (64-bit)

Chapter 3 — Arithmetic for Computers — 19

IEEE Floating-Point Format
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction

x  ( 1)S  (1 Fraction)  2(Exponent Bias)

 S: sign bit (0  non-negative, 1  negative)

 Normalize significand: 1.0 ≤ |significand| < 2.0
 Always has a leading pre-binary-point 1 bit, so no need to
represent it explicitly (hidden bit)
 Significand is Fraction with the “1.” restored
 Exponent: excess representation: actual exponent + Bias
 Ensures exponent is unsigned
 Single: Bias = 127; Double: Bias = 1203

Chapter 3 — Arithmetic for Computers — 20

Single-Precision Range
 Exponents 00000000 and 11111111 reserved
 Smallest value
 Exponent: 00000001
 actual exponent = 1 – 127 = –126
 Fraction: 000…00  significand = 1.0
 ±1.0 × 2–126 ≈ ±1.2 × 10–38
 Largest value
 exponent: 11111110
 actual exponent = 254 – 127 = +127
 Fraction: 111…11  significand ≈ 2.0
 ±2.0 × 2+127 ≈ ±3.4 × 10+38

Chapter 3 — Arithmetic for Computers — 21

Chapter 3 — Arithmetic for Computers — 22
Double-Precision Range
 Exponents 0000…00 and 1111…11 reserved
 Smallest value
 Exponent: 00000000001
 actual exponent = 1 – 1023 = –1022
 Fraction: 000…00  significand = 1.0
 ±1.0 × 2–1022 ≈ ±2.2 × 10–308
 Largest value
 Exponent: 11111111110
 actual exponent = 2046 – 1023 = +1023
 Fraction: 111…11  significand ≈ 2.0
 ±2.0 × 2+1023 ≈ ±1.8 × 10+308

Chapter 3 — Arithmetic for Computers — 23

Floating-Point Precision
 Relative precision
 all fraction bits are significant
 Single: approx 2–23
 A float has 23 bits of mantissa, and 2^23 is 8,388,608. 23 bits let
you store all 6 digit numbers or lower, and most of the 7 digit
numbers. This means that floating point numbers have between 6
and 7 digits of precision, regardless of exponent.
 Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal
digits of precision
 Double: approx 2–52
 Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal
digits of precision

Chapter 3 — Arithmetic for Computers — 24

Floating-Point Example
 Represent –0.75
 –0.75 = (–1)1 × 1.12 × 2–1
 S=1
 Fraction = 1000…002
 Exponent = –1 + Bias
 Single: –1 + 127 = 126 = 011111102
 Double: –1 + 1023 = 1022 = 011111111102
 Single: 1011111101000…00
 Double: 1011111111101000…00

Chapter 3 — Arithmetic for Computers — 25

Floating-Point Example
 What number is represented by the single-
precision float
11000000101000…00
 S=1
 Fraction = 01000…002
 Fxponent = 100000012 = 129
 x = (–1)1 × (1 + 012) × 2(129 – 127)
= (–1) × 1.25 × 22
= –5.0

Chapter 3 — Arithmetic for Computers — 26

Denormal Numbers

Chapter 3 — Arithmetic for Computers — 27

Denormal Numbers
 Exponent = 000...0  hidden bit is 0
Bias
x  ( 1)  (0  Fraction)  2
S

 Smaller than normal numbers

 allow for gradual underflow, with
diminishing precision

 Denormal with fraction = 000...0

Bias
x  ( 1)  (0  0)  2
S
 0.0
Two representations
of 0.0!

Chapter 3 — Arithmetic for Computers — 28

Infinities and NaNs
 Exponent = 111...1, Fraction = 000...0
 ±Infinity
 Can be used in subsequent calculations,
avoiding need for overflow check
 Exponent = 111...1, Fraction ≠ 000...0
 Not-a-Number (NaN)
 Indicates illegal or undefined result
 e.g., 0.0 / 0.0
 Can be used in subsequent calculations

Chapter 3 — Arithmetic for Computers — 29

Floating-Point Addition
 Consider a 4-digit decimal example
 9.999 × 101 + 1.610 × 10–1
 1. Align decimal points
 Shift number with smaller exponent
 9.999 × 101 + 0.016 × 101
 2. Add significands
 9.999 × 101 + 0.016 × 101 = 10.015 × 101
 3. Normalize result & check for over/underflow
 1.0015 × 102
 4. Round and renormalize if necessary
 1.002 × 102

Chapter 3 — Arithmetic for Computers — 30

Floating-Point Addition
 Now consider a 4-digit binary example
 1.0002 × 2–1 + –1.1102 × 2–2 (0.5 + –0.4375)
 1. Align binary points
 Shift number with smaller exponent
 1.0002 × 2–1 + –0.1112 × 2–1
 2. Add significands
 1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1
 3. Normalize result & check for over/underflow
 1.0002 × 2–4, with no over/underflow
 4. Round and renormalize if necessary
 1.0002 × 2–4 (no change) = 0.0625

Chapter 3 — Arithmetic for Computers — 31

FP Adder Hardware
 Much more complex than integer adder
 Doing it in one clock cycle would take too
long
 Much longer than integer operations
 Slower clock would penalize all instructions
 FP adder usually takes several cycles
 Can be pipelined

Chapter 3 — Arithmetic for Computers — 32

FP Adder Hardware

Step 1

Step 2

Step 3

Step 4

Chapter 3 — Arithmetic for Computers — 33

Rounding Bits
 Guard and round digits, and sticky bit
 When computing result, assume there are several extra
digits available for shifting and computation. This
improves accuracy of computation.
 Guard digit: first extra digit/bit to the right of mantissa --
used for rounding addition results
 Round digit: second extra digit/bit to the right of mantissa
-- used for rounding multiplication results
 Sticky bit: third extra digit/bit to the right of mantissa –
used for resolving ties such as 0.50...00 vs. 0.50...01
Rounding Bits
 Rounding using Guard and round digits,
and sticky bit
G R S Action
0 0 0 Truncate
0 0 1 Truncate 1.100GRS
0 1 0 Truncate
1.10001 = 1.53125
0 1 1 Truncate 1.10010 = 1.56250
1 0 0 Round to Even 1.10011 = 1.59375
1 0 1 Round Up
1 1 0 Round Up
1 1 1 Round Up
Floating-Point Multiplication
 Consider a 4-digit decimal example
 1.110 × 1010 × 9.200 × 10–5
 1. Add exponents
 For biased exponents, subtract bias from sum
 New exponent = 10 + –5 = 5
 2. Multiply significands
 1.110 × 9.200 = 10.212  10.212 × 105
 3. Normalize result & check for over/underflow
 1.0212 × 106
 4. Round and renormalize if necessary
 1.021 × 106
 5. Determine sign of result from signs of operands
 +1.021 × 106

Chapter 3 — Arithmetic for Computers — 36

Floating-Point Multiplication
 Now consider a 4-digit binary example
 1.0002 × 2–1 × –1.1102 × 2–2 (0.5 × –0.4375)
 1. Add exponents
 Unbiased: –1 + –2 = –3
 Biased: (–1 + 127) + (–2 + 127) = –3 + 254 – 127 = –3 + 127
 2. Multiply significands
 1.0002 × 1.1102 = 1.1102  1.1102 × 2–3
 3. Normalize result & check for over/underflow
 1.1102 × 2–3 (no change) with no over/underflow
 4. Round and renormalize if necessary
 1.1102 × 2–3 (no change)
 5. Determine sign: +ve × –ve  –ve
 –1.1102 × 2–3 = –0.21875

Chapter 3 — Arithmetic for Computers — 37

FP Arithmetic Hardware
 FP multiplier is of similar complexity to FP
adder
 But uses a multiplier for significands instead of
an adder
 FP arithmetic hardware usually does
 Addition, subtraction, multiplication, division,
reciprocal, square-root
 FP  integer conversion
 Operations usually takes several cycles
 Can be pipelined

Chapter 3 — Arithmetic for Computers — 38

Associativity of FP Addition
 Associativity: a+(b+c) = (a+b) + c
 Is FP addition associative?
 No
FP Instructions in MIPS
 FP hardware is coprocessor 1
 Adjunct processor that extends the ISA
 Separate FP registers
 32 single-precision: $f0, $f1, … $f31
 Paired for double-precision: $f0/$f1, $f2/$f3, …
 Release 2 of MIPs ISA supports 32 × 64-bit FP reg’s
 FP instructions operate only on FP registers
 Programs generally don’t do integer ops on FP data,
or vice versa
 More registers with minimal code-size impact
 FP load and store instructions
 lwc1, ldc1, swc1, sdc1
 e.g., ldc1 $f8, 32($sp)

Chapter 3 — Arithmetic for Computers — 40

Chapter 3 — Arithmetic for Computers — 41
FP Instructions in MIPS
 Single-precision arithmetic
 add.s, sub.s, mul.s, div.s
 e.g., add.s $f0, $f1, $f6
 Double-precision arithmetic
 add.d, sub.d, mul.d, div.d
 e.g., mul.d $f4, $f4, $f6
 Single- and double-precision comparison
 c.xx.s, c.xx.d (xx is eq, lt, le, …)
 Sets or clears FP condition-code bit
 e.g. c.lt.s $f3, $f4
 Branch on FP condition code true or false
 bc1t, bc1f
 e.g., bc1t TargetLabel

Chapter 3 — Arithmetic for Computers — 42

Single and Double Precision operations
 A double precision register is really an
even-odd pair of single precision registers,
using the even register number as its
name.

 What if add.d was used?

 Floating-Point Instructions in MIPS

 Floating-point addition, single (add.s) and addition, double

(add.d)
 e.g., add.s $f0, $f4, $f6 # $f2 = $f4 + $f6
 Floating-point subtraction, single (sub.s) and subtraction,
double (sub.d)
 e.g., sub.d $f2, $f4, $f6 # $f2 = $f4 - $f6
 Floating-point multiplication, single (mul.s) and
multiplication, double (mul.d)
 e.g., mul.s $f2, $f4, $f6 # $f2 = $f4 X $f6
 Floating-point division, single (div.s) and division, double
(div.d)
 e.g., div.d $f2, $f4, $f6 # $f2 = $f4 / $f6
Floating-Point Instructions in MIPS
 Floating-point comparison, single (c.x.s) and comparison,
double (c.x.d),
where x may be equal (eq), not equal (neq), less than
(lt), less than or equal
(le), greater than (gt), or greater than or equal (ge)
 e.g., c.lt.s $f2, $f4 # if ($f2 < $f4) cond = 1; else
cond = 0
 Floating-point branch, true (bc1t) and branch, false (bc1f)
 e.g., bclt 25 # if (cond == 1) go to PC + 4 + 100
Floating-Point Instructions in MIPS

if (i==j)
f = g + h;
else
f = g – h;
MIPS FP Operands
MIPS FP Operations
MIPS FP Instruction Format
FP Example: °F to °C
 C code:
float f2c (float fahr) {
return ((5.0/9.0)*(fahr - 32.0));
}
 fahr in $f12, result in $f0, literals in global memory
space
 Compiled MIPS code:
f2c: lwc1 $f16, const5($gp)
lwc2 $f18, const9($gp)
div.s $f16, $f16, $f18
lwc1 $f18, const32($gp)
sub.s $f18, $f12, $f18
mul.s $f0, $f16, $f18
jr $ra
Chapter 3 — Arithmetic for Computers — 50
Accurate Arithmetic
 IEEE Std 754 specifies additional rounding
control
 Extra bits of precision (guard, round, sticky)
 Choice of rounding modes
 Allows programmer to fine-tune numerical behavior of
a computation
 Not all FP units implement all options
 Most programming languages and FP libraries just
use defaults
 Trade-off between hardware complexity,
performance, and market requirements

Chapter 3 — Arithmetic for Computers — 51

 §3.9 Concluding Remarks
Concluding Remarks
 Bits have no inherent meaning
 Interpretation depends on the instructions
applied
 Computer representations of numbers
 Finite range and precision
 Need to account for this in programs

Chapter 3 — Arithmetic for Computers — 52

Concluding Remarks
 ISAs support arithmetic
 Signed and unsigned integers
 Floating-point approximation to reals
 Bounded range and precision
 Operations can overflow and underflow
 MIPS ISA
 Core instructions: 54 most frequently used
 100% of SPECINT, 97% of SPECFP
 Other instructions: less frequent

Chapter 3 — Arithmetic for Computers — 53