Multiplication Example

Multiplicand 1000ten
Multiplier x 1001ten
---------------
1000
0000
0000
1000
----------------
Product 1001000ten

In every step
• multiplicand is shifted
• next bit of multiplier is examined (also a shifting step)
• if this bit is 1, shifted multiplicand is added to the product
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HW Algorithm 1
initially left half is zeros and right half is non zero,
shifted to the left 64 times (and hence needs a 128 bit register)

shifted to the right in every

step, to get the least sig bit
every time.

adds the shifted

multiplicand

decides whether to add the shifted multiplicand or not

Source: H&P textbook

In every step
• multiplicand is shifted
• next bit of multiplier is examined (also a shifting step)
• if this bit is 1, shifted multiplicand is added to the product
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 the 64 bit register is actually 64+1 (to handle the case
HW Algorithm 2 of overflow as an extra space for the carry out bit)

same 64 bit register for both multiplier and product,

the register is shifted right. we can get the lsb of the
register and if it is 1, then add it to the last 32 bit of
the register using ALU. finally the 64 bit register will
take the value of the product entirely after 32 iterations

left half is product (initially zeros),

right half is multiplier

Source: H&P textbook

• 32-bit ALU and multiplicand is untouched

• the sum keeps shifting right
• at every step, number of bits in product + multiplier = 64,
hence, they share a single 64-bit register
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Notes

• The previous algorithm also works for signed numbers

(negative numbers in 2’s complement form)

• We can also convert negative numbers to positive, multiply

the magnitudes, and convert to negative if signs disagree

• The product of two 32-bit numbers can be a 64-bit number

-- hence, in MIPS, the product is saved in two 32-bit
registers

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MIPS Instructions

mult $s2, $s3 computes the product and stores

it in two “internal” registers that
can be referred to as hi and lo

mfhi $s0 moves the value in hi into $s0

mflo $s1 moves the value in lo into $s1

Similarly for multu

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Fast Algorithm

• The previous algorithm

requires a clock to ensure that
the earlier addition has
completed before shifting

• This algorithm can quickly set

up most inputs – it then has to
wait for the result of each add
to propagate down – faster
because no clock is involved

-- Note: high transistor cost

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Source: H&P textbook
Division

1001ten Quotient
Divisor 1000ten | 1001010ten Dividend
-1000
10
101
1010
-1000
10ten Remainder

At every step,
• shift divisor right and compare it with current dividend
• if divisor is larger, shift 0 as the next bit of the quotient
• if divisor is smaller, subtract to get new dividend and shift 1
as the next bit of the quotient 8
 Division

1001ten Quotient
Divisor 1000ten | 1001010ten Dividend

0001001010 0001001010 0000001010 0000001010

100000000000  0001000000 00001000000000001000
Quo: 0 000001 0000010 000001001

At every step,
• shift divisor right and compare it with current dividend
• if divisor is larger, shift 0 as the next bit of the quotient
• if divisor is smaller, subtract to get new dividend and shift 1
as the next bit of the quotient 9
Divide Example
• Divide 7ten (0000 0111two) by 2ten (0010two)

Iter Step Quot Divisor Remainder

0 Initial values
1

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 IMPORTANT PAGE
Divide Example
• Divide 7ten (0000 0111two) by 2ten (0010two)
Iter Step Quot Divisor Remainder
0 Initial values 0000 0010 0000 0000 0111
1 Rem = Rem – Div 0000 0010 0000 1110 0111
Rem < 0  +Div, shift 0 into Q 0000 0010 0000 0000 0111
Shift Div right 0000 0001 0000 0000 0111
2 Same steps as 1 0000 0001 0000 1111 0111
0000 0001 0000 0000 0111
0000 0000 1000 0000 0111
3 Same steps as 1 0000 0000 0100 0000 0111
4 Rem = Rem – Div 0000 0000 0100 0000 0011
Rem >= 0  shift 1 into Q 0001 0000 0100 0000 0011
Shift Div right 0001 0000 0010 0000 0011
5 Same steps as 4 0011 0000 0001 0000 0001
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divisor is shifted left initially until its 64 bit. in each step we subtract it from remainder. if remainder becomes negative, we add it back
and add 0 in the end of the divisor, else we add 1 in the end of the divisor. after each step we shift the divisor by 1.

Hardware for Division

Source: H&P textbook

A comparison requires a subtract; the sign of the result is

examined; if the result is negative, the divisor must be added back

Similar to multiply, results are placed in Hi (remainder) and Lo (quotient)

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 learn this, i dont fully understand this
Efficient Division

left side contains remainder (initially set equal to the 64 bit dividend)
right side contains the quotient (initially set to zeros) in the 64+1 bit register
last 32 bits compared, if smaller then subtract from last 33 bits, put just 1, or 01
accordingly in lsb of the register (because remainder has given up one bit)

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Source: H&P textbook
Divisions Involving Negatives

• Simplest solution: convert to positive and adjust sign later

• Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Remainder

+7 div +2 Quo = Rem =

-7 div +2 Quo = Rem =
+7 div -2 Quo = Rem =
-7 div -2 Quo = Rem =

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Divisions involving Negatives

• Simplest solution: convert to positive and adjust sign later

• Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Remainder

+7 div +2 Quo = +3 Rem = +1

-7 div +2 Quo = -3 Rem = -1
+7 div -2 Quo = -3 Rem = +1
-7 div -2 Quo = +3 Rem = -1

Convention: Dividend and remainder have the same sign

Quotient is negative if signs disagree
These rules fulfil the equation above

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