Department of Electrical and Computer Engineering

Pak-Austria Fachhochschule: Institute of Applied Sciences and

Technology, Haripur, Pakistan

Course Title Advanced FPGA-based System Design

Course Code: ECE-863 Semester: Spring 2025
Credit Hours: 3 Prerequisite(s): Digital Logic Design
Instructor: Dr. Zahid Ullah Class: MS Embedded Systems and IoTs
Office: A2-206 E-mail: [email protected]
Lecture Day(s): Thursday and Saturday Consultation Appointment may be taken through email
Hours:
Classroom: A2-210 Knowledge Group: Embedded Systems and IoTs

Course Description:
HDL (hardware description language) and FPGA (field-programmable gate array) allow designers to quickly
develop and simulate a digital circuit, realize it on a prototyping device, and verify operation of the physical
implementation. An FPGA is an integrated circuit which is configurable after manufacturing. FPGAs can be used
to implement any logic function and have become a major implementation technology for digital systems because
of several reasons such as its reconfigurability, massive hardware parallelism, high clock rate, and rapid
prototyping capability. HDLs are used for modeling digital systems. Verilog HDL will be used in this course for
describing digital systems. Basic building blocks of FPGA programming, design methodologies, best design
practices, and optimization techniques for performance (speed, latency, area, power) will be discussed. Digital
systems will be verified through testbenches.
Course Objectives:
This course will advance the student's understanding of Verilog HDL and FPGA design flow. Students would be
able to design digital systems, verify them, and optimize them in terms of performance evaluation metrics.

Recommended Books
1. Advanced digital design with the Verilog HDL / Michael D. Ciletti. 2nd Edition, 2017, Prentice Hall Xilinx
Design Series
2. M. Morris R. Mano, Michael D. Ciletti, “Digital Design: With an Introduction to the Verilog HDL”, 6th edition,
Pearson, 2018
3. FPGA Prototyping by Verilog Examples/ Pong P. Chu. 1st Edition, Xilinx Spartan-3 Version

Topics
Week 1 Introduction to FPGA based system designing: FPGA introduction, FPGA usage and applications,
introduction to FPGA Programming and digital design methodology, installation of the CAD tools for the
FPGA-based design.
Week 2 Review of combinational and sequential logic design.
Week 3 Introduction to digital design using Verilog HDL, Basics Concepts in Verilog HDL, Verilog Module,
Common abstraction levels in Verilog HDL, installation of the CAD tools for the FPGA-based design.
Week 4 Coding in Verilog HDL, demonstration from the CAD tool: Verilog HDL file for design and testbench,
synthesis, place & route, resources consumed on FPGA, reports of synthesis and place & route for
combinational circuits.
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 Department of Electrical and Computer Engineering
Pak-Austria Fachhochschule: Institute of Applied Sciences and
Technology, Haripur, Pakistan

Week 5 Behavioral modelling for combinational circuits, RTL level combinational circuits: Data flow modelling in
Verilog HDL, continuous assignment, expressions, operators and operands, operator types.
Week 6 Sequential Circuits: Introduction, Synchronous system, Code Development, HDL Code of FF and register,
Design Examples, Testbench for Sequential Circuits, loops in Verilog HDL.
Week 7 Architecture of FPGA, components such as RAMs, LUTs, CLBs, etc. on FPGA, ASIC (application-specific
integrated circuit), FPGAs’ providers, Xilinx FPGAs
Week 8 Design examples of various combinational and sequential circuits, their implementation, and verification
using the CAD tools.
Mid-semester Examination
Week 9 Block RAM and its types, Distributed RAM, Developing Verilog modules for block RAM and Distributed
RAM along with their testbenches.
Week 10 Initialize memory (all types of Block RAM and Distributed RAM) from a file, how to write to a file?
Testbenches to read data from initialized RAMs.
Week 11 Design of a Control Unit of Digital Circuits: Introduction, Mealy and Moore Outputs, FSM Representation,
FSM code development, Sequential Machine Design Examples.
Week 12 Demonstration from the CAD tools: generation of SAIF file, estimation of dynamic power consumption by
Xilinx Power Analyzer, setting different parameters for estimating dynamic power consumption, synthesis,
place & route, resources consumed on FPGA, reports of synthesis and place & route, and max. operating
speed, optimization for throughput, latency, and area for digital systems.
Week 13 Types of CAM cells, some low power CAMs: selective pre-charging, pre-computation-based CAM, bank
selection, content-addressable RAM (CA-RAM), associative RAM-based CAM (AR-CAM), memory and
power efficient mechanism for fast table lookup, circuit to generate an sequential index for an input number.
Implementation of selected architectures on FPGA and analyzing different performance evaluation metrics
Week 14 Design of a complex digital system: Students need to implement it on different Xilinx FPGAs and answer
the following questions.
1. How many SR?
2. How many LUTs?
3. How many BRAMs? How many 36K and how many 18K?
4. How many multiplexers?
5. How many comparators?
6. How many adders?
7. How many clock cycles (latency)?
8. What is the speed of the design?
9. What about power consumption for a single search operation?

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 Department of Electrical and Computer Engineering
Pak-Austria Fachhochschule: Institute of Applied Sciences and
Technology, Haripur, Pakistan

10. Any timing errors?

11. How can you increase the speed of the design?
12. Can you decrease the latency of the design? If yes, which other parameter (s) will be
compromised?
Week 15 Xilinx core generator, report submission (by all students), presentations, and demonstrations of the
semester projects.
Week 16 Presentations and demonstrations of the semester projects.
Week 17 Final Examination

Assessment Plan
Assessment Weightage (%)
Projects report, demonstration and presentation 5 + 5 + 5 = 15
Assignments (3) 10
Quizzes (3) 10
Mid-Semester Examination 25
Final Examination 40

Tools / Software Requirement:

Xilinx ISE Design Suite, Xilinx Vivado

Grading Policy:

Semester project: Students are required to undertake a semester project relevant to the subject, write a
report, demonstrate and present it.

Assignments: Three assignments will be given.

Quizzes Three quizzes will be taken.
Mid-semester Examination: Mid-semester examination will be held in 8th week of the semester.

Final Examination: Final examination will be held in the 17th week and will cover the entire course.
Plagiarism: Collaboration and group work are encouraged but each student is required to submit
his/her own contribution(s). Your writing must be your own thoughts. You must cite
and acknowledge all sources of information. Cheating and plagiarism will not be
tolerated and will lead to strict penalties including zero marks as well as referral to the
HoD for appropriate action(s).

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