OOPs PART-1 VIKRAM RENESAS

Table of Contents
1. Class
2. Handle
3. Object
4. Property
5. Method
6. Prototype
7. Static, Local, and Global Variables
8. Shallow Copy and Deep Copy
9. Static Methods
10. Inheritance
11. Super Keyword
12. This Keyword
13. Polymorphism
14. Casting
15. Abstract Class
16. Extern Keyword

Object-Oriented Programming in SystemVerilog

In SystemVerilog, Object-Oriented Programming (OOP) concepts are supported, allowing you to

create reusable and modular code. Below is an explanation of the key OOP terminology in
SystemVerilog.

1. Class

A class is a blueprint or template for creating objects. It defines the properties (data members) and
methods (functions/tasks) that the objects of the class will have.

2. Handle

A handle is a reference to an object of a class. It is similar to a pointer in other programming

languages. You use a handle to access the properties and methods of an object.

3. Object

An object is an instance of a class. It is created dynamically using the new() method. Each object has its
own set of properties and can call the methods defined in the class.

4. Property

A property is a data member of a class. It holds the state or attributes of an object. Properties can be
of any data type, such as int, string, or even another class.
 OOPs PART-1 VIKRAM RENESAS

5. Method

A method is a function or task defined within a class. It defines the behavior or actions that an object
can perform.

6. Prototype

A prototype is a declaration of a method (function or task) within a class. It specifies the method's
name, return type (if any), and arguments (if any). The actual implementation of the method is defined
later.

Static, Local, and Global Variables

In SystemVerilog, static, local, and global variables have specific scoping and lifetime rules.

1. Static Variable

 A static variable retains its value between function/task calls.

 It is initialized only once and persists throughout the simulation.
 Declared using the static keyword.

2. Local Variable

 A local variable is declared inside a function or task.

 It is created when the function/task is called and destroyed when the function/task exits.
 Declared without any special keyword.

3. Global Variable

 A global variable is declared outside any function, task, or class.

 It is accessible throughout the entire module or program.
 Declared at the module or program level.

Shallow Copy and Deep Copy

In SystemVerilog, shallow copy and deep copy are two ways to copy objects. The key difference lies
in how they handle nested objects or dynamic data within the object being copied.

Shallow Copy

 A shallow copy creates a new object and copies all the fields of the original object.
 If the object contains references to other objects, the references are copied, but the
referenced objects themselves are not duplicated.
 Both the original and the copied object will share the same nested objects.
 OOPs PART-1 VIKRAM RENESAS

Deep Copy

 A deep copy creates a new object and recursively copies all the fields of the original object,
including any nested objects.
 If the object contains references to other objects, new instances of those objects are created,
and their contents are copied.
 The original and the copied object will have independent copies of nested objects.

Static Methods

In SystemVerilog, a static method is a method that belongs to a class itself, rather than to an instance
of the class. This means that the method can be called without creating an object of the class.

Characteristics of Static Methods:

1. No Access to Instance Variables: Static methods do not have access to instance-specific

variables (non-static fields) or this. They can only access static fields and other static methods.
2. Called Using Class Name: Static methods are typically called using the class name, not an
instance of the class.
3. Used for Utility Functions: Static methods are ideal for utility functions or operations that
don't need object state, such as mathematical calculations or managing static data shared
among all instances of the class.

Inheritance

In SystemVerilog, inheritance is a key feature of Object-Oriented Programming (OOP) that allows you
to create a new class (called the derived class or subclass) based on an existing class (called the base
class or superclass). The derived class inherits all the properties and methods of the base class and
can also add new properties and methods or override existing ones.

Key Concepts of Inheritance:

1. Base Class (Superclass): The original class from which properties and methods are inherited.
2. Derived Class (Subclass): The new class that inherits from the base class.
3. extends Keyword: Used to specify that a class inherits from another class.
4. super Keyword: Used to refer to the base class from within the derived class.

Polymorphism

Polymorphism is one of the core concepts of Object-Oriented Programming (OOP), and it allows for
the ability to use a single interface to represent different types of objects. In SystemVerilog,
polymorphism is primarily used with classes, and it enables you to write more flexible and reusable
code by allowing objects of different classes to be treated through a common interface.
 OOPs PART-1 VIKRAM RENESAS

Key Concepts of Polymorphism:

1. Base Class and Derived Classes: A base class defines a common interface (methods and
properties). Derived classes inherit from the base class and can override its methods to
provide specific implementations.
2. Virtual Methods: Methods in the base class must be declared as virtual to allow overriding in
derived classes.
3. Dynamic Method Dispatch: The actual method to be called is determined at runtime based
on the type of the object, not the type of the handle.

Casting

Dynamic Casting

 Dynamic casting is used to safely cast a super-class pointer (reference) into a subclass pointer
(reference) in a class hierarchy.
 Dynamic casting will be checked during runtime, and an attempt to cast an object to an
incompatible object will result in a runtime error.
 Dynamic casting is done using the $cast(destination, source) method.

Abstract Class

SystemVerilog prohibits a class declared as virtual to be directly instantiated and is called an abstract
class.

Pure Virtual Method

 A virtual method inside an abstract class can be declared with the keyword pure and is called
a pure virtual method.
 Such methods only require a prototype to be specified within the abstract class, and the
implementation is left to be defined within the sub-classes.

Extern Keyword

The extern keyword is used to declare methods that are defined outside the class body. This allows
for separation of method declaration and implementation.

This document provides a comprehensive overview of Object-Oriented Programming concepts in

SystemVerilog, including classes, handles, objects, methods, inheritance, polymorphism, and more.
 OOPs PART-1 VIKRAM RENESAS

Object-Oriented Programming (OOP)

Concepts are supported, allowing you to create reusable and modular code. Below is an explanation
of the key OOP terminology in SystemVerilog

1. Class

A class is a blueprint or template for creating objects. It defines the properties (data members) and
methods (functions/tasks) that the objects of the class will have.

2. Handle

A handle is a reference to an object of a class. It is similar to a pointer in other programming

languages. You use a handle to access the properties and methods of an object.

3. Object

An object is an instance of a class. It is created dynamically using the new() method. Each object has its
own set of properties and can call the methods defined in the class.

4. Property

A property is a data member of a class. It holds the state or attributes of an object. Properties can be
of any data type, such as int, string, or even another class.
 OOPs PART-1 VIKRAM RENESAS

5. Method

A method is a function or task defined within a class. It defines the behavior or actions that an object
can perform.

6. Prototype

A prototype is a declaration of a method (function or task) within a class. It specifies the method's
name, return type (if any), and arguments (if any). The actual implementation of the method is defined
later.
 OOPs PART-1 VIKRAM RENESAS

Complete code:

../simv up to date
CPU time: .460 seconds to compile + .382 seconds to elab + .390 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 10:23 2025

------------------------------->
Name: Dog, Age: 5

------------------------------->
V C S S i m u l a t i o n R e p o r t
 OOPs PART-1 VIKRAM RENESAS

Feature new() new[]

Creates a dynamic
Creates a single object array of objects of a
Purpose of a class. class.
Used when you want to Used when you want to
instantiate a single create a dynamic array
Usage object. of objects.
ClassName arr[size] =
Syntax ClassName obj = new(); new[size];

An array of instances of
a class with a specified
Creates One instance of a class. size.
MyClass arr[10] =
Example MyClass obj = new(); new[10];
Memory Allocates memory for a Allocates memory for
Allocation single object. an array of objects.
Allows dynamic size for
the array (can specify
Not applicable (single the number of
Dynamic Size object). elements).
Can pass arguments to
Can pass arguments to the constructor of each
the constructor of the object in the array (or
Arguments class. to the array itself).
MyClass obj = new(5); `MyClass arrct in the
Argument (if the constructor array needs an
Example takes an argument) argument)

Feature time realtime

realtime is a built-in
Type time is a built-in type. type.
64-bit unsigned 64-bit signed floating-
Precision integer. point number.
Maximum value of time Can represent both
is 2^64 - 1 (for positive and negative
Range unsigned integer). values.
 OOPs PART-1 VIKRAM RENESAS

Used to represent Used for real-time

simulation time in calculations or time
clock cycles or as a intervals (e.g., in
Use Case counter. seconds).
Typically represents Represents real time in
Unit of time in simulation seconds (floating
Measurement cycles. point).
Can represent
Limited by simulation fractional seconds (e.g.,
Resolution time resolution. 1.5, 0.0001).

time t = 100;
(Represents 100 time realtime rt = 0.01;
units in simulation (Represents 10
Example cycles). milliseconds).
Supports arithmetic
with fractions (e.g., 5.5
Cannot support
Arithmetic fractional values. or 0.1).
Can be converted
to/from real and int but Can be used in
not directly to/from expressions with
Conversion time. floating-point numbers.

Null –object de-allocation

In SystemVerilog, setting an object reference to null is often used in conjunction with
deallocation, but it does not actually deallocate the memory itself. Instead, setting an object
reference to null simply makes the object reference invalid and removes the reference to the
object, which means you can no longer access the object through that reference.

The actual deallocation of memory is done using the delete operator. Setting an object to
null just nullifies the reference and marks it as no longer pointing to the object. The object
itself will be deallocated only if there are no other references to it and the delete operator
is used.
 OOPs PART-1 VIKRAM RENESAS

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 10:38 2025

------------------------------>
Object value: 10
------------------------------>

Error-[NOA] Null object access

testbench.sv, 24
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.

#0 in test at testbench.sv:24
#1 in test

V C S S i m u l a t i o n R e p o r t
 OOPs PART-1 VIKRAM RENESAS

STATIC LOCAL AND GLOBAL

In SystemVerilog, static, local, and global variables have specific scoping and lifetime rules. Below is
an example that demonstrates the use of static, local, and global variables in SystemVerilog.

1. Static Variable:
o A static variable retains its value between function/task calls.
o It is initialized only once and persists throughout the simulation.
o Declared using the static keyword.
2. Local Variable:
o A local variable is declared inside a function or task.
o It is created when the function/task is called and destroyed when the function/task
exits.
o Declared without any special keyword.
3. Global Variable:
o A global variable is declared outside any function, task, or class.
o It is accessible throughout the entire module or program.
o Declared at the module or program level.

EXAMPLE:

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 12:25 2025
Static Var: 1, Local Var: 1, Global Var: 1
Static Var: 2, Local Var: 1, Global Var: 2
Static Var: 3, Local Var: 1, Global Var: 3
V C S S i m u l a t i o n R e p o r t
 OOPs PART-1 VIKRAM RENESAS

Explanation of the Code

1. Global Variable (global_var):

o Declared outside the task, so it is accessible throughout the module.
o Retains its value throughout the simulation.
2. Static Variable (static_var):
o Declared inside the task with the static keyword.
o Retains its value between task calls.
3. Local Variable (local_var):
o Declared inside the task without any special keyword.
o Reinitialized to 0 every time the task is called.

When to Use Each

 Use static variables when you need to retain values between function/task calls.
 Use local variables for temporary storage within a function/task.
 Use global variables for data that needs to be shared across multiple functions/tasks or
throughout the module.

EXAMPLE 2:
 OOPs PART-1 VIKRAM RENESAS
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 12:30 2025
Object 1:
Static Var: 1, Non-Static Var: 1
Static Var: 2, Non-Static Var: 2

Object 2:
Static Var: 3, Non-Static Var: 1
Static Var: 4, Non-Static Var: 2
V C S S i m u l a t i o n R e p o r t

PROTECTED KEYWORD
The protected keyword is used to specify that a class member (variable or method) can be
accessed within the class itself and by derived (child) classes. However, it cannot be
accessed from outside the class hierarchy, i.e., it is not accessible by instances of the class or
non-derived classes.

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:47 2025
Protected Data: 100
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.460 seconds; Data structure size: 0.0Mb

Keyword Scope Access Control

Only accessible within the block or

Limited to the block or function where it function it is declared in. Cannot be
is declared (e.g., within an initial block accessed outside the scope of that
local or a function). block or function.

Accessible only by the class that

Accessible within the current class and declares it and any subclasses
its derived (child) classes, but not (derived classes), not by outside
protected outside of the class hierarchy. classes or modules.
 OOPs PART-1 VIKRAM RENESAS

Accessible anywhere within the scope of Accessible from anywhere within the
the module, class, or program in which it module, class, or program where it is
global is declared. declared.

SHALLOW COPY AND DEEP COPY

In SystemVerilog, shallow copy and deep copy are two ways to copy objects. The key difference lies
in how they handle nested objects or dynamic data within the object being copied.

Shallow Copy

 A shallow copy creates a new object and copies all the fields of the original object.
 If the object contains references to other objects (e.g., handles to class objects), the references
are copied, but the referenced objects themselves are not duplicated.
 Both the original and the copied object will share the same nested objects.

Deep Copy

 A deep copy creates a new object and recursively copies all the fields of the original object,
including any nested objects.
 If the object contains references to other objects, new instances of those objects are created,
and their contents are copied.
 The original and the copied object will have independent copies of nested objects.

Aspect Shallow Copy Deep Copy

Copies the object, its fields, and

Copies the object and its fields, but not recursively copies all nested
Definition the objects referenced by its fields. objects.
 OOPs PART-1 VIKRAM RENESAS

New instances of nested objects

References to nested objects are shared are created, and their contents
Nested Objects between the original and copied object. are copied.

Less memory is used because nested More memory is used because

Memory Usage objects are not duplicated. nested objects are duplicated.

Faster because it does not recursively Slower because it recursively

Performance copy nested objects. copies nested objects.

Suitable when nested objects are Suitable when nested objects

Use Case immutable or shared intentionally. need to be independent.

STATIC

In SystemVerilog, a static method is a method that belongs to a class itself, rather than to an
instance of the class. This means that the method can be called without creating an object of
the class, which is particularly useful when you need to perform a task that does not depend
on any instance-specific data.

Characteristics of Static Methods in SystemVerilog:

1. No Access to Instance Variables: Static methods do not have access to instance-

specific variables (non-static fields) or this. They can only access static fields and
other static methods.
2. Called Using Class Name: Static methods are typically called using the class name,
not an instance of the class.
3. Used for Utility Functions: Static methods are ideal for utility functions or
operations that don't need object state, such as mathematical calculations or managing
static data shared among all instances of the class.
 OOPs PART-1 VIKRAM RENESAS

Syntax to Define a Static Method:

To define a static method, you use the static keyword before the function or task
keyword.

EXAMPLE FOR STATIC METHOD

RESULT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 04:16 2025

-------------------->
Counter incremented: 3
-------------------->

-------------------->
Counter incremented: 4
-------------------->

-------------------->
Current counter value (static): 4
Current counter2 value (non-static): 1
-------------------->
-------------------->
Current counter value (static): 4
Current counter2 value (non-static): 5
-------------------->
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.420 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

Note : you can’t call non static member in static method

ERROR:
Error-[SV-AMC] Non-static member access
testbench.sv, 13
$unit, "counter2"
Illegal access of non-static member 'counter2' from static method
'MyClass::increment_counter'.
 OOPs PART-1 VIKRAM RENESAS

INHERETANCE
In SystemVerilog, inheritance is a key feature of Object-Oriented Programming (OOP) that allows you
to create a new class (called the derived class or subclass) based on an existing class (called the base
class or superclass). The derived class inherits all the properties and methods of the base class and
can also add new properties and methods or override existing ones.

Key Concepts of Inheritance

1. Base Class (Superclass):

o The original class from which properties and methods are inherited.
2. Derived Class (Subclass):
o The new class that inherits from the base class.
o Can add new properties and methods.
o Can override methods from the base class.
3. extends Keyword:
o Used to specify that a class inherits from another class.
4. super Keyword:
o Used to refer to the base class from within the derived class.
o Commonly used to call the base class constructor or access base class methods.
 OOPs PART-1 VIKRAM RENESAS

EXAMPLE 1:

RESULT:
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 12:51 2025

===========================>>>>>>>>>>>>
Value of addr = 10 data = 20
===========================>>>>>>>>>>>>

V C S S i m u l a t i o n R e p o r t

parent_class is a class that has one member variable:

 addr is a 32-bit wide bit (which is similar to a reg in Verilog but more suited for use
in classes). This variable is intended to hold an address.

child_class is another class, which extends the parent_class, meaning it inherits all the
properties and behaviors of parent_class.

 In addition to the addr variable inherited from the parent_class, child_class

defines its own member:
o data is another 32-bit wide bit variable.

The initial block is used for initialization in simulation. It runs once at the start of the
simulation.

 child_class c = new();: This creates an object c of type child_class using the

new() constructor. This object will have both the addr (from the parent) and data
(from the child) properties.
 c.addr = 10;: Sets the addr member of the object c to 10.
 c.data = 20;: Sets the data member of the object c to 20.
 $display(...): This is a SystemVerilog task that displays the output to the console.
 OOPs PART-1 VIKRAM RENESAS

o The first $display adds some formatting (a divider line).

o The second $display prints the values of c.addr and c.data (i.e., 10 and
20).
o The third $display adds another divider line.

SUPER KEYWORD

In SystemVerilog, the super keyword is used in the context of inheritance to refer to the base class
(superclass) from within a derived class (subclass). It is primarily used for two purposes:

1. Calling the Base Class Constructor:

o When a derived class is instantiated, the base class constructor must be called to
initialize the inherited properties.
o The super keyword is used to explicitly call the base class constructor from the derived
class constructor.
2. Accessing Base Class Methods:
o If a derived class overrides a method from the base class, the super keyword can be
used to call the base class version of the method from within the derived class.

Chronologic VCS simulator copyright 1991-2023

Contains Synopsys proprietary information.
 OOPs PART-1 VIKRAM RENESAS
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:04 2025

===========================>>>>>>>>>>>>
THIS IS PARENT CLASS
Value of addr = 10 data = 20
===========================>>>>>>>>>>>>

V C S S i m u l a t i o n R e p o r t

EXAMPLE3

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:07 2025

===========================>>>>>>>>>>>>
THIS IS CHILD CLASS
THIS IS PARENT CLASS
Value of addr = 10 data = 20
===========================>>>>>>>>>>>>

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.380 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

EXAMPLE 4

RESULT:
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:19 2025

===========================>>>>>>>>>>>>
Value CHILD variable N = 4
Child get_N(): 4

===========================>>>>>>>>>>>>
Value PARENT variable N (via super) = 3
Child get_N1(): 3

===========================>>>>>>>>>>>>
V C S S i m u l a t i o n R e p o r t
 OOPs PART-1 VIKRAM RENESAS

“THIS” KEYWORD
The keyword is used to refer to class properties, parameters and methods of the current instance. It
can only be used within non-static methods, constraints and covergroups. this is basically a pre-
defined object handle that refers to the object that was used to invoke the method in which this is
used.

 This is used inside a class method to refer to the object that is currently calling the method.
 It can be useful when you need to distinguish between the instance's own variables and
parameters that might be passed to a method with the same name.
 It’s typically used in constructor methods, for chaining, or when you need to call another
method or access another member within the same class.

EXAMPLE:

CPU time: .406 seconds to compile + .426 seconds to elab + .485 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:24 2025

===========================>>>>>>>>>>>>
Value of x: 10
===========================>>>>>>>>>>>>

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.460 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

POLYMORPHISM IN SYSTEMVERILOG

Polymorphism in SystemVerilog

Polymorphism is one of the core concepts of Object-Oriented Programming (OOP), and it

allows for the ability to use a single interface to represent different types of objects. In
SystemVerilog, polymorphism is primarily used with classes, and it enables you to write
more flexible and reusable code by allowing objects of different classes to be treated through
a common interface.

Polymorphism means many forms. Polymorphism in SystemVerilog provides an ability to an object to

take on many forms.

Key Concepts of Polymorphism

1. Base Class and Derived Classes:

o A base class defines a common interface (methods and properties).
o Derived classes inherit from the base class and can override its methods to provide
specific implementations.
2. Virtual Methods:
o Methods in the base class must be declared as virtual to allow overriding in derived
classes.
o When a base class handle refers to a derived class object, the overridden method in
the derived class is called.
3. Dynamic Method Dispatch:
o The actual method to be called is determined at runtime based on the type of the
object, not the type of the handle
 OOPs PART-1 VIKRAM RENESAS

1. Polymorphism allows a base class handle to refer to objects of derived classes.

2. Virtual methods enable dynamic method dispatch.
3. Polymorphism is a powerful feature for writing flexible and reusable code

SystemVerilog supports two types of polymorphism:

1. Compile-time Polymorphism (Method Overloading)

2. Runtime Polymorphism (Method Overriding)

1. Compile-time Polymorphism (Method Overloading)

This is achieved by having multiple methods in the same class with the same name but
different argument types or numbers of arguments. This allows the compiler to choose the
correct method at compile-time based on the method signature.

Example 1:

RESULT:
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:54 2025
Drawing a generic shape
Drawing a circle with radius 5
Drawing a rectangle with length 10 and width 20
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.400 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

In this example, the draw() method is overloaded in the derived classes (Circle and Rectangle)
with different parameters. The method that gets called is determined at compile-time based on the
arguments passed.

2. Runtime Polymorphism (Method Overriding)

Runtime polymorphism is achieved through method overriding. In this case, a derived class
provides its specific implementation of a method that was declared in the base class. The
method to be called is determined at runtime based on the actual object type (i.e., whether it's
a Circle, Rectangle, or a Shape).

Chronologic VCS simulator copyright 1991-2023

Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 5 13:57 2025
Drawing a circle
Drawing a rectangle
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

EXAMPLE 1 WITHOUT USING VIRTUAL KEYWORD

RESULT:
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 04:28 2025

-------------------->
Inside parent class
Inside child class 1
-------------------->

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.340 seconds; Data structure size: 0.0Mb
Sat Feb 8 04:28:58 2025
 OOPs PART-1 VIKRAM RENESAS

WITH USING VIRTAL KEYWORD

RESULT :
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 04:35 2025

-------------------->
Inside child class 1

-------------------->
Inside child class 1

-------------------->
Inside parent class 2
-------------------->

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.320 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

Explanation:

The parent class contains two methods:

 display(): This is a virtual function, which means it can be overridden by derived

classes (child classes). The virtual keyword allows subclasses to provide their own
implementation of this method, enabling run-time polymorphism.
 display1(): This is a regular (non-virtual) function. It cannot be overridden by child
classes and will always call the parent class's implementation.

The display() function is designed to print "Inside parent class", and display1()
prints "Inside parent class 2".

 The child_1 class inherits from the parent class.

 The display() function in child_1 overrides the display() function in the parent
class. The display() method in child_1 prints "Inside child class 1".
 Since display1() is not marked as virtual, the child_1 class cannot override it. So, the
version of display1() in the parent class will be used when called from child_1 objects.

Key Concepts in the Code:

1. Polymorphism:
o The line p = c1; demonstrates polymorphism. Here, the parent class handle
p is assigned an instance of child_1. Even though p is of type parent, it
points to an object of child_1. This allows us to call the display() method
in a polymorphic way.
o When p.display() is called, the overridden version of display() in
child_1 is executed, not the one in parent. This is run-time polymorphism.
o The p.display1() call will invoke the display1() method from the parent
class, because display1() is not virtual and cannot be overridden in
child_1.
2. Method Overriding:
o The display() method in child_1 overrides the display() method in
parent. This is done by providing a new implementation for display() in the
child_1 class.
o When p.display() is called (even though p is a parent type handle), the
method in child_1 is executed because display() is virtual.
3. Base Class Handle:
o The parent class handle p can point to an object of any class that extends
parent, like child_1. This allows accessing methods from the derived class
through the base class reference.
o c1.display() is a direct call to the display() method of child_1, and it
also calls the overridden display() in the child_1 class.
 OOPs PART-1 VIKRAM RENESAS

OVERRIDE

-------------------->
Inside parent class 2
Addr = 0

-------------------->
Inside child class 1
Data = 60
Addr = 50

-------------------->
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.350 seconds; Data structure size: 0.0Mb
Sat Feb 8 05:00:34 2025
 OOPs PART-1 VIKRAM RENESAS

EXAMPLE 2
 OOPs PART-1 VIKRAM RENESAS
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 05:10 2025

-------------------->
Inside child class 1
-------------------->

-------------------->
Inside child class 2
-------------------->

-------------------->
Inside child class 3
-------------------->

Inside parent class 2

-------------------->

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.380 seconds; Data structure size: 0.0Mb
Sat Feb 8 05:10:06 2025
 OOPs PART-1 VIKRAM RENESAS

IMPORTANT:
Here child can get all property from parents ex father took 2bh property it will
go to child

Parents cannot get child property ex child took 2bhk that cannot be in
herniated to parents

Another way father has cricket or singing or blue eye pr sugar it will be
inherited to child but child skills will not in to parent if child learn cooking or
any other it will not got to father

P=C1; -> ALLOWED

C1=P -> NOT ALLOWED
ERROR
 OOPs PART-1 VIKRAM RENESAS

CASTING

DYNAMIC CASTING

 Dynamic casting is used to, safely cast a super-class pointer (reference) into a subclass pointer
(reference) in a class hierarchy
 Dynamic casting will be checked during run time, an attempt to cast an object to an incompatible
object will result in a run-time error
 Dynamic casting is done using the $cast(destination, source) method
 With $cast compatibility of the assignment will not be checked during compile time, it will be checked
during run-time
 It is never legal to directly assign a super-class (parent class) variable to a variable of one of its
subclasses (child class).
child_class = parent_class; //not-allowed

 However, it is legal to assign a super-class (parent class) handle to a subclass (child class)
variable if the super-class (parent class) handle refers to an object of the given subclass(child
class).
parent_class = child_class ;
child_class = parent_class; //allowed because parent_class is pointing to
child_class.

ALLOWED

RESULT
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 05:18 2025
 OOPs PART-1 VIKRAM RENESAS
Addr = 10
Data = 20
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.580 seconds; Data structure size: 0.0Mb
Sat Feb 8 05:18:20 202

NOT ALLOWED

ERROR
Error-[SV-ICA] Illegal class assignment
testbench.sv, 22
"c = p;"
Expression 'p' on rhs is not a class or a compatible class and hence cannot
be assigned to a class handle on lhs.
Source type: class $unit::parent_class
Target type: class $unit::child_class
Please make sure that the lhs and rhs expressions are compatible.
OOPs PART-1 VIKRAM RENESAS
 OOPs PART-1 VIKRAM RENESAS

Use of $cast or casting

In the above example, assigning parent class handle (which is pointing to child class handle) to child
class handle is valid but compilation error is observed.
During the compile time, as the handle of p is of parent class type which leads to compile error.

With the use of $cast(), type check during compile time can be skipped.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 05:29 2025

Addr = 10
Data = 20
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.380 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

ABSTRACT CLASS
SystemVerilog prohibits a class declared as virtual to be directly instantiated
and is called an abstract class
EXAMPLE NORMAL CLASS

RESULT
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 05:50 2025

-------------------->
Addr = 10
-------------------->

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.370 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

 ABSTRACT CLASS EXAMPLE

Let us declare the class base as virtual to make it an abstract class and see what
happens.

PURE VIRTUAL METHOD

A virtual method inside an abstract class can be declared with the keyword pure and is
called a pure virtual method. Such methods only require a prototype to be specified within the
abstract class and the implementation is left to defined within the sub-classes.

CPU time: .376 seconds to compile + .360 seconds to elab + .393 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 05:29 2025
Addr = 10
Data = 20
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.380 seconds; Data structure size: 0.0Mb
Sat Feb 8 05:29:25 2025
 OOPs PART-1 VIKRAM RENESAS

EXTERN KEYWORD

ompiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 8 06:18 2025

-------------------->
INSIDE PARENT CLASS: addr = 10
-------------------->

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.420 seconds; Data structure size: 0.0Mb
 OOPs PART-1 VIKRAM RENESAS

Error