Low Cost Instrumentation Amplifier

AD622
FEATURES PIN CONFIGURATION
Easy to use RG 1
AD622 8 RG
Low cost solution –IN 2 7 +VS
Higher performance than two or three op amp design
+IN 3 6 OUTPUT

00777-001
Unity gain with no external resistor
–VS 4 5 REF
Optional gains with one external resistor
(Gain range: 2 to 1000) Figure 1. 8-Lead PDIP and 8-Lead SOIC_N
(N and R Suffixes)
Wide power supply range: ±2.6 V to ±15 V
Available in 8-lead PDIP and 8-lead SOIC_N packages GENERAL DESCRIPTION
Low power, 1.5 mA maximum supply current
The AD622 is a low cost, moderately accurate instrumentation
DC performance
amplifier that requires only one external resistor to set any gain
0.15% gain accuracy: G = 1
between 2 and 1000. For a gain of 1, no external resistor is
125 μV maximum input offset voltage
required. The AD622 is a complete difference or subtracter
1.0 μV/°C maximum input offset drift
amplifier system that also provides superior linearity and
5 nA maximum input bias current
common-mode rejection by incorporating precision laser-
66 dB minimum common-mode rejection ratio: G = 1
trimmed resistors.
Noise
12 nV/√Hz @ 1 kHz input voltage noise The AD622 replaces low cost, discrete, two or three op amp
0.60 μV p-p noise: 0.1 Hz to 10 Hz, G = 10 instrumentation amplifier designs and offers good common-
AC characteristics mode rejection, superior linearity, temperature stability,
800 kHz bandwidth: G = 10 reliability, and board area consumption. The low cost of the
10 μs settling time to 0.1% @ G = 1 to 100 AD622 eliminates the need to design discrete instrumentation
1.2 V/μs slew rate amplifiers to meet stringent cost targets. While providing a
lower cost solution, it also provides performance and space
APPLICATIONS improvements.
Transducer interface
Low cost thermocouple amplifier
Industrial process controls
Difference amplifier
Low cost data acquisition

Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1996–2007 Analog Devices, Inc. All rights reserved.
AD622

TABLE OF CONTENTS
Features .............................................................................................. 1 Theory of Operation .........................................................................9
Applications....................................................................................... 1 Make vs. Buy: A Typical Application Error Budget..................9
Pin Configuration............................................................................. 1 Gain Selection ................................................................................. 11
General Description ......................................................................... 1 Input and Output Offset Voltage.............................................. 11
Revision History ............................................................................... 2 Reference Terminal .................................................................... 11
Specifications..................................................................................... 3 Input Protection ......................................................................... 11
Absolute Maximum Ratings............................................................ 5 RF Interference ........................................................................... 11
Thermal Resistance ...................................................................... 5 Ground Returns for Input Bias Currents ................................ 12
ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 13
Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 14

REVISION HISTORY
8/07—Rev. C to Rev. D
Updated Format..................................................................Universal
Added Thermal Resistance Section ............................................... 5
Added Figure 16................................................................................ 9
Added Large Input Voltages at Large Gains Section.................. 11
Replaced RF Interference Section ................................................ 11
Deleted Grounding Section........................................................... 10
Deleted Figure 16............................................................................ 10
Changes to Ground Returns for Input Bias Currents Section.. 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
4/99—Rev. B to Rev. C
8/98—Rev. A to Rev. B
2/97—Rev. 0 to Rev. A
1/96—Revision 0: Initial Version

Rev. D | Page 2 of 16
 AD622

SPECIFICATIONS
TA = 25°C, VS = ±15 V, and RL = 2 kΩ typical, unless otherwise noted.

Table 1.
Parameter Conditions Min Typ Max Unit
GAIN G = 1 + (50.5 k/RG)
Gain Range 1 1000
Gain Error 1 VOUT = ±10 V
G=1 0.05 0.15 %
G = 10 0.2 0.50 %
G = 100 0.2 0.50 %
G = 1000 0.2 0.50 %
Nonlinearity VOUT = ±10 V
G = 1 to 1000 RL = 10 kΩ 10 ppm
G = 1 to 100 RL = 2 kΩ 10 ppm
Gain vs. Temperature Gain = 1 10 ppm/°C
Gain > 11 −50 ppm/°C
VOLTAGE OFFSET Total RTI Error = VOSI + VOSO/G
Input Offset, VOSI VS = ±5 V to ±15 V 60 125 μV
Average Temperature Coefficient VS = ±5 V to ±15 V 1.0 μV/°C
Output Offset, VOSO VS = ±5 V to ±15 V 600 1500 μV
Average Temperature Coefficient VS = ±5 V to ±15 V 15 μV/°C
Offset Referred to Input vs. Supply (PSR) VS = ±5 V to ±15 V
G=1 80 100 dB
G = 10 95 120 dB
G = 100 110 140 dB
G = 1000 110 140 dB
INPUT CURRENT
Input Bias Current 2.0 5.0 nA
Average Temperature Coefficient 3.0 pA/°C
Input Offset Current 0.7 2.5 nA
Average Temperature Coefficient 2.0 pA/°C
INPUT
Input Impedance
Differential 10||2 G Ω||pF
Common Mode 10||2 GΩ||pF
Input Voltage Range 2 VS = ±2.6 V to ±5 V −VS + 1.9 +VS – 1.2 V
Over Temperature −VS + 2.1 +VS – 1.3 V
VS = ±5 V to ±18 V −VS + 1.9 +VS – 1.4 V
Over Temperature −VS + 2.1 +VS – 1.4 V
Common-Mode Rejection Ratio VCM = 0 V to ±10 V
DC to 60 Hz with 1 kΩ Source Imbalance
G=1 66 78 dB
G = 10 86 98 dB
G = 100 103 118 dB
G = 1000 103 118 dB
OUTPUT
Output Swing RL = 10 kΩ
VS = ±2.6 V to ±5 V −VS + 1.1 +VS – 1.2 V
Over Temperature −VS + 1.4 +VS – 1.3 V
VS = ±5 V to ±18 V −VS + 1.2 +VS – 1.4 V
Over Temperature −VS + 1.6 +VS – 1.5 V
Short Current Circuit ±18 mA

Rev. D | Page 3 of 16
AD622
Parameter Conditions Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=1 1000 kHz
G = 10 800 kHz
G = 100 120 kHz
G = 1000 12 kHz
Slew Rate 1.2 V/μs
Settling Time to 0.1% 10 V step
G = 1 to 100 10 μs
NOISE
Voltage Noise, 1 kHz Total RTI Noise = √(e2ni) + (eno⁄G)2
Input Voltage Noise, eni 12 nV/√Hz
Output Voltage Noise, eno 72 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G=1 4.0 μV p-p
G = 10 0.6 μV p-p
G = 100 0.3 μV p-p
Current Noise f = 1 kHz 100 fA/√Hz
0.1 Hz to 10 Hz 10 pA p-p
REFERENCE INPUT
RIN 20 kΩ
IIN VIN+, VREF = 0 50 60 μA
Voltage Range −VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0015
POWER SUPPLY
Operating Range 3 ±2.6 ±18 V
Quiescent Current VS = ±2.6 V to ±18 V 0.9 1.3 mA
Over Temperature 1.1 1.5 mA
TEMPERATURE RANGE
For Specified Performance −40 to +85 °C
1
Does not include effects of External Resistor RG.
2
One input grounded, G = 1.
3
Defined as the same supply range that is used to specify PSR.

Rev. D | Page 4 of 16
 AD622

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 2.
Parameter Rating θJA is specified for the device in free air.
Supply Voltage ±18 V Table 3. Thermal Resistance
Internal Power Dissipation1 650 mW Package Type θJA Unit
Input Voltage (Common Mode) ±VS 8-Lead PDIP (N-8) 95 °C/W
Differential Input Voltage2 ±25 V 8-Lead SOIC_N (R-8) 155 °C/W
Output Short Circuit Duration Indefinite
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature (Soldering, 10 sec) 300°C
1
Specification is for device in free air; see Table 3.
2
May be further restricted for gains greater than 14. See the Input Protection
section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. D | Page 5 of 16
AD622

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
50 1000
SAMPLE SIZE = 191

40
GAIN = 1

VOLTAGE NOISE (nV/ Hz)

PERCENTAGE OF UNITS

100
30

GAIN = 10

20
10

GAIN = 100, 1000

10

GAIN = 1000
BW LIMIT
0 1
00777-002

00777-005
–1.2 –0.8 –0.4 0 0.4 0.8 1.2 1 10 100 1k 10k 100k
OUTPUT OFFSET VOLTAGE (mV) FREQUENCY (Hz)

Figure 2. Typical Distribution of Output Offset Voltage Figure 5. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)

50 1000
SAMPLE SIZE = 383

40
CURRENT NOISE (fA/ Hz)
PERCENTAGE OF UNITS

30

100

20

10

0 10
00777-003

00777-006
60 80 100 120 140 1 10 100 1000
COMMON-MODE REJECTION RATIO (dB) FREQUENCY (Hz)

Figure 3. Typical Distribution of Common-Mode Rejection Figure 6. Current Noise Spectral Density vs. Frequency

2.0 140

120 G = 1000
INPUT OFFSET VOLTAGE (µV)

1.5 G = 100
100
G = 10
80
CMR (dB)

1.0 G=1
60

40
0.5

20

0 0
00777-004

00777-007

0 1 2 3 4 5 0.1 1 10 100 1k 10k 100k 1M

WARM-UP TIME (Minutes) FREQUENCY (Hz)

Figure 4. Change in Input Offset Voltage vs. Warm-Up Time Figure 7. CMR vs. Frequency, RTI, 0 kΩ to 1 kΩ Source Imbalance

Rev. D | Page 6 of 16
 AD622
180 30
VS = ±15V
G = 10
160

OUTPUT VOLTAGE SWING (V p-p)

140
POSITIVE PSR (dB)

20
120 G = 1000

100

G = 100
80
10

60 G = 10

40
G=1

20 0

00777-008

00777-011
0.1 1 10 100 1k 10k 100k 1M 10 100 1k 10k
FREQUENCY (Hz) LOAD RESISTANCE (Ω)

Figure 8. Positive PSR vs. Frequency, RTI (G = 1 to 1000) Figure 11. Output Voltage Swing vs. Load Resistance

180 20

160

140 15

SETTLING TIME (µs)

NEGATIVE PSR (dB)

120 TO 0.1%

100 10
G = 1000
80

G = 100 5
60

40 G = 10

G=1
20 0
00777-009

00777-012
0.1 1 10 100 1k 10k 100k 1M 0 5 10 15 20
FREQUENCY (Hz) OUTPUT STEP SIZE (V)

Figure 9. Negative PSR vs. Frequency, RTI (G = 1 to 1000) Figure 12. Settling Time vs. Step Size (G = 1)

1000 1000

100
SETTLING TIME (µs)

100
GAIN (V/V)

10

10
1

0.1 1
00777-010

00777-013

100 1k 10k 100k 1M 10M 1 10 100 1000

FREQUENCY (Hz) GAIN

Figure 10. Gain vs. Frequency Figure 13. Settling Time to 0.1% vs. Gain, for a 10 V Step

Rev. D | Page 7 of 16
AD622
10kΩ 1kΩ 10kΩ
INPUT 0.01% POT 0.1%
20V p-p
VOUT

100 100kΩ
0.1%
90
+VS

11kΩ 1kΩ 100Ω 2 7

Ø 0.1% 0.1% 0.1%
1

G = 1000 G=1 AD622 6

8 5
G = 100 G = 10

5.62kΩ
3

51.1Ω
10 4

511Ω
0%
–VS

00777-015
10µV 2V

00777-014
Figure 14. Gain Nonlinearity, G = 1, RL = 10 kΩ (20 μV = 2 ppm) Figure 15. Settling Time Test Circuit

Rev. D | Page 8 of 16
 AD622

THEORY OF OPERATION
The AD622 is a monolithic instrumentation amplifier based on The value of RG also determines the transconductance of the
a modification of the classic three op amp approach. Absolute preamp stage. As RG is reduced for larger gains, the trans-
value trimming allows the user to program gain accurately (to conductance increases asymptotically to that of the input
0.5% at G = 100) with only one resistor. Monolithic construction transistors. This has the following three important advantages:
and laser wafer trimming allow the tight matching and tracking • Open-loop gain is boosted for increasing programmed
of circuit components, thus insuring AD622 performance. gain, thus reducing gain-related errors.
Input Transistor Q1 and Input Transistor Q2 provide a single • The gain-bandwidth product (determined by C1, C2, and
differential-pair bipolar input for high precision (see Figure 16). the preamp transconductance) increases with programmed
Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop gain, thus optimizing frequency response.
maintains constant collector current of the Q1 and Q2 input • The input voltage noise is reduced to a value of 12 nV/√Hz,
devices, thereby impressing the input voltage across External determined mainly by the collector current and base
Gain-Setting Resistor RG. This creates a differential gain from the resistance of the input devices.
inputs to the A1 and A2 outputs given by G = (R1 + R2)/RG + 1. The internal gain resistors, R1 and R2, are trimmed to an
Unity-Gain Subtracter A3 removes any common-mode signal, absolute value of 25.25 kΩ, allowing the gain to be programmed
yielding a single-ended output referred to the REF pin potential. accurately with a single external resistor.
MAKE vs. BUY: A TYPICAL APPLICATION ERROR
I1 20µA VB 20µA I2 BUDGET
The AD622 offers cost and performance advantages over
A1 A2
discrete two op amp instrumentation amplifier designs along
10kΩ
C1 C2 with smaller size and fewer components. In a typical application
10kΩ shown in Figure 17, a gain of 10 is required to receive and
A3 OUTPUT amplify a 0 to 20 mA signal from the AD694 current transmitter.
R3 10kΩ 10kΩ The current is converted to a voltage in a 50 Ω shunt. In
R1 R2 REF
400Ω
–IN Q1 Q2 +IN applications where transmission is over long distances, line
R4
RG 400Ω impedance can be significant so that differential voltage
GAIN GAIN measurement is essential. Where there is no connection
SENSE SENSE
between the ground returns of transmitter and receiver, there
must be a dc path from each input to ground, implemented in
00777-021

–VS
this case using two 1 kΩ resistors. The error budget detailed in
Figure 16. Simplified Schematic of the AD622 Table 4 shows how to calculate the effect of various error
sources on circuit accuracy.

+
RL2 1kΩ
10Ω
VIN 1/2
LT1013 1/2
AD694 0 TO 20mA 50Ω LT1013
0 TO 20mA 1kΩ RG –
TRANSMITTER 5.62kΩ AD622 1kΩ
RL2
REF
10Ω 1kΩ 9kΩ* 1kΩ* 1kΩ* 9kΩ*

*0.1% RESISTOR MATCH, 50ppm/°C TRACKING

00777-016

0 TO 20mA CURRENT LOOP AD622 MONOLITHIC INSTRUMENTATION HOMEBREW IN-AMP, G = 10

WITH 50Ω SHUNT IMPEDANCE AMPLIFIER, G = 9.986
Figure 17. Make vs. Buy

Rev. D | Page 9 of 16
AD622
The AD622 provides greater accuracy at lower cost. The higher over temperature due to the drift mismatch of the discrete
cost of the homebrew circuit is dominated in this case by the resistors.
matched resistor network. One could also realize a homebrew Note that for the homebrew circuit, the LT1013 specification for
design using cheaper discrete resistors that are either trimmed noise has been multiplied by √2. This is because a two op amp
or hand selected to give high common-mode rejection. This type instrumentation amplifier has two op amps at its inputs,
level of common-mode rejection, however, degrades significantly both contributing to the overall noise.

Table 4. Make vs. Buy Error Budget

Total Error in ppm
Relative to 1 V FS
Error Source AD622 Circuit Calculation Homebrew Circuit Calculation AD622 Homebrew
ABSOLUTE ACCURACY at TA = 25°C
Total RTI Offset Voltage, μV 250 μV + 1500 μV/10 800 μV × 2 400 1600
Input Offset Current, nA 2.5 nA × 1 kΩ 15 nA × 1 kΩ 2.5 15
CMR, dB 86 dB→50 ppm × 0.5 V (0.1% Match × 0.5 V)/10 V 25 50
Total Absolute Error 427.5 1665
DRIFT TO 85°C
Gain Drift, ppm/°C (50 ppm + 5 ppm) × 60°C (50 ppm)/°C × 60°C 3300 3000
Total RTI Offset Voltage, μV/°C (2 μV/°C + 15 μV/°C /10) × 60°C 9 μV/°C × 2 × 60°C 210 1080
Input Offset Current, pA/°C 2 pA/°C × 1 kΩ × 60°C 155 pA/°C × 1 kΩ × 60°C 0.12 9.3
Total Drift Error 3510.12 4089.3
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 10 ppm 20 ppm 10 20
Typ 0.1 Hz to 10 Hz Voltage Noise, μV p-p 0.6 μV p-p 0.55 μV p-p × √2 0.6 0.778
Total Resolution Error 10.6 20.778
Grand Total Error 3948 5775

Rev. D | Page 10 of 16
 AD622

GAIN SELECTION
The AD622 gain is resistor programmed by RG or, more separately. For longer time periods, the input current should not
precisely, by whatever impedance appears between Pin 1 and exceed 6 mA. For input overloads beyond the supplies, clamping
Pin 8. The AD622 is designed to offer gains as close as possible the inputs to the supplies (using a diode such as a BAV199)
to popular integer values using standard 1% resistors. Table 5 reduces the required resistance, yielding lower noise.
shows required values of RG for various gains. Note that for Large Input Voltages at Large Gains
G = 1, the RG pins are unconnected (RG = ∞). For any arbitrary When operating at high gain, large differential input voltages
gain, RG can be calculated by using the formula may cause more than 6 mA of current to flow into the inputs.
50.5 k Ω This condition occurs when the maximum differential voltage
RG = exceeds the following critical voltage:
G −1
To minimize gain error, avoid high parasitic resistance in series VCRITICAL = (400 + RG) × (6 mA)
with RG. To minimize gain drift, RG should have a low temperature This is true for differential voltages of either polarity.
coefficient less than 10 ppm/°C for the best performance.
The maximum allowed differential voltage can be increased by
Table 5. Required Values of Gain Resistors adding an input protection resistor in series with each input.
Desired Calculated The value of each protection resistor should be as follows:
Gain 1% Std Table Value of RG, Ω Gain RPROTECT = (VDIFF_MAX − VCRITICAL)/6 mA
2 51.1 k 1.988
5 12.7 k 4.976
RF INTERFERENCE
10 5.62 k 9.986 RF rectification is often a problem when amplifiers are used in
20 2.67 k 19.91 applications where there are strong RF signals. The disturbance
33 1.58 k 32.96 may appear as a small dc offset voltage. High frequency signals
40 1.3 k 39.85 can be filtered with a low-pass, RC network placed at the input
50 1.02 k 50.50 of the instrumentation amplifier, as shown in Figure 18. In
65 787 65.17 addition, this RC input network also provides additional input
100 511 99.83 overload protection (see the Input Protection section).
200 255 199.0 +VS

500 102 496.1 +

0.1µF 10µF
1000 51.1 989.3
CC
R
INPUT AND OUTPUT OFFSET VOLTAGE 4.02kΩ 1nF
+IN
VOUT
The low errors of the AD622 are attributable to two sources: R CD RG AD622
4.02kΩ 47nF
input and output errors. The output error is divided by G when REF
–IN
referred to the input. In practice, the input errors dominate at CC
1nF
high gains and the output errors dominate at low gains. The
0.1µF 10µF +
total VOS for a given gain is calculated as follows: 00777-017

–VS
Total Error RTI = input error + (output error/G)
Figure 18. RFI Suppression Circuit for AD622 Series In-Amps
Total Error RTO = (input error × G) + output error
REFERENCE TERMINAL
The filter limits the input signal bandwidth to the following
The reference terminal potential defines the zero output voltage
cutoff frequencies:
and is especially useful when the load does not share a precise
1
ground with the rest of the system. The reference terminal provides FilterFreq DIFF =
a direct means of injecting a precise offset to the output, with an 2π R(2C D + CC )
allowable range of 2 V within the supply voltages. Parasitic 1
resistance should be kept to a minimum for optimum CMR. FilterFreqCM =
2π RCC
INPUT PROTECTION
where CD ≥ 10CC.
The AD622 features 400 Ω of series thin film resistance at its
inputs and safely withstands input overloads of up to ±15 V or
±60 mA for up to an hour at room temperature. This is true for
all gains and power on and off, which is particularly important
because the signal source and amplifier can be powered

Rev. D | Page 11 of 16
AD622
+VS
Figure 18 shows an example where the differential filter
–IN
frequency is approximately 400 Hz, and the common-mode 2 7

filter frequency is approximately 40 kHz. With this differential 1

filter in place and operating at gain of 1000, the typical dc offset RG

AD622 6 VOUT

shift over a frequency range of 1 Hz to 20 MHz is less than 1.5 μV 8 5

RTI, and the RF signal rejection of the circuit is better than 3 4 LOAD
+IN REF
71 dB. At a gain of 100, the dc offset shift is well below 1 mV
–VS
TO POWER

00777-018
RTI, and RF rejection is greater than 70 dB. SUPPLY
GROUND
The input resistors should be selected to be high enough to
Figure 19. Ground Returns for Bias Currents with Transformer Coupled Inputs
isolate the sensor from the CC and C D capacitors but low
+VS
enough not to influence system noise. Mismatch between
–IN
R × CC at the positive input and R × CC at the negative input 2 7

degrades the CMRR of the AD622. Therefore, the CC capacitors 1

RG
should be high precision types such as NPO/COG ceramics. AD622 6 VOUT
8
The tolerance of the CD capacitor is less critical. 5
3 4 LOAD
+IN REF
GROUND RETURNS FOR INPUT BIAS CURRENTS
–VS TO POWER

00777-019
Input bias currents are those currents necessary to bias the SUPPLY
GROUND
input transistors of an amplifier. There must be a direct return
path for these currents; therefore, when amplifying floating Figure 20. Ground Returns for Bias Currents with Thermocouple Inputs

input sources such as transformers or ac-coupled sources, there +VS

must be a dc path from each input to ground as shown in –IN

2 7
Figure 19, Figure 20, and Figure 21. Refer to the Designer’s 1

Guide to Instrumentation Amplifiers (free from Analog Devices, RG

AD622 6 VOUT
Inc.) for more information regarding in-amp applications. 8 5
3 4 LOAD
+IN REF
100kΩ 100kΩ
–VS TO POWER

00777-020
SUPPLY
GROUND
Figure 21. Ground Returns for Bias Currents with AC-Coupled Inputs

Rev. D | Page 12 of 16
 AD622

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 22. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-A A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 23. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

Rev. D | Page 13 of 16
AD622
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD622AN −40°C to +85°C 8-Lead PDIP N-8
AD622ANZ 1 −40°C to +85°C 8-Lead PDIP N-8
AD622AR –40°C to +85°C 8-Lead SOIC_N R-8
AD622AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD622AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD622ARZ1 –40°C to +85°C 8-Lead SOIC_N R-8
AD622ARZ-RL1 –40°C to +85°C 8-Lead SOIC_N R-8
AD622ARZ-RL71 –40°C to +85°C 8-Lead SOIC_N R-8
1
Z = RoHS Compliant Part.

Rev. D | Page 14 of 16
 AD622

NOTES

Rev. D | Page 15 of 16
AD622

NOTES

©1996–2007 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C00777-0-8/07(D)

Rev. D | Page 16 of 16