Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015

SN74LVC245A Octal Bus Transceiver With 3-State Outputs

1 Features 2 Applications
•
1 Operates From 1.65 V to 3.6 V • Cable Modem Termination Systems
• Inputs Accept Voltages to 5.5 V • Servers
• Max tpd of 6.3 ns at 3.3 V • LED Displays
• Typical VOLP (Output Ground Bounce) • Network Switches
< 0.8 V at VCC = 3.3 V, TA = 25°C • Telecom Infrastructure
• Typical VOHV (Output VOH Undershoot) • Motor Drivers
> 2 V at VCC = 3.3 V, TA = 25°C • I/O Expanders
• Ioff Supports Live Insertion, Partial-Power-Down
Mode and Back Drive protection 3 Description
• Supports Mixed-Mode Signal Operation on All These octal bus transceivers are designed for 1.65-V
Ports (5-V Input/Output Voltage With 3.3-V VCC) to 3.6-V VCC operation. The ’LVC245A devices are
• Latch-Up Performance Exceeds 250 mA designed for asynchronous communication between
Per JESD 17 data buses.
• ESD Protection Exceeds JESD 22 Device Information(1)
– 2000-V Human-Body Model PART NUMBER PACKAGE (PIN) BODY SIZE
– 1000-V Charged-Device Model VQFN (20) 4.50 mm × 3.50 mm
SSOP (20) 7.50 mm × 5.30 mm
SN74LVC245A TSSOP (20) 6.50 mm × 4.40 mm
TVSOP (20) 5.00 mm × 4.40 mm
SOIC (20) 12.80 mm × 7.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

4 Simplified Schematic

1
DIR

19
OE

2
A1

18
B1

To Seven Other Channels

Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................... 9
2 Applications ........................................................... 1 9.2 Functional Block Diagram ......................................... 9
3 Description ............................................................. 1 9.3 Feature Description................................................... 9
9.4 Device Functional Modes.......................................... 9
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2 10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
6 Pin Configuration and Functions ......................... 3
10.2 Typical Application ............................................... 10
7 Specifications......................................................... 4
11 Power Supply Recommendations ..................... 11
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
7.3 Recommended Operating Conditions....................... 5
12.2 Layout Example .................................................... 11
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6 13 Device and Documentation Support ................. 12
7.6 Switching Characteristics .......................................... 6 13.1 Trademarks ........................................................... 12
7.7 Operating Characteristics.......................................... 7 13.2 Electrostatic Discharge Caution ............................ 12
7.8 Typical Characteristics .............................................. 7 13.3 Glossary ................................................................ 12
8 Parameter Measurement Information .................. 8 14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
9 Detailed Description .............................................. 9

5 Revision History
Changes from Revision W (May 2013) to Revision X Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1

Changes from Revision V (September 2010) to Revision W Page

• Added –40°C to 125°C temperature specification to Recommended Operating Conditions table. ...................................... 5

2 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC245A

 SN74LVC245A
www.ti.com SCAS218X – JANUARY 1993 – REVISED JANUARY 2015

6 Pin Configuration and Functions

GQN OR ZQN PACKAGE
(TOP VIEW)
1 2 3 4

A
B
C
D
E

DB, DGV, DW, N, NS, OR PW PACKAGE RGY PACKAGE

(TOP VIEW) (TOP VIEW)

VCC
DIR
DIR 1 20 VCC
A1 2 19 OE
1 20
A2 3 18 B1
A1 2 19 OE
A3 4 17 B2
A2 3 18 B1
A4 5 16 B3
A3 4 17 B2
A5 6 15 B4
A4 5 16 B3
A6 7 14 B5 A5 6 15 B4
A7 8 13 B6 A6 7 14 B5
A8 9 12 B7 A7 8 13 B6
GND 10 11 B8 A8 9 12 B7
10 11

B8
GND

Pin Functions
PIN
DB, DGV, TYPE DESCRIPTION
NAME DW, NS, PW, GQN or ZQN
and RGY
A1 2 A1 I/O Transceiver I/O pin
A2 3 B3 I/O Transceiver I/O pin
A3 4 B1 I/O Transceiver I/O pin
A4 5 C2 I/O Transceiver I/O pin
A5 6 C1 I/O Transceiver I/O pin
A6 7 D3 I/O Transceiver I/O pin
A7 8 D1 I/O Transceiver I/O pin
A8 9 E2 I/O Transceiver I/O pin
B1 18 B4 I/O Transceiver I/O pin
B2 17 B2 I/O Transceiver I/O pin
B3 16 C4 I/O Transceiver I/O pin
B4 15 C3 I/O Transceiver I/O pin
B5 14 D4 I/O Transceiver I/O pin
B6 13 D2 I/O Transceiver I/O pin
B7 12 E4 I/O Transceiver I/O pin
B8 11 E3 I/O Transceiver I/O pin
Direction control. When high, the signal propagates from A to B. When low, the signal
DIR 1 A2 I
propagates from B to A.
OE 19 A4 I Output enable
GND 10 E1 — Ground
VCC 20 A3 — Power pin

Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: SN74LVC245A
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

7.2 ESD Ratings

PARAMETER DEFINITION VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000
Electrostatic
V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101, all V
discharge 1000
pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC245A

 SN74LVC245A
www.ti.com SCAS218X – JANUARY 1993 – REVISED JANUARY 2015

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
TA = 25°C –40°C TO 85°C –40°C TO 125°C
UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level input
VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
voltage
VCC = 2.7 V to 3.6 V 2 2 2
0.35 × 0.35 ×
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC VCC
Low-level input
VIL V
voltage VCC = 2.3 V to 2.7 V 0.7 0.7 0.7
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65 V –4 –4 –4
High-level output VCC = 2.3 V –8 –8 –8
IOH mA
current VCC = 2.7 V –12 –12 –12
VCC = 3 V –24 –24 –24
VCC = 1.65 V 4 4 4
Low-level output VCC = 2.3 V 8 8 8
IOL mA
current VCC = 2.7 V 12 12 12
VCC = 3 V 24 24 24
Δt/Δv Input transition rise or fall rate 10 10 10 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal Information

SN74LVC245A
(1) (2) (2) (2) GQN or UNI
THERMAL METRIC DB DGV DW N (2) NS (2) PW (2) RGY (3)
ZQN (2) T
20 PINS
Junction-to-ambient thermal
RθJA 106.5 124.1 92.9 78 59.2 83.6 108.1 44.0
resistance
RθJC(t Junction-to-case(top) thermal
68.1 39.5 60.6 44.9 49.4 43.0 53.0
op) resistance
Junction-to-board thermal
RθJB 61.7 65.5 60.4 40.1 51.2 59.1 22.1
resistance °C/
Junction-to-top characterization W
ψJT 28.5 2.1 28.2 29.9 21.9 4.7 3.0
parameter
Junction-to-board
ψJB 61.2 64.9 60.0 39.9 50.8 58.6 22.2
characterization parameter
RθJC(b Junction-to-case(bottom)
— — — — — — 16.6
ot) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.

Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: SN74LVC245A
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C –40°C TO 85°C –40°C TO 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
1.65 V
IOH = –100 μA to VCC – 0.2 VCC – 0.2 VCC – 0.2
3.6 V
IOH = –4 mA 1.65 V 1.29 1.2 1.1
VOH IOH = –8 mA 2.3 V 1.9 1.7 1.6 V
2.7 V 2.2 2.2 2.1
IOH = –12 mA
3V 2.4 2.4 2.3
IOH = –24 mA 3V 2.3 2.2 2.1
1.65 V
IOL = 100 μA to 0.1 0.2 0.2
3.6 V
IOL = 4 mA 1.65 V 0.24 0.45 0.60
VOL V
IOL = 8 mA 2.3 V 0.3 0.7 0.75
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.75
Control
II VI = 0 to 5.5 V 3.6 V ±1 ±5 ±10 μA
inputs
Ioff VI or VO = 5.5 V 0 ±1 ±10 ±20 μA
IOZ (1) VO = 0 to 5.5 V 3.6 V ±1 ±10 ±20 μA
VI = VCC or GND 1 10 30
ICC IO = 0 3.6 V μA
3.6 V ≤ VI ≤ 5.5 V (2) 1 10 30
One input at VCC – 0.6 V, 2.7 V to
ΔICC 500 500 5000 μA
Other inputs at VCC or GND 3.6 V
Control
Ci VI = VCC or GND 3.3 V 4 pF
inputs
A or B
Cio VI = VCC or GND 3.3 V 5.5 pF
ports (3)

(1) All typical values are at VCC = 3.3 V, TA = 25 C.

(2) This applies in the disabled state only.
(3) For I/O ports, the parameter Ioz includes the input leakage current.

7.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C TO –40°C TO
FROM TO TA = 25°C
PARAMETER VCC 85°C 125°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
1.8 V ± 0.15 V 1 6 12.2 1 12.7 1 13.7
2.5 V ± 0.2 V 1 3.9 7.8 1 8.3 1 9.1
tpd A or B B or A ns
2.7 V 1 4.2 7.1 1 7.3 1 8.3
3.3 V ± 0.3 V 1.5 3.8 6.1 1.5 6.3 1.5 7.3
1.8 V ± 0.15 V 1 7 14.8 1 15.3 1 16.8
2.5 V ± 0.2 V 1 4.5 10 1 10.5 1 12
ten OE A or B ns
2.7 V 1 5.4 9.3 1 9.5 1 11
3.3 V ± 0.3 V 1.5 4.4 8.3 1.5 8.5 1.5 10
1.8 V ± 0.15 V 1 7.8 16.5 1 17 1 18
2.5 V ± 0.2 V 1 4 9 1 9.5 1 10.5
tdis OE A or B ns
2.7 V 1 4.4 8.3 1 8.5 1 9.5
3.3 V ± 0.3 V 1.7 4.1 7.3 1.7 7.5 1.7 8.5
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns

6 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC245A

 SN74LVC245A
www.ti.com SCAS218X – JANUARY 1993 – REVISED JANUARY 2015

7.7 Operating Characteristics

TA = 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
1.8 V 42
Outputs enabled 2.5 V 43
3.3 V 45
Cpd Power dissipation capacitance per transceiver f = 10 MHz pF
1.8 V 1
Outputs disabled 2.5 V 1
3.3 V 2

7.8 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12

tpd – Propagation Delay Time – ns

One Output Switching
tpd – Propagation Delay Time – ns

One Output Switching

Four Outputs Switching 8 Four Outputs Switching
Eight Outputs Switching Eight Outputs Switching
10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition) Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance vs Load Capacitance

Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: SN74LVC245A
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

8 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH - V∆
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

8 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC245A

 SN74LVC245A
www.ti.com SCAS218X – JANUARY 1993 – REVISED JANUARY 2015

9 Detailed Description

9.1 Overview
This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC245A device is designed for asynchronous communication between data buses. This device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses
effectively are isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a
translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.

9.2 Functional Block Diagram

1
DIR

19
OE

2
A1

18
B1

To Seven Other Channels

Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.

9.3 Feature Description

• Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
• Inputs accept voltage levels up to 5.5 V

9.4 Device Functional Modes

Table 1. Function Table

INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation

Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: SN74LVC245A
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

SN74LVC245A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.

10.2 Typical Application

Regulated 1.8 V Regulated 1.65 V to 3.6 V

Regulated 5 V
SN74LVC245A SN74LVC245A
1OE VCC 1OE VCC
DIR DIR
uC
A1 B1 A1 B1
uC uC
System Logic uC System Logic
or LEDs/Relays LEDs/Relays
System Logic
A8 B8 LEDs/Relays A8 B8
Other System
Boards
GND GND

Figure 4. Typical Application Schematic

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.

10 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC245A

 SN74LVC245A
www.ti.com SCAS218X – JANUARY 1993 – REVISED JANUARY 2015

Typical Application (continued)

10.2.3 Application Curves
100 60
TA = 25°C, VCC = 3 V, TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V, 40 VIH = 3 V, VIL = 0 V,
80 All Outputs Switching All Outputs Switching
20
60
0
I OL – mA

I OH – mA
40 –20

–40
20

–60
0
–80

–20 –100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOL – V VOH – V

Figure 5. Output Drive Current (IOL) Figure 6. Output Drive Current (IOH)
vs LOW-level Output Voltage (VOL) vs HIGH-level Output Voltage (VOH)

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.

12.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

Figure 7. Layout Diagram

Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: SN74LVC245A
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

13 Device and Documentation Support

13.1 Trademarks
All trademarks are the property of their respective owners.

13.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

12 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC245A

 PACKAGE OPTION ADDENDUM

www.ti.com 27-May-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC245ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245ADBRE4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245ADBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A Samples

SN74LVC245ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A Samples

SN74LVC245ADWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A Samples

SN74LVC245AN ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74LVC245AN Samples

SN74LVC245ANE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74LVC245AN Samples

SN74LVC245ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC245A Samples

SN74LVC245APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWRG3 ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC245A Samples

SN74LVC245ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC245A Samples

(1)
The marketing status values are defined as follows:

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 27-May-2022

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC245A :

• Enhanced Product : SN74LVC245A-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC245ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVC245ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC245ADWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74LVC245ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74LVC245APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC245APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVC245APWRG3 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC245APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVC245APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC245ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC245ADBR SSOP DB 20 2000 356.0 356.0 35.0
SN74LVC245ADGVR TVSOP DGV 20 2000 356.0 356.0 35.0
SN74LVC245ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVC245ANSR SO NS 20 2000 367.0 367.0 45.0
SN74LVC245APWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74LVC245APWR TSSOP PW 20 2000 356.0 356.0 35.0
SN74LVC245APWRG3 TSSOP PW 20 2000 364.0 364.0 27.0
SN74LVC245APWRG4 TSSOP PW 20 2000 356.0 356.0 35.0
SN74LVC245APWT TSSOP PW 20 250 356.0 356.0 35.0
SN74LVC245ARGYR VQFN RGY 20 3000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74LVC245ADW DW SOIC 20 25 507 12.83 5080 6.6
SN74LVC245AN N PDIP 20 20 506 13.97 11230 4.32
SN74LVC245ANE4 N PDIP 20 20 506 13.97 11230 4.32
SN74LVC245APW PW TSSOP 20 70 530 10.2 3600 3.5
SN74LVC245APWE4 PW TSSOP 20 70 530 10.2 3600 3.5
SN74LVC245APWG4 PW TSSOP 20 70 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 GENERIC PACKAGE VIEW
RGY 20 VQFN - 1 mm max height
3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225264/A

www.ti.com
 PACKAGE OUTLINE
RGY0020A SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.65 B
A
3.35

PIN 1 INDEX AREA

4.65
4.35

1.0
0.8

SEATING PLANE
0.05
0.00 0.08 C
2.05 0.1

2X 1.5
(0.2) TYP
10 11 EXPOSED
THERMAL PAD
9
12
14X 0.5

2X SYMM 21
3.05 0.1
3.5

2
19
0.30
1 20 20X
PIN 1 ID 0.18
SYMM
0.1 C A B
0.5 0.05
20X
0.3
4225320/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.05)
SYMM
1 20
20X (0.6)

2
19

20X (0.24)

(1.275)

(4.3)
SYMM 21
(3.05)

14X (0.5)

(0.775) 12
9

(R0.05) TYP

( 0.2) TYP
VIA 10 11
(0.75) TYP

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225320/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

4X (0.92)

1 20 (R0.05) TYP

20X (0.6)

2
19

20X (0.24)

4X
(1.33)

21
SYMM

(4.3)
(0.77)

14X (0.5)

(0.56)
9 12

METAL
TYP
10 11
(0.75)
TYP
(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4225320/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated