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Manual_14

This laboratory manual focuses on the introduction to JK Flip-Flops, detailing their operation and applications in frequency division. It outlines the equipment and components needed for experiments, including tasks to verify the flip-flop's basic functions and to construct frequency dividers. The manual emphasizes the importance of understanding the PRESET and CLEAR inputs for controlling the flip-flop states.

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14 views4 pages

Manual_14

This laboratory manual focuses on the introduction to JK Flip-Flops, detailing their operation and applications in frequency division. It outlines the equipment and components needed for experiments, including tasks to verify the flip-flop's basic functions and to construct frequency dividers. The manual emphasizes the importance of understanding the PRESET and CLEAR inputs for controlling the flip-flop states.

Uploaded by

dlpkrshna
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INSTITUTE OF BUSINESS ADMINISTRATION, KARACHI

Digital Logic Design (CSE-241)


Laboratory Manual
LAB # 14
Introduction to Flip-Flops
Objective:

The aim of this experiment is to study the basic working of a JK Flip-Flop and to learn designing
frequency dividers using flip-flops

Equipment: Components:

1. One- Single Polarity Variable DC Power 1. One-74LS76 JK-Flip-Flop


Supply 2. LEDs
2. Digital Oscilloscope 3. Switches
3. Digital Function Generator 4. One- Bread Board
4. Logic Probe

Note: Do consult the data sheets before connecting you ICs

THEORY: J-K Flip-Flop

A J-K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the entries in the function
table. In the case of an R-S flip-flop, the input combination S = R = 1 is prohibited. In the case of a J-K flip-
flop with active HIGH inputs, the output of the flip-flop toggles, that is, it goes to the other state, for J =
K = 1 . The output toggles. Thus, a J-K flip-flop overcomes the problem of a forbidden input combination
of the R-S flip-flop. This is achieved by a minor addition in the R-S flip flop circuit. Notice in the figure

that the Q output is connected back to the input of gate G2. and the Q output is connected back to

the input of gate G1.

Faculty of Computer Science Page 1


J-K Flip-Flop with PRESET and CLEAR Inputs:

It is often necessary to clear a flip-flop to a logic ‘0’ state (Qn = 0) or preset it to a logic ‘1’ state (Qn =1 ).
An example of how this is realized is shown in Fig. The flip-flop is cleared (that is, Qn = 0) whenever the
CLEAR input is ‘0’ and the PRESET input is ‘1’. The flip-flop is preset to the logic ‘1’ state whenever the
PRESET input is ‘0’ and the CLEAR input is ‘1’. Here, the CLEAR and PRESET inputs are active when LOW.
It is evident from the function table that, whenever the PRESET input is active, the output goes to the ‘1’
state irrespective of the status of the clock, J and K inputs. Similarly, when the flip-flop is cleared, that is,
the CLEAR input is active, the output goes to the ‘0’ state irrespective of the status of the clock, J and K
inputs. In a flip-flop of this type, both PRESET and CLEAR inputs should not be made active at the same
time.

Faculty of Computer Science Page 2


J-K Flip-Flop Applications:

For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip
flops to continue to divide by two One flip-flop will divide fin by 2, two flip-flops will divide fin by 4 (and
so on). A side benefit of frequency division is that the output has an exact 50% duty cycle.

Faculty of Computer Science Page 3


Task 1:
 Connect any one of the two flip-flops available to you, please keep all the inputs of the flip-flop
(i.e. J, K, PRE and CLR) connected to switches so that they could be altered according to need.
 Initially keep your PRE and CLR connected to Vcc for observing general operation of the flip-flop.
 Verify the basic function of a flip-flop using the truth table given above.
o Set your input clock to 10 Hz.
 The 74LS76 flip-flop has a direct-set input PRE and direct reset input CLR, which will operate at
any time, independent of the clock, and will take precedence over any other signal. With the
flip-flop running in the toggle mode (i.e. J and K inputs both set to high), apply 0 V dc to PRE and
then to CLR to verify that these inputs do indeed set and reset the flip-flop independently.
Observe the resulting waveforms on the oscilloscope, and verify with you instructor.

Task 2:
 Construct a ÷2 and ÷4 frequency divider using the flip-flops provided to you.
o For this task set your clock input to 100 Hz using the digital function generator.
o Verify the frequency through measurements using oscilloscope measurement set
readings.
o Also observe the output waveforms (÷2 , ÷4) using oscilloscope.

Faculty of Computer Science Page 4

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