Manual_14
Manual_14
The aim of this experiment is to study the basic working of a JK Flip-Flop and to learn designing
frequency dividers using flip-flops
Equipment: Components:
A J-K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the entries in the function
table. In the case of an R-S flip-flop, the input combination S = R = 1 is prohibited. In the case of a J-K flip-
flop with active HIGH inputs, the output of the flip-flop toggles, that is, it goes to the other state, for J =
K = 1 . The output toggles. Thus, a J-K flip-flop overcomes the problem of a forbidden input combination
of the R-S flip-flop. This is achieved by a minor addition in the R-S flip flop circuit. Notice in the figure
that the Q output is connected back to the input of gate G2. and the Q output is connected back to
It is often necessary to clear a flip-flop to a logic ‘0’ state (Qn = 0) or preset it to a logic ‘1’ state (Qn =1 ).
An example of how this is realized is shown in Fig. The flip-flop is cleared (that is, Qn = 0) whenever the
CLEAR input is ‘0’ and the PRESET input is ‘1’. The flip-flop is preset to the logic ‘1’ state whenever the
PRESET input is ‘0’ and the CLEAR input is ‘1’. Here, the CLEAR and PRESET inputs are active when LOW.
It is evident from the function table that, whenever the PRESET input is active, the output goes to the ‘1’
state irrespective of the status of the clock, J and K inputs. Similarly, when the flip-flop is cleared, that is,
the CLEAR input is active, the output goes to the ‘0’ state irrespective of the status of the clock, J and K
inputs. In a flip-flop of this type, both PRESET and CLEAR inputs should not be made active at the same
time.
For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip
flops to continue to divide by two One flip-flop will divide fin by 2, two flip-flops will divide fin by 4 (and
so on). A side benefit of frequency division is that the output has an exact 50% duty cycle.
Task 2:
Construct a ÷2 and ÷4 frequency divider using the flip-flops provided to you.
o For this task set your clock input to 100 Hz using the digital function generator.
o Verify the frequency through measurements using oscilloscope measurement set
readings.
o Also observe the output waveforms (÷2 , ÷4) using oscilloscope.