UART
UART
---
**A:**
- **UART** (Universal Asynchronous Receiver/Transmitter) is a hardware device for **asynchronous serial communication**.
- **Asynchronous**: No shared clock signal; relies on pre-agreed **baud rate** for timing.
- **Point-to-Point**: Uses two unidirectional lines: **TX** (transmit) and **RX** (receive).
- **Idle State**: Logic high (1). Communication starts with a **start bit** (logic low, 0), followed by data bits, parity (optional), and stop bits
(logic high).
- **Key Features**:
- Full-duplex communication.
---
- **Stop Bits**: 1, 1.5, or 2 bits (logic high), marks the end of the frame.
---
- **Formula**:
\[
\]
Microcontrollers program this divisor into a **baud rate register** (e.g., UBRR in AVR).
\[
\text{Divisor} = \frac{16,000,000}{16 \times 115200} \approx 8.68 \rightarrow \text{Use 8 or 9 with fractional divisor}.
\]
---
**A:**
- **Overrun Error**: New data received before the previous data is read (buffer overflow).
---
**A:**
- **Hardware (RTS/CTS)**:
- **Software (XON/XOFF)**:
- **XOFF (0x13)**: Receiver sends to pause transmission.
---
**A:**
|--------------------|-------------------|-------------------|-------------------|-------------------|
| **Clock** | Asynchronous | Async/Sync | Synchronous | Synchronous |
| **Lines** | TX, RX | TX, RX, XCK (sync)| SCLK, MOSI, MISO, SS | SDA, SCL |
---
**A:**
- **TTL UART**:
- **RS232**:
---
**A:**
```c
UBRR0L = divisor;
```
---
**A:**
---
**A:**
- **Direct Memory Access (DMA)** offloads data transfer between UART and memory.
**A:**
**A:**
- Address byte wakes target slave; data bytes follow until next address.
---
### **Summary**
UART is foundational in embedded systems for simple, low-speed communication. Mastery of frame structure, baud rate calculation, error
handling, and debugging is critical. Understanding advanced features like DMA and multi-processor modes demonstrates depth. Always
emphasize practical considerations (e.g., clock accuracy, voltage levels) in interviews.