The Intel 8085 microprocessor has a rich instruction set, categorized into different types based on their operations.
Below is a list of instructions,
1. Data Transfer Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
MOV r1, r2 Move data from r2 to r1 1 (F) R.A.M None
MOV r, M Move data from memory to register 2 (F, R) R.I.A.M None
MOV M, r Move data from register to memory 2 (F, W) R.I.A.M None
MVI r, data Move Imm data to register 2 (F, R) Imm None
MVI M, data Move Imm data to memory 3 (F, R, W) Imm None
LXI rp, data 16 Load Imm 16-bit data to register pair 3 (F, R, R) Imm None
LDA addr Load accumulator from memory address 4 (F, R, R, R) D.A.M None
STA addr Store accumulator to memory address 4 (F, R, R, W) D.A.M None
LHLD addr Load H and L registers from memory address 5 (F, R, R, R, R) D.A.M ( None
SHLD addr Store H and L registers to memory address 5 (F, R, R, W, W) D.A.M None
LDAX rp Load accumulator from memory location pointed
2 (F, by
R) R.I.A.M None
STAX rp Store accumulator to memory location pointed
2 (F,
byW) R.I.A.M None
XCHG Exchange contents of H and L with D and E 1 (F) R.A.M None
2. Arithmetic Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
ADD r Add register to accumulator 1 (F) R.A.M All
ADD M Add memory to accumulator 2 (F, R) R.I.A.M All
ADI data Add Imm data to accumulator 2 (F, R) Imm All
ADC r Add register with carry to accumulator 1 (F) R.A.M All
ADC M Add memory with carry to accumulator 2 (F, R) R.I.A.M All
ACI data Add Imm data with carry to accumulator 2 (F, R) Imm All
SUB r Subtract register from accumulator 1 (F) R.A.M All
SUB M Subtract memory from accumulator 2 (F, R) R.I.A.M All
SUI data Subtract Imm data from accumulator 2 (F, R) Imm All
SBB r Subtract register with borrow from accumulator
1 (F) R.A.M All
SBB M Subtract memory with borrow from accumulator
2 (F, R) R.I.A.M All
SBI data Subtract Imm data with borrow from accumulator
2 (F, R) Imm All
INR r Increment register 1 (F) R.A.M All except Carry
INR M Increment memory 3 (F, R, W) R.I.A.M All except Carry
DCR r Decrement register 1 (F) R.A.M All except Carry
DCR M Decrement memory 3 (F, R, W) R.I.A.M All except Carry
INX rp Increment register pair 1 (F) R.A.M None
DCX rp Decrement register pair 1 (F) R.A.M None
DAD rp Add register pair to H and L 3 (F, R, R) R.A.M Carry
DAA Decimal adjust accumulator 1 (F) Implied All
3. Logical Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
ANA r AND register with accumulator 1 (F) R.A.M All
ANA M AND memory with accumulator 2 (F, R) R.I.A.M All
ANI data AND Imm data with accumulator 2 (F, R) Imm All
ORA r OR register with accumulator 1 (F) R.A.M All
ORA M OR memory with accumulator 2 (F, R) R.I.A.M All
ORI data OR Imm data with accumulator 2 (F, R) Imm All
XRA r XOR register with accumulator 1 (F) R.A.M All
XRA M XOR memory with accumulator 2 (F, R) R.I.A.M All
XRI data XOR Imm data with accumulator 2 (F, R) Imm All
CMP r Compare register with accumulator 1 (F) R.A.M All
CMP M Compare memory with accumulator 2 (F, R) R.I.A.M All
CPI data Compare Imm data with accumulator 2 (F, R) Imm All
RLC Rotate accumulator left 1 (F) Implied Carry
RRC Rotate accumulator right 1 (F) Implied Carry
RAL Rotate accumulator left through carry 1 (F) Implied Carry
RAR Rotate accumulator right through carry 1 (F) Implied Carry
CMA Complement accumulator 1 (F) Implied None
CMC Complement carry flag 1 (F) Implied Carry
STC Set carry flag 1 (F) Implied Carry
4. Branching Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
JMP addr Unconditional jump to address 3 (F, R, R) D.A.M None
JZ addr Jump to address if zero flag is set 3 (F, R, R) D.A.M None
JNZ addr Jump to address if zero flag is not set 3 (F, R, R) D.A.M None
JC addr Jump to address if carry flag is set 3 (F, R, R) D.A.M None
JNC addr Jump to address if carry flag is not set 3 (F, R, R) D.A.M None
JP addr Jump to address if sign flag is not set 3 (F, R, R) D.A.M None
JM addr Jump to address if sign flag is set 3 (F, R, R) D.A.M None
JPE addr Jump to address if parity flag is set 3 (F, R, R) D.A.M None
JPO addr Jump to address if parity flag is not set 3 (F, R, R) D.A.M None
CALL addr Call subroutine at address 5 (F, R, R, W, W) D.A.M None
RET Return from subroutine 3 (F, R, R) Implied None
RZ Return if zero flag is set 3 (F, R, R) Implied None
RNZ Return if zero flag is not set 3 (F, R, R) Implied None
RC Return if carry flag is set 3 (F, R, R) Implied None
RNC Return if carry flag is not set 3 (F, R, R) Implied None
RP Return if sign flag is not set 3 (F, R, R) Implied None
RM Return if sign flag is set 3 (F, R, R) Implied None
RPE Return if parity flag is set 3 (F, R, R) Implied None
RPO Return if parity flag is not set 3 (F, R, R) Implied None
5. Control Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
NOP No operation 1 (F) Implied None
HLT Halt 1 (F) Implied None
DI Disable interrupts 1 (F) Implied None
EI Enable interrupts 1 (F) Implied None
RIM Read interrupt mask 1 (F) Implied None
SIM Set interrupt mask 1 (F) Implied None
6. Stack Operations
Instruction Operation Machine Cycles Addressing Mode Flags Affected
PUSH rp Push register pair onto stack 3 (F, W, W) R.A.M None
POP rp Pop register pair from stack 3 (F, R, R) R.A.M None
PUSH PSW Push accumulator and flags onto stack 3 (F, W, W) R.A.M None
POP PSW Pop accumulator and flags from stack 3 (F, R, R) R.A.M All
XTHL Exchange H and L with top of stack 5 (F, R, R, W, W) R.I.A.M None
SPHL Copy H and L to stack pointer 1 (F) R.A.M None
7. I/O Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
IN port Input from port to accumulator 3 (F, R, R) D.A.M None
OUT port Output from accumulator to port 3 (F, R, W) D.A.M None
8. Special Instructions
Instruction Operation Machine Cycles Addressing Mode Flags Affected
RST n Restart (call subroutine at n*8) 3 (F, W, W) Implied None
