STM32C091xB/xC

STM32C092xB/xC
Arm®Cortex®-M0+ 32-bit MCU, 256 KB flash, 36 KB RAM,
4 x USART, timers, ADC, FDCAN, comm. I/Fs, 2-3.6V
Datasheet - production data

Features
• Includes ST state-of-the-art patented
technology
TSSOP20 LQFP32 UFQFPN28
• Core: Arm® 32-bit Cortex®-M0+ CPU, (6.5 × 4.4 mm) (7 × 7 mm) (4 × 4 mm)
UFBGA64
(5 × 5 mm)
frequency up to 48 MHz LQFP48 UFQFPN32
(7 × 7 mm)
• -40°C to 85°C/105°C/125°C operating (5 × 5 mm)
temperature LQFP64 UFQFPN48
(10 x 10 mm) (7 × 7 mm)
WLCSP24
• Memories (2.61 x 1.73 mm)
– Up to 256 Kbytes of flash memory with
protection and securable area • Communication interfaces
– Two I2C-bus interface supporting Fast-
– Up to 36 Kbytes of SRAM with hardware
parity check mode Plus (1 Mbit/s) with extra current
sink; one supporting SMBus/PMBus™ and
• CRC calculation unit wake-up from Stop mode
• Reset and power management – Four USARTs with master/slave
– Voltage range: 2.0 V to 3.6 V synchronous SPI; one supporting ISO7816
– Power-on / power-down reset (POR/PDR) interface, LIN, IrDA capability, auto baud
– Programmable brownout reset (BOR) rate detection and wake-up feature
– Low-power modes: – Two SPIs (24 Mbit/s) with 4- to 16-bit
Sleep, Stop, Standby, Shutdown programmable bitframe, one multiplexed
with I²S interface; four extra SPIs through
• Clock management USARTs
– 4 to 48 MHz crystal oscillator
• One FDCAN controller (STM32C092xx only)
– 32 kHz crystal oscillator with calibration
– Internal 48 MHz RC oscillator (±1 %) • Development support: serial wire debug (SWD)
– Internal 32 kHz RC oscillator (±5 %) • 96-bit unique ID
• Up to 61 fast I/Os • All packages ECOPACK 2 compliant
– All mappable on external interrupt vectors
Table 1. Device summary
– All 5 V-tolerant
Reference Part number
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 µs ADC (up to 19 ext. channels) STM32C091FB, STM32C091GB,
STM32C091KB, STM32C091CB,
– Conversion range: 0 to 3.6 V
STM32C091RB, STM32C091FC,
STM32C091xx
• 10 timers: 16-bit for advanced motor control, STM32C091EC, STM32C091GC,
one 32-bit timer and five 16-bit general- STM32C091KC, STM32C091CC,
purpose, two watchdogs, SysTick timer STM32C091RC

• Calendar RTC with alarm STM32C092FB, STM32C092GB,

STM32C092KB, STM32C092CB,
STM32C092RB, STM32C092FC,
STM32C092xx
STM32C092EC, STM32C092GC,
STM32C092KC, STM32C092CC,
STM32C092RC

December 2024 DS14720 Rev 1 1/123

This is information on a product in full production. www.st.com
Contents STM32C091xB/xC STM32C092xB/xC

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.1 Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 15
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 21
3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 24
3.15.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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3.15.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.15.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18 Universal synchronous/asynchronous receiver transmitter (USART) . . . 26
3.19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.21 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.21.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 29

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 48
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 48
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.6 Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.9 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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5.3.14 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.15 Extended interrupt and event controller input (EXTI) characteristics . . . 77
5.3.16 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.19 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . . 84

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2 TSSOP20 package information (YA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3 WLCSP24 package information (B0Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.4 UFQFPN28 package information (A0B0) . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.5 LQFP32 package information (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.6 UFQFPN32 package information (A0B8) . . . . . . . . . . . . . . . . . . . . . . . . 104
6.7 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.8 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . .110
6.9 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
6.10 UFBGA64 package information (A019) . . . . . . . . . . . . . . . . . . . . . . . . . .115
6.11 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
6.11.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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STM32C091xB/xC STM32C092xB/xC List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32C091xB/xC and STM32C092xB/xC device features and peripheral counts . . . . . . 10
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 14
Table 4. Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Terms and symbols used in the pin assignment table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Port A alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Port A alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Port B alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Port B alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Port C alternate function mapping (AF0 to AF7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Port C alternate function mapping (AF8 to AF15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Port D alternate function mapping (AF0 to AF7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Port F alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 28. Current consumption in Run mode from flash memory at different die temperatures . . . . 51
Table 29. Current consumption in Run mode from SRAM at different die temperatures . . . . . . . . . . 52
Table 30. Typical current consumption in Run depending on code executed . . . . . . . . . . . . . . . . . . 53
Table 31. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 32. Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 33. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 34. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 35. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 36. Low-power mode wake-up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 41. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 43. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 44. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 45. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 46. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 47. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 48. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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List of tables STM32C091xB/xC STM32C092xB/xC

Table 49. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 50. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 51. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 52. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 53. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 54. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 55. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 56. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 57. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 58. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 59. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 60. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 61. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 63. USART (SPI mode) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 64. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 65. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 66. TSSOP20 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 67. WLCSP24 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 68. WLCSP24 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 69. UFQFPN28 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 70. LQFP32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 71. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 72. Tolerance of form and position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 73. Exposed pad variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 74. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 75. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 76. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 77. UFBGA64 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 78. UFBGA64 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 117
Table 79. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 80. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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STM32C091xB/xC STM32C092xB/xC List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. STM32C09xFxP TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. STM32C09xExY WLCSP24 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. STM32C09xGxU UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. STM32C09xKxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7. STM32C09xKxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. STM32C09xCxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9. STM32C09xCxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. STM32C09xRxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. STM32C09xRxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 18. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 23. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 25. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 26. ADC typical connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 27. USART timing diagram in SPI master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 28. USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 30. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 31. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 32. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 33. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 34. TSSOP20 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 35. TSSOP20 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 36. WLCSP24 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 37. Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 38. WLCSP24 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 39. UFQFPN28 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 40. UFQFPN28 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 41. LQFP32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 42. LQFP32 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 43. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 44. UFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 45. LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 46. LQFP48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 47. UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 48. UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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List of figures STM32C091xB/xC STM32C092xB/xC

Figure 49. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 50. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 51. UFBGA64 – Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 52. UFBGA64 – Footprint example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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STM32C091xB/xC STM32C092xB/xC Introduction

1 Introduction

This document provides information on STM32C091xB/xC and STM32C092xB/xC

microcontrollers, such as description, functional overview, pin assignment and definition,
electrical characteristics, packaging, and ordering codes.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32C091xB/xC and STM32C092xB/xC errata sheet ES0625.
Information on memory mapping and control registers is the subject of the reference manual
RM0490.
Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description STM32C091xB/xC STM32C092xB/xC

2 Description

The STM32C091xB/xC STM32C092xB/xC mainstream microcontrollers are based on

high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 48 MHz
frequency. Offering a high level of integration, they are suitable for a wide range of
applications in consumer, industrial and appliance domains and ready for the Internet of
Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(up to 36 Kbytes of SRAM and up to 256 Kbytes of flash program memory with read and
write protection, proprietary code protection, and securable area), DMA, an extensive range
of system functions, enhanced I/Os, and peripherals. The devices offer standard
communication interfaces (two I2Cs, two SPI / one I2S, one FDCAN, and four USARTs), one
12-bit ADC (2.5 MSps) with up to 19 channels, a low-power RTC, an advanced control PWM
timer, five general-purpose 16-bit timers, a 32-bit general-purpose timer, two watchdog
timers, and a SysTick timer.
The devices operate within ambient temperatures from -40 to 125°C and with supply
voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with power-saving
modes allows the design of low-power applications.
The devices are housed in packages with 20 to 64 pins.

Table 2. STM32C091xB/xC and STM32C092xB/xC device features and peripheral counts

STM32C09x
Peripheral
_FB / _FC _EC _GB / _GC _KB / _KC _CB / _CC _RB / _RC

Flash memory (Kbyte) 128/256 256 128/256 128/256(1)

SRAM (Kbyte) 36 (STM32C091xx) / 30 (STM32C092xx)
Advanced control 1 (16-bit)
1 (32-bit)
Timers

General-purpose
5 (16-bit)
SysTick 1
Watchdog 2
SPI [I2S](2) 2 [1] + 4 extra through USARTs
interfaces
Comm.

I2C 2

USART 4
RTC Yes
FDCAN No (STM32C091xx) / Yes (STM32C092xx)
GPIOs (all 5V-tolerant) 18 22 26 30 45 61
DMA channels 7
Wakeup pins 4 5 5 5 5 6
12-bit ADC channels
11 + 4 13 + 4 13 + 4 14 + 4 17 + 4 19 + 4
(ext. + int.)
Max. CPU frequency 48 MHz

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STM32C091xB/xC STM32C092xB/xC Description

Table 2. STM32C091xB/xC and STM32C092xB/xC device features and peripheral counts

STM32C09x
Peripheral
_FB / _FC _EC _GB / _GC _KB / _KC _CB / _CC _RB / _RC

Operating voltage 2.0 to 3.6 V

Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Operating temperature(3)
Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
LQFP32 LQFP48 LQFP64
Packages TSSOP20 WLCSP24 UFQFPN28
UFQFPN32 UFQFPN48 UFBGA64

Bootloader USART1, USART2, I2C1, I2C2, SPI1, SPI2, FDCAN(4)

1. Only 256 KB version is available for parts in UFBGA64 package.

2. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.
3. Depends on order code. Refer to Section 7: Ordering information for details.
4. Only available on STM32C092xx, except for the TSSOP20 package.

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Description STM32C091xB/xC STM32C092xB/xC

Figure 1. Block diagram

POWER
DMAMUX
Voltage
VCORE regulator
SWCLK
SWDIO SWD DMA
VDDIO1
as AF
VDDA VDD/VDDA
Flash memory VSS/VSSA
I/F VDD
CPU

Bus matrix
up to 256 KB
CORTEX-M0+
SUPPLY
fmax = 48 MHz SUPERVISION
SRAM POR
up to 36 KB Parity POR/BOR
Reset
Int NRST
NVIC IOPORT
T sensor

GPIOs HSI48
RC 48 MHz
PAx Port A
LSI RC 32 kHz XTAL OSC OSC_IN
4-48 MHz OSC_OUT
PBx Port B
HSE
decoder

IWDG
PCx Port C

PDx Port D RCC LSE LSE OSCX_IN

XTAL 32 kHz
Reset & clock control OSCX_OUT
CRC
PFx Port F
AHB

RTC_OUT
System and RTC RTC_REFIN
peripheral RTC_TS
EXTI clocks

from peripherals AHB-to-APB

TIM1 2 int. channels
APB BKIN, ETR input as AF
VREF+ TIM2 (32-bit) 4 ch., ETR as AF
ADC I/F
19x IN
TIM3 4 ch., ETR as AF

MOSI/SD SYSCFG
APB

TIM14 1 channel as AF
MISO/MCK
SCK/CK SPI1/I2S
2 channels, BKIN
NSS/WS as AF TIM15
as AF
PWRCTRL
MOSI, MISO TIM16 &
TIMER 17
16/17 1 channel as AF
SPI2
SCK, NSS
WWDG
IRTIM IR_OUT
(1)
RX, TX FDCAN RX, TX, CTS, RTS
DBGMCU USART1 to 4 as AF

I2C1 SCL, SDA, SMBA

as AF

I2C2 SCL, SDA

Power domain of analog blocks : VDD VDDA VDDIO1

MSv66178V2

1. Only available on STM32C092xx

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STM32C091xB/xC STM32C092xB/xC Functional overview

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:
• a simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32C091xB/xC and STM32C092xB/xC devices are
compatible with Arm tools and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.13.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded flash memory

STM32C091xB/xC and STM32C092xB/xC devices feature up to 256 Kbytes of embedded
flash memory available for storing code and data.

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Functional overview STM32C091xB/xC STM32C092xB/xC

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in
RAM and bootloader selection are disabled. This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

User execution Debug, boot from RAM or boot

Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase

Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A
System 1 Yes No No Yes No No
memory 2 Yes No No N/A N/A N/A
Option 1 Yes Yes Yes Yes Yes Yes
bytes 2 Yes No No N/A N/A N/A

• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU as instruction code, while all other accesses
(DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional
option bit (PCROP_RDP) determines whether the PCROP area is erased or not when
the RDP protection is changed from Level 1 to Level 0.

3.3.1 Securable area

A part of the Flash memory can be hidden from the application once the code it contains is
executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot
be accessed until the system resets. The securable area generally contains the secure boot
code to execute only once at boot. This helps to isolate secret code from untrusted
application code.

3.4 Embedded SRAM

STM32C091xB/xC and STM32C092xB/xC devices have 36 Kbytes and 30 Kbytes,
respectively, of embedded SRAM with parity. Hardware parity check allows memory data
errors to be detected, which contributes to increasing functional safety of applications.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

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3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• boot from main flash memory
• boot from system memory
• boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector
option bit. If the BOOT0 pin selects the boot from the main flash memory of which the first
location is empty, the flash memory empty checker forces the boot from the system memory.
The system memory contains an embedded boot loader. It manages the flash memory
reprogramming through one of the following interfaces:
• USART on pins PA9/PA10 or PA3/PA2
• I2C-bus on pins PB6/PB7 or PB10/PB11
• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15
• FDCAN on PD0/PD1 pins, or on PB0/PB1 pins (for packages under 48 pins), of the
STM32C092xx devices (except for the TSSOP20 package)
When boot loader is executed, it configures some of the GPIOs out of their by-default high-Z
state. Refer to AN2606 for more details on the boot loader and on the GPIO configuration
when booting from the system memory.

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32C091xB/xC and STM32C092xB/xC devices require 2.0 V to 3.6 V operating
supply voltage (VDD). Several different power supplies are provided to specific peripherals:
• VDD = 2.0 V (1.96 V) to 3.6 V
VDD is the external power supply for the internal regulator and the system analog such
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
The minimum voltage of 2.0 V corresponds to power-on reset release threshold
VPOR(max). Once this threshold is crossed and power-on reset is released, the
functionality is guaranteed down to power-down reset threshold VPDR(min) of 1.96 V.

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Functional overview STM32C091xB/xC STM32C092xB/xC

• VDDA = 2.0 V (1.96 V) to 3.6 V

VDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to
VDD voltage as it is provided externally through VDD/VDDA pin.
• VDDIO1 = VDD
VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage
as it is provided externally through VDD/VDDA pin.
• VREF+ is the analog peripheral input reference voltage.
VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is
internally connected with VDD.
• VCORE is an internal supply for digital peripherals, SRAM and flash memory. It is
produced by an embedded linear voltage regulator. On top of VCORE, the flash memory
is also powered from VDD.

Figure 2. Power supply overview

VDDA domain
VREF+(1)
VREF+
VDDA A/D converter
VSSA

VDDIO1
I/O ring VDDIO1 domain

Reset block VDD domain

Temp. sensor
HSI48
Standby circuitry
VSS (Wakeup logic, VCORE domain
VSS/VSSA IWDG)
VDD LSE 32 kHz Core
VDD/VDDA VCORE
Voltage regulator SRAM
Digital
peripherals

Flash memory
RTC domain
RTC

MSv66174V2

1. Internally connected to VDD/VDDA pin on packages without VREF+ pin.

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It
can be enabled and configured through option bytes, by selecting one of four thresholds for
rising VDD and other four for falling VDD.

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3.7.3 Voltage regulator

An embedded linear voltage regulator supplies most of the digital circuitry in the device.
In Standby and Shutdown modes, the regulator is powered down and its output set in high-
impedance state, such as to bring its current consumption close to zero.

3.7.4 Low-power modes

By default, the device is in Run mode after system or power reset. It is up to the user to
select one of the low-power modes described below:

• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
In Stop mode, the device achieves the lowest power consumption while retaining the
SRAM and register contents. All clocks in the VCORE are stopped. The HSE and HSI48
oscillators stop. The HSI48 can be restarted by a peripheral with wake-up capability
requiring HSI48.
The LSE and LSI can be kept running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).
The event of exiting Stop mode enables the HSI48 oscillator and select HSISYS as
system clock.
• Standby mode
The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The regulator is switched off to power down VCORE domain.
The HSI48 RC oscillator and the HSE crystal oscillator are also powered down. The
RTC is switched off.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.
Upon entering Standby mode, register contents are lost, except for 16-bit backup
registers whose contents are kept.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wake-up event (any WKUP pin, configurable rising or falling edge), or when a
failure is detected on LSE (CSS on LSE).
• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off to power down the VCORE domain. The HSI48 and LSI RC-
oscillators and HSE crystal oscillator are also powered down. The RTC is off.
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode.
SRAM and register contents are lost.
The device exits Shutdown mode upon external reset event (NRST pin), or wake-up
event (any WKUP pin, configurable rising or falling edge).

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3.7.5 Reset mode

During and upon exiting reset, the Schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.

Table 4. Interconnect of peripherals

Interconnect
Interconnect source Interconnect action Run Sleep Stop
destination

TIMx Timer synchronization or chaining Y Y -

ADCx Conversion triggers Y Y -
TIMx
DMA Memory-to-memory transfer trigger Y Y -
ADCx TIM1 Timer triggered by analog watchdog Y Y -

RTC TIM16 Timer input channel from RTC events Y Y -

All clock sources (internal and Clock source used as input channel for
TIM14,16,17 Y Y -
external) RC measurement and trimming
CSS
RAM (parity error) TIM1,15,16,17 Timer break Y Y -

CPU (hard fault) TIM1,15,16,17 Timer break Y - -

TIM1,2,3 External trigger Y Y -
GPIO
ADC Conversion external trigger Y Y -

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3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: the following clock sources can deliver SYSCLK system clock:
– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
The HSE can also be configured in bypass mode for an external clock.
– 48 MHz high-speed internal RC oscillator (HSI48), trimmable by software.
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting two drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
• Peripheral clock sources: several peripherals (I2S, USART1, I2C1, ADC) can
operate with a clock source independent of the system clock.
• Clock security system (CSS): in the event of HSE or LSE clock failure, the system
clock is automatically switched to HSI48 or LSI, respectively. If enabled, a software
interrupt is generated. The CCS feature can be enabled by software.
• Clock output:
– MCO and MCO2 (microcontroller clock output) provides one of the internal
clocks for external use by the application.
– LSCO (low speed clock output) provides LSI or LSE in all low-power modes.
Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 48 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.
Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with
single-AHB architecture.

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With 7 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The unit includes an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request originates from
any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controller. Each channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
DMAMUX may also be used as a DMA request generator from programmable events on its
input trigger signals.

3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.
The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving

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time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.
If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.
Features of the NVIC:
• Low-latency interrupt processing
• 4 priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wake-up from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising,
and falling edge detector capability. Any GPIO and a few peripheral signals can be
connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32C091xB/xC and
STM32C092xB/xC devices. The ADC has up to 19 external channels and 2 internal

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channels (temperature sensor, voltage reference). It performs conversions in single-shot or

scan mode. In scan mode, automatic conversion is performed on a selected group of analog
inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 2.5 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole VDD supply
range.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factory-
calibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,
accessible in read-only mode.

Table 5. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF7568-0x1FFF7569
VDDA = VREF+ = 3.0 V (± 10 mV)

3.14.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually
precisely measured for each part by ST during production test and stored in the part’s
engineering bytes. It is accessible in read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value name Description Memory address

Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF756A-0x1FFF756B
VDDA = VREF+ = 3.0 V (± 10 mV)

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3.15 Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two watchdog
timers and a SysTick timer. Table 7 compares features of the advanced-control and
general-purpose timers.

Table 7. Timer feature comparison

Maximum DMA Capture/ Comple-
Counter Counter Prescaler
Timer Timer type operating request compare mentary
resolution type factor
frequency generation channels outputs

Advanced- Up, down, Integer from 4

TIM1 16-bit 48 MHz Yes 3
control up/down 1 to 216 +2 internal
General- Up, down, Integer from
TIM2 32-bit 48 MHz Yes 4 -
purpose up/down 1 to 216
General- Up, down, Integer from
TIM3 16-bit 48 MHz Yes 4 -
purpose up/down 1 to 216
General- Integer from
TIM14 16-bit Up 48 MHz No 1 -
purpose 1 to 216
General- Integer from
TIM15 16-bit Up 48 MHz Yes 2 1
purpose 1 to 216
TIM16 General- Integer from
16-bit Up 48 MHz Yes 1 1
TIM17 purpose 1 to 216

3.15.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• input capture
• output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• one-pulse mode output
On top of these, there are two internal channels that can be used.
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.15.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.

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3.15.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)

There are six synchronizable general-purpose timers embedded in the device (refer to
Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs
or act as a simple timebase.
• TIM2, TIM3
These are full-featured general-purpose timers:
– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler
– TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler
They have four independent channels for input capture/output compare, PWM or one-
pulse mode output. They can operate in combination with other general-purpose timers
via the Timer Link feature for synchronization or event chaining. They can generate
independent DMA request and support quadrature encoders. Their counter can be
frozen in debug mode.
• TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.
• TIM15, TIM16, TIM17
These are general-purpose timers featuring:
– 16-bit auto-reload upcounter and 16-bit prescaler
– 2 channels and 1 complementary channel for TIM15
– 1 channel and 1 complementary channel for TIM16 and TIM17
All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.

3.15.3 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.

3.15.4 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.

3.15.5 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.

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Features of SysTick timer:

• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source

3.16 Real-time clock (RTC)

The devices embed an RTC located in the RTC domain and supplied from VCORE.
The RTC is an independent BCD timer/counter.
Features of the RTC:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Programmable alarm
• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with
a master clock
• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be
used to improve the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature to save a calendar snapshot, triggered by an event on the
timestamp pin
• Multiple clock sources and references:
– a 32.768 kHz external crystal (LSE)
– an external resonator or oscillator (LSE)
– the internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
– the high-speed external clock (HSE) divided by 32
The RTC operates in Run, Sleep, and Stop mode.
RTC events (Alarm, Timestamp) can generate an interrupt and wake the device up from the
low-power modes.

3.17 Inter-integrated circuit interface (I2C)

The devices embed two I2C peripheral. Refer to Table 8 for the features.
The I2C peripheral handles communication between the microcontroller and the serial
I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

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Features of the I2C peripheral:

• I2C-bus specification and user manual rev. 5 compatibility:
– Target and controller modes, multicontroller capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit target addresses
– Programmable setup and hold times
– Clock stretching
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C-bus
communication speed to be independent of the PCLK reprogramming
• Wake-up from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 8. I2C implementation

I2C features(1) I2C1 I2C2

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X
Programmable analog and digital noise filters X X
SMBus/PMBus hardware support X -
Independent clock X -
Wakeup from Stop mode on address match X -
1. X: supported

3.18 Universal synchronous/asynchronous receiver transmitter

(USART)
The devices embed four universal synchronous/asynchronous receivers/transmitters that
communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, synchronous SPI communication and single-wire half-

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duplex communication mode. Some can also support SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have
a clock domain independent of the CPU clock, which allows them to wake up the MCU from
Stop mode. The wake-up events from Stop mode are programmable and can be:
• start bit detection
• any received data frame
• a specific programmed data frame
All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

USART2/USART3
USART modes/features(1) USART1
/USART4

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
SPI emulation master/slave (synchronous mode) X X
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wake-up from Stop mode X -
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection X -
Driver Enable X X
1. X: supported

3.19 Serial peripheral interface (SPI)

The devices contain two SPI running at up to 24 Mbits/s in master and slave modes. It
supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight
master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI
peripherals support NSS pulse mode, TI mode and hardware CRC calculation.
The SPI peripherals can be served by the DMA controller.
The I2S interface mode of the SPI peripheral (if supported, see the following table) supports
four different audio standards can operate as master or slave, in half-duplex communication
mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, it can output a clock for an external audio component at 256 times the sampling
frequency.

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Functional overview STM32C091xB/xC STM32C092xB/xC

Table 10. SPI/I2S implementation

SPI features(1) SPI1 SPI2

Hardware CRC calculation X X

Rx/Tx FIFO X X
NSS pulse mode X X
I2S mode X -
TI mode X X
1. X = supported.

3.20 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of a CAN module and a message
RAM.
The CAN module is compliant with ISO 11898-1 (CAN protocol specification version 2.0 part
A, B) and CAN FD protocol specification version 1.0.
The 1-Kbyte message RAM implements filters, receive FIFOs, receive buffers, transmit
event FIFOs, and transmit buffers.

3.21 Development support

3.21.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.

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4 Pinouts, pin description and alternate functions

Figure 3. STM32C09xFxP TSSOP20 pinout

Top view
PB7/PB8 1 20 PB3/PB4/PB5/PB6
PC14-OSCX_IN 2 19 PA14-BOOT0/PA15
PC15-OSCX_OUT 3 18 PA13
VDD/VDDA 4 17 PA12 [PA10]
VSS/VSSA 5 16 PA11 [PA9]
PF2-NRST 6
TSSOP20 15 PB0/PB1/PB2/PA8
PA0 7 14 PA7
PA1 8 13 PA6
PA2 9 12 PA5
PA3 10 11 PA4

MSv66180V1

Figure 4. STM32C09xExY WLCSP24 ballout

Top view
1 2 3 4 5 6 7

PC14-
PB3/ PB4/
A PA15 OSCX_
PB5 PB6
IN
PC15-
PA14- PB7/
B OSCX_
BOOT0 PB8
OUT
VDD/
C PB1 PA13 PA0
VDDA

VSS/
D PA4
VSSA

PA12 PF2-
E PB0 PA1
[PA10] NRST

PA11
F PA6 PA3
[PA9]

PB2/
G PA7 PA5 PA2
PA8

MS57541V1

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Pinouts, pin description and alternate functions STM32C091xB/xC STM32C092xB/xC

Figure 5. STM32C09xGxU UFQFPN28 pinout

Top view

PA15
PB8
PB7
PB6
PB5
PB4
PB3
28
27
26
25
24
23
22
PC14-OSCX_IN 1 21 PA14-BOOT0
PC15-OSCX_OUT 2 20 PA13
VDD/VDDA 3 19 PA12 [PA10]
VSS/VSSA 4 UFQFPN28 18 PA11 [PA9]
PF2-NRST 5 17 PC6
PA0 6 16 PA8
PA1 7 15 PB1

10

12
13
14
11
8
9

PB0
PA2
PA3
PA4
PA5
PA6
PA7
MSv65937V1

Figure 6. STM32C09xKxT LQFP32 pinout

PA14-BOOT0
PA15
Top view
PB8
PB7
PB6
PB5

PB3
PB4
32
31
30
29
28
27
26
25

PB9 1 24 PA13
PC14-OSCX_IN 2 23 PA12 [PA10]
PC15-OSCX_OUT 3 22 PA11 [PA9]
VDD/VDDA 4 21 PA10
VSS/VSSA 5
LQFP32 20 PC6
PF2-NRST 6 19 PA9
PA0 7 18 PA8
PA1 8 17 PB2
10

12
13
14
15
16
11
9

PB0
PB1
PA2
PA3
PA4
PA5
PA6
PA7

MSv65935V1

Figure 7. STM32C09xKxU UFQFPN32 pinout

PA14-BOOT0

Top view
PA15
PB8
PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25

PB9 1 24 PA13
PC14-OSCX_IN 2 23 PA12 [PA10]
PC15-OSCX_OUT 3 22 PA11 [PA9]
VDD/VDDA 4 21 PA10
VSS/VSSA 5 UFQFPN32 20 PC6
PF2-NRST 6 19 PA9
PA0 7 Exposed pad 18 PA8
PA1 8 17 PB2
10

12
13
14
15
16
11
9

VSS
PB0
PB1
PA2
PA3
PA4
PA5
PA6
PA7

MSv65936V1

30/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Pinouts, pin description and alternate functions

Figure 8. STM32C09xCxT LQFP48 pinout

Top view

PA15
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
PC13 1 36 PA14-BOOT0
PC14-OSCX_IN 2 35 PA13
PC15-OSCX_OUT 3 34 PA12 [PA10]
PF3 4 33 PA11 [PA9]
VREF+ 5 32 PA10
VDD/VDDA 6 31 PC7
VSS/VSSA 7
LQFP48 30 PC6
PF0-OSC_IN 8 29 PA9
PF1-OSC_OUT 9 28 PA8
PF2-NRST 10 27 PB15
PA0 11 26 PB14
PA1 12 25 PB13
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10

PB12
PA2
PA3
PA4
PA5
PA6
PA7

PB11
MSv65933V1

Figure 9. STM32C09xCxU UFQFPN48 pinout

Top view
PA15
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

PC13 1 36 PA14-BOOT0
PC14-OSCX_IN 2 35 PA13
PC15-OSCX_OUT 3 34 PA12 [PA10]
PF3 4 33 PA11 [PA9]
VREF+ 5 32 PA10
VDD/VDDA 6 31 PC7
VSS/VSSA 7 UFQFPN48 30 PC6
PF0-OSC_IN 8 29 PA9
PF1-OSC_OUT 9 28 PA8
PF2-NRST 10 27 PB15
PA0 11 Exposed pad 26 PB14
PA1 12 25 PB13
13
14
15
16
17
18
19
20
21
22
23
24

VSS
PB0
PB1
PB2
PB10

PB12
PA2
PA3
PA4
PA5
PA6
PA7

PB11

MSv66934V1

DS14720 Rev 1 31/123

37
Pinouts, pin description and alternate functions STM32C091xB/xC STM32C092xB/xC

Figure 10. STM32C09xRxT LQFP64 pinout

PC10

PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC9
PB9
PB8
PB7
PB6
PB5
PB4
PB3
Top view

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PC11 1 48 PC8
PC12 2 47 PA15
PC13 3 46 PA14-BOOT0
PC14-OSCX_IN 4 45 PA13
PC15-OSCX_OUT 5 44 PA12 [PA10]
PF3 6 43 PA11 [PA9]
VREF+ 7 42 PA10
VDD/VDDA 8 41 PD9
VSS/VSSA 9 LQFP64 40 PD8
PF0-OSC_IN 10 39 PC7
PF1-OSC_OUT 11 38 PC6
PF2-NRST 12 37 PA9
PC0 13 36 PA8
PC1 14 35 PB15
PC2 15 34 PB14
PC3 16 33 PB13
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC4
PC5
PB0
PB1
PB2
PB10

PB12
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PB11
MSv66176V1

Figure 11. STM32C09xRxI UFBGA64 pinout

1 2 3 4 5 6 7 8
Top view

A PC11 PC10 PB7 PB6 PD6 PD2 PD0 PC8

PC15-
PA12
B OSCX PC12 PB8 PB3 PD5 PD1 PC9
[PA10]
_OUT

PC14-
PA14- PA11
C OSCX PC13 PB9 PB4 PD4 PA15
BOOT0 [PA9]
_IN

VDD/
D VDDA
VREF+ PF3 PB5 PD3 PA10 PA13 PD9

VSS/ PF2-
E VSSA NRST
PC0 PA7 PC7 PA9 PC6 PD8

PF0-
F OSC_IN
PC1 PA3 PA6 PB0 PB14 PB15 PA8

PF1-
G OSC PC2 PA2 PA5 PB1 PB10 PB12 PB13
_OUT

H PC3 PA0 PA1 PA4 PC4 PC5 PB2 PB11

MSv66175V1

32/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Pinouts, pin description and alternate functions

Table 11. Terms and symbols used in the pin assignment table
Column Symbol Definition

Terminal name corresponds to its by-default function at reset, unless otherwise specified in
Pin name
parenthesis under the pin name.
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
RST Reset pin with embedded weak pull-up resistor
Options for FT I/Os
_f I/O, Fm+ capable
I/O structure

_a I/O, with analog switch function

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions

Table 12. Pin assignment and description

Pin number
I/O structure
Pin type

Pin name
UFQFPN28

UFQFPN32

UFQFPN48
WLCSP24

UFBGA64

Notes
TSSOP20

Additional
LQFP32

LQFP48

LQFP64

(function Alternate functions

functions
after reset)

- - - - - 1 A1 PC11 I/O FT - USART3_RX, USART4_RX, TIM1_CH4 -

- - - - - 2 B2 PC12 I/O FT - TIM14_CH1 -

RTC_TS,
- - - - 1 3 C2 PC13 I/O FT - TIM1_ETR, TIM1_BKIN RTC_OUT1,
WKUP2

USART1_TX, TIM1_ETR, TIM1_BKIN2,

PC14- USART3_TX, IR_OUT,
2 A7 1 2 2 4 C1 OSCX_IN(PC I/O FT_f - USART2_RTS/USART2_DE/USART2_CK, OSCX_IN
14) TIM17_CH1, TIM3_CH2, SPI2_NSS,
FDCAN1_TX, I2C1_SDA, EVENTOUT

PC15-
OSC32_EN, OSC_EN, TIM1_ETR,
3 B6 2 3 3 5 B1 OSCX_OUT( I/O FT - OSCX_OUT
TIM3_CH3, TIM15_BKIN
PC15)

DS14720 Rev 1 33/123

37
Pinouts, pin description and alternate functions STM32C091xB/xC STM32C092xB/xC

Table 12. Pin assignment and description (continued)

Pin number

I/O structure
Pin type
Pin name
UFQFPN28

UFQFPN32

UFQFPN48
WLCSP24

UFBGA64

Notes
TSSOP20

Additional
LQFP32

LQFP48

LQFP64
(function Alternate functions
functions
after reset)

- - - - 4 6 D3 PF3 I/O FT - - -

- - - - 5 7 D2 VREF+ S - - - -

4 C7 3 4 6 8 D1 VDD S - - - -
5 D6 4 5 7 9 E1 VSS S - - - -

PF0-
- - - - 8 10 F1 OSC_IN(PF0 I/O FT - TIM14_CH1 OSC_IN
)

PF1-
- - - - 9 11 G1 OSC_OUT(P I/O FT - OSC_EN, TIM15_CH1N OSC_OUT
F1)

RST, (1)
6 E7 5 6 10 12 E2 PF2-NRST I/O MCO, TIM1_CH4 NRST
FT

- - - - - 13 E3 PC0 I/O FT - USART4_RX, USART3_TX -

- - - - - 14 F2 PC1 I/O FT - USART4_TX, TIM15_CH1, USART3_RX -

- - - - - 15 G2 PC2 I/O FT - SPI2_MISO, TIM15_CH2, FDCAN1_RX -

- - - - - 16 H1 PC3 I/O FT - SPI2_MOSI, FDCAN1_TX -

SPI2_SCK, USART2_CTS/USART2_NSS,
ADC_IN0,
7 C5 6 7 11 17 H2 PA0 I/O FT_a - TIM16_CH1, TIM2_ETR/TIM2_CH1,
WKUP1
USART1_TX, TIM1_CH1, USART4_TX

SPI1_SCK/I2S1_CK,
USART2_RTS/USART2_DE/USART2_CK,
8 E5 7 8 12 18 H3 PA1 I/O FT_a - TIM17_CH1, TIM2_CH2, USART1_RX, ADC_IN1
TIM1_CH2, I2C1_SMBA, EVENTOUT,
TIM15_CH1N, USART4_RX

SPI1_MOSI/I2S1_SD, USART2_TX, ADC_IN2,

9 G7 8 9 13 19 G3 PA2 I/O FT_a - TIM16_CH1N, TIM3_ETR, TIM1_CH3, WKUP4,
TIM2_CH3, TIM15_CH1 LSCO

SPI2_MISO, USART2_RX, TIM1_CH1N,

10 F6 9 10 14 20 F3 PA3 I/O FT_a - TIM2_CH4, TIM1_CH4, EVENTOUT, ADC_IN3
TIM15_CH2

SPI1_NSS/I2S1_WS, USART2_TX,
ADC_IN4,
- - - - 15 21 H4 PA4 I/O FT_a - TIM1_CH2N, SPI2_MOSI, TIM14_CH1,
RTC_OUT2
TIM17_CH1N, EVENTOUT

ADC_IN4,
SPI1_NSS/I2S1_WS, USART2_TX,
RTC_TS,
11 D2 10 11 - - - PA4 I/O FT_a - TIM1_CH2N, SPI2_MOSI, TIM14_CH1,
RTC_OUT1,
TIM17_CH1N, EVENTOUT
WKUP2

SPI1_SCK/I2S1_CK, USART2_RX,
12 G5 11 12 16 22 G4 PA5 I/O FT_a - TIM1_CH3N, TIM2_ETR/TIM2_CH1, ADC_IN5
USART3_TX, TIM1_CH1, EVENTOUT

34/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin number

I/O structure
Pin type
Pin name
UFQFPN28

UFQFPN32

UFQFPN48
WLCSP24

UFBGA64

Notes
TSSOP20

Additional
LQFP32

LQFP48

LQFP64
(function Alternate functions
functions
after reset)

SPI1_MISO/I2S1_MCK, TIM3_CH1,
13 F4 12 13 17 23 F4 PA6 I/O FT_fa - TIM1_BKIN, USART3_CTS/USART3_NSS, ADC_IN6
TIM16_CH1, I2C2_SDA

SPI1_MOSI/I2S1_SD, TIM3_CH2,
14 G3 13 14 18 24 E4 PA7 I/O FT_fa - TIM1_CH1N, TIM14_CH1, TIM17_CH1, ADC_IN7
I2C2_SCL

USART3_TX, USART1_TX,
- - - - - 25 H5 PC4 I/O FT_a - ADC_IN11
TIM2_ETR/TIM2_CH1, FDCAN1_RX

USART3_RX, USART1_RX, TIM2_CH2, ADC_IN12,

- - - - - 26 H6 PC5 I/O FT_a -
FDCAN1_TX WKUP5

SPI1_NSS/I2S1_WS, TIM3_CH3,
15 E3 14 15 19 27 F5 PB0 I/O FT_a - ADC_IN17
TIM1_CH2N, FDCAN1_RX, USART3_RX

TIM14_CH1, TIM3_CH4, TIM1_CH3N,

FDCAN1_TX,
15 C1 15 16 20 28 G5 PB1 I/O FT_a - ADC_IN18
USART3_RTS/USART3_DE/USART3_CK,
TIM1_CH2N, EVENTOUT

USART1_RX, MCO2, SPI2_MISO,

15 G1 - 17 21 29 H7 PB2 I/O FT_a - ADC_IN19
USART3_TX, EVENTOUT

TIM2_CH3, USART3_TX, SPI2_SCK,

- - - - 22 30 G6 PB10 I/O FT_fa - ADC_IN20
I2C2_SCL

SPI2_MOSI, TIM2_CH4, USART3_RX,

- - - - 23 31 H8 PB11 I/O FT_fa - ADC_IN21
I2C2_SDA

SPI2_NSS, TIM1_BKIN2, TIM1_BKIN,

- - - - 24 32 G7 PB12 I/O FT_a - ADC_IN22
FDCAN1_RX, TIM15_BKIN, EVENTOUT

SPI2_SCK, TIM1_CH1N, FDCAN1_TX,

- - - - 25 33 G8 PB13 I/O FT_fa - USART3_CTS/USART3_NSS, -
TIM15_CH1N, I2C2_SCL, EVENTOUT

SPI2_MISO, TIM1_CH2N,
- - - - 26 34 F6 PB14 I/O FT_fa - USART3_RTS/USART3_DE/USART3_CK, -
TIM15_CH1, I2C2_SDA, EVENTOUT

SPI2_MOSI, TIM1_CH3N, TIM15_CH1N,

- - - - 27 35 F7 PB15 I/O FT - RTC_REFIN
TIM15_CH2, EVENTOUT

MCO, USART2_TX, TIM1_CH1, SPI2_NSS,

SPI2_MISO, EVENTOUT,
15 G1 16 18 28 36 F8 PA8 I/O FT_a - SPI1_NSS/I2S1_WS, TIM1_CH2N, ADC_IN8
TIM1_CH3N, TIM3_CH3, TIM3_CH4,
TIM14_CH1, USART1_RX, MCO2

MCO, USART1_TX, TIM1_CH2, TIM3_ETR,

- - - 19 29 37 E6 PA9 I/O FT_f (2) SPI2_MISO, TIM15_BKIN, I2C1_SCL, -
EVENTOUT, I2C2_SCL
- - 17 20 30 38 E7 PC6 I/O FT - TIM3_CH1, TIM2_CH3 -

- - - - 31 39 E5 PC7 I/O FT - TIM3_CH2, TIM2_CH4 -

DS14720 Rev 1 35/123

37
Pinouts, pin description and alternate functions STM32C091xB/xC STM32C092xB/xC

Table 12. Pin assignment and description (continued)

Pin number

I/O structure
Pin type
Pin name
UFQFPN28

UFQFPN32

UFQFPN48
WLCSP24

UFBGA64

Notes
TSSOP20

Additional
LQFP32

LQFP48

LQFP64
(function Alternate functions
functions
after reset)

- - - - - 40 E8 PD8 I/O FT - SPI1_SCK/I2S1_CK, USART3_TX -

SPI1_NSS/I2S1_WS, TIM1_BKIN2,
- - - - - 41 D8 PD9 I/O FT - -
USART3_RX

SPI2_MOSI, USART1_RX, TIM1_CH3,

- - - 21 32 42 D6 PA10 I/O FT_f (2) MCO2, TIM17_BKIN, I2C1_SDA, -
EVENTOUT, I2C2_SDA

SPI1_MISO/I2S1_MCK,
16 F2 18 22 33 43 C8 PA11 [PA9] I/O FT_f (2) USART1_CTS/USART1_NSS, TIM1_CH4, -
FDCAN1_RX, TIM1_BKIN2, I2C2_SCL

SPI1_MOSI/I2S1_SD,
(2) USART1_RTS/USART1_DE/USART1_CK,
17 E1 19 23 34 44 B8 PA12 [PA10] I/O FT_f -
TIM1_ETR, FDCAN1_TX, I2S_CKIN,
I2C2_SDA

(3) SWDIO, IR_OUT, TIM3_ETR, USART2_RX,

18 C3 20 24 35 45 D7 PA13 I/O FT_a ADC_IN13
EVENTOUT

SWCLK, USART2_TX, EVENTOUT,

(3) SPI1_NSS/I2S1_WS, USART2_RX, ADC_IN14,
19 B2 21 25 36 46 C7 PA14-BOOT0 I/O FT_a
TIM1_CH1, MCO2, BOOT0
USART1_RTS/USART1_DE/USART1_CK
SPI1_NSS/I2S1_WS, USART2_RX,
TIM1_CH1, MCO2,
USART1_RTS/USART1_DE/USART1_CK,
19 A1 22 26 37 47 C6 PA15 I/O FT - TIM2_CH1/TIM2_ETR, -
USART4_RTS/USART4_DE/USART4_CK,
EVENTOUT,
USART3_RTS/USART3_DE/USART3_CK

- - - - - 48 A8 PC8 I/O FT - TIM3_CH3, TIM1_CH1 -

- - - - - 49 B7 PC9 I/O FT - TIM3_CH4, TIM1_CH2, I2S_CKIN -

EVENTOUT, TIM16_CH1, SPI2_NSS,

- - - - 38 50 A7 PD0 I/O FT - -
FDCAN1_RX

EVENTOUT, TIM17_CH1, SPI2_SCK,

- - - - 39 51 B6 PD1 I/O FT - -
FDCAN1_TX

USART3_RTS/USART3_DE/USART3_CK,
- - - - 40 52 A6 PD2 I/O FT - -
TIM3_ETR, TIM1_CH1N

USART2_CTS/USART2_NSS, TIM1_CH2N,
- - - - 41 53 D5 PD3 I/O FT - -
SPI2_MISO

SPI2_MOSI,
- - - - - 54 C5 PD4 I/O FT - USART2_RTS/USART2_DE/USART2_CK, -
TIM1_CH3N

SPI1_MISO/I2S1_MCK, USART2_TX,
- - - - - 55 B5 PD5 I/O FT - -
TIM1_BKIN

- - - - - 56 A5 PD6 I/O FT - SPI1_MOSI/I2S1_SD, USART2_RX -

36/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin number

I/O structure
Pin type
Pin name
UFQFPN28

UFQFPN32

UFQFPN48
WLCSP24

UFBGA64

Notes
TSSOP20

Additional
LQFP32

LQFP48

LQFP64
(function Alternate functions
functions
after reset)

SPI1_SCK/I2S1_CK, TIM1_CH2,
TIM3_CH2,
20 A3 23 27 42 57 B4 PB3 I/O FT_f - -
USART1_RTS/USART1_DE/USART1_CK,
I2C2_SCL, TIM2_CH2, EVENTOUT

SPI1_MISO/I2S1_MCK, TIM3_CH1,
20 A5 24 28 43 58 C4 PB4 I/O FT_f - USART1_CTS/USART1_NSS, TIM17_BKIN, -
I2C2_SDA, EVENTOUT

SPI1_MOSI/I2S1_SD, TIM3_CH2,
20 A3 25 29 44 59 D4 PB5 I/O FT - TIM16_BKIN, TIM3_CH3, FDCAN1_RX, WKUP6
I2C1_SMBA

USART1_TX, TIM1_CH3, TIM16_CH1N,

TIM3_CH3, SPI2_MISO,
USART1_NSS/USART1_CTS, I2C1_SCL,
I2C1_SMBA, SPI1_MOSI/I2S1_SD,
20 A5 26 30 45 60 A4 PB6 I/O FT_f - WKUP3
SPI1_MISO/I2S1_MCK,
SPI1_SCK/I2S1_CK, TIM1_CH2,
TIM3_CH1, TIM3_CH2, TIM16_BKIN,
FDCAN1_TX

USART1_RX, TIM1_CH4, TIM17_CH1N,

TIM3_CH4, SPI2_MOSI,
- - - - 46 61 A3 PB7 I/O FT_f - USART4_CTS/USART4_NSS, I2C1_SDA, -
EVENTOUT, USART2_CTS/USART2_NSS,
TIM16_CH1, TIM3_CH1, I2C1_SCL

USART1_RX, TIM1_CH4, TIM17_CH1N,

TIM3_CH4, SPI2_MOSI,
1 B4 27 31 - - - PB7 I/O FT_f - USART4_CTS/USART4_NSS, I2C1_SDA, RTC_REFIN
EVENTOUT, USART2_CTS/USART2_NSS,
TIM16_CH1, TIM3_CH1, I2C1_SCL
USART3_TX,
USART2_CTS/USART2_NSS, TIM16_CH1,
1 B4 28 32 47 62 B3 PB8 I/O FT_f - -
TIM3_CH1, SPI2_SCK, TIM15_BKIN,
I2C1_SCL, EVENTOUT, FDCAN1_RX

IR_OUT,
USART2_RTS/USART2_DE/USART2_CK,
- - - 1 48 63 C3 PB9 I/O FT_f - TIM17_CH1, TIM3_CH2, USART3_RX, -
SPI2_NSS, I2C1_SDA, EVENTOUT,
FDCAN1_TX

- - - - - 64 A2 PC10 I/O FT - USART3_TX, USART4_TX, TIM1_CH3 -

1. RST I/O structure when the PF2-NRST pin is configured as reset (input or input/output mode), FT I/O structure when the
PF2-NRST pin is configured as GPIO
2. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.
3. Upon reset, this pin is configured as SWD alternate function, and the internal pull-up device on the PA13 pin and the
internal pull-down device on the PA14 pin are activated.

DS14720 Rev 1 37/123

37
 Table 13. Port A alternate function mapping (AF0 to AF7)
38/123 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

USART2_CTS/ TIM2_ETR/
PA0 SPI2_SCK TIM16_CH1 USART1_TX TIM1_CH1 - -
USART2_NSS TIM2_CH1
USART2_RTS/
SPI1_SCK/
PA1 USART2_DE/ TIM17_CH1 TIM2_CH2 USART1_RX TIM1_CH2 I2C1_SMBA EVENTOUT
I2S1_CK
USART2_CK
SPI1_MOSI/
PA2 USART2_TX TIM16_CH1N TIM3_ETR - TIM1_CH3 TIM2_CH3 -
I2S1_SD
PA3 SPI2_MISO USART2_RX TIM1_CH1N TIM2_CH4 - TIM1_CH4 - EVENTOUT
SPI1_NSS/
PA4 USART2_TX TIM1_CH2N SPI2_MOSI TIM14_CH1 TIM17_CH1N - EVENTOUT
I2S1_WS
SPI1_SCK/ TIM2_ETR/
PA5 USART2_RX TIM1_CH3N USART3_TX TIM1_CH1 - EVENTOUT
I2S1_CK TIM2_CH1
DS14720 Rev 1

SPI1_MISO/ USART3_CTS/U
PA6 TIM3_CH1 TIM1_BKIN - TIM16_CH1 I2C2_SDA -
I2S1_MCK SART3_NSS
SPI1_MOSI/
PA7 TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 I2C2_SCL -
I2S1_SD
PA8 MCO USART2_TX TIM1_CH1 SPI2_NSS - - SPI2_MISO EVENTOUT
PA9 MCO USART1_TX TIM1_CH2 TIM3_ETR SPI2_MISO TIM15_BKIN I2C1_SCL EVENTOUT

STM32C091xB/xC STM32C092xB/xC
PA10 SPI2_MOSI USART1_RX TIM1_CH3 MCO2 - TIM17_BKIN I2C1_SDA EVENTOUT
SPI1_MISO/ USART1_CTS/
PA11 TIM1_CH4 - FDCAN1_RX TIM1_BKIN2 I2C2_SCL -
I2S1_MCK USART1_NSS
USART1_RTS/
SPI1_MOSI/
PA12 USART1_DE/ TIM1_ETR - FDCAN1_TX I2S_CKIN I2C2_SDA -
I2S1_SD
USART1_CK
PA13 SWDIO IR_OUT - TIM3_ETR USART2_RX - - EVENTOUT
PA14 SWCLK USART2_TX - - - - - EVENTOUT
USART1_RTS/ USART4_RTS/U
SPI1_NSS/ TIM2_ETR/
PA15 USART2_RX TIM1_CH1 MCO2 USART1_DE/ SART4_DE/USA EVENTOUT
I2S1_WS TIM2_CH1
USART1_CK RT4_CK
 Table 14. Port A alternate function mapping (AF8 to AF15)

STM32C091xB/xC STM32C092xB/xC
Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PA0 - USART4_TX - - - - - -
PA1 TIM15_CH1N USART4_RX - - - - - -
PA2 TIM15_CH1 - - - - - - -
PA3 TIM15_CH2 - - - - - - -
PA4 - - - - - - - -
PA5 - - - - - - - -
PA6 - - - - - - - -
PA7 - - - - - - - -
SPI1_NSS/
PA8 TIM1_CH2N TIM1_CH3N TIM3_CH3 TIM3_CH4 TIM14_CH1 USART1_RX MCO2
I2S1_WS
DS14720 Rev 1

PA9 I2C2_SCL - - - - - - -
PA10 I2C2_SDA - - - - - - -
PA11 - - - - - - - -
PA12 - - - - - - - -
PA13 - - - - - - - -
USART1_RTS/
SPI1_NSS/
PA14 USART2_RX TIM1_CH1 MCO2 USART1_DE/ - - -
I2S1_WS
USART1_CK
USART3_RTS/U
PA15 SART3_DE/USA - - - - - - -
RT3_CK
39/123
 Table 15. Port B alternate function mapping (AF0 to AF7)
40/123 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1_NSS/
PB0 TIM3_CH3 TIM1_CH2N FDCAN1_RX USART3_RX - - -
I2S1_WS
USART3_RTS/U
PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N FDCAN1_TX SART3_DE/USA TIM1_CH2N - EVENTOUT
RT3_CK
PB2 USART1_RX - - MCO2 SPI2_MISO USART3_TX - EVENTOUT
USART1_RTS/
SPI1_SCK/
PB3 TIM1_CH2 - TIM3_CH2 USART1_DE/ I2C2_SCL TIM2_CH2 EVENTOUT
I2S1_CK
USART1_CK
SPI1_MISO/ USART1_CTS/
PB4 TIM3_CH1 - - TIM17_BKIN I2C2_SDA EVENTOUT
I2S1_MCK USART1_NSS
SPI1_MOSI/
PB5 TIM3_CH2 TIM16_BKIN TIM3_CH3 FDCAN1_RX - I2C1_SMBA -
DS14720 Rev 1

I2S1_SD
USART1_NSS/
PB6 USART1_TX TIM1_CH3 TIM16_CH1N TIM3_CH3 SPI2_MISO I2C1_SCL I2C1_SMBA
USART1_CTS
USART4_CTS/U
PB7 USART1_RX TIM1_CH4 TIM17_CH1N TIM3_CH4 SPI2_MOSI I2C1_SDA EVENTOUT
SART4_NSS
USART2_CTS/
PB8 USART3_TX TIM16_CH1 TIM3_CH1 SPI2_SCK TIM15_BKIN I2C1_SCL EVENTOUT
USART2_NSS

STM32C091xB/xC STM32C092xB/xC
USART2_RTS/
PB9 IR_OUT USART2_DE/ TIM17_CH1 TIM3_CH2 USART3_RX SPI2_NSS I2C1_SDA EVENTOUT
USART2_CK
PB10 - - - TIM2_CH3 USART3_TX SPI2_SCK I2C2_SCL -
PB11 SPI2_MOSI - - TIM2_CH4 USART3_RX - I2C2_SDA -
PB12 SPI2_NSS TIM1_BKIN2 TIM1_BKIN - FDCAN1_RX TIM15_BKIN - EVENTOUT
USART3_CTS/U
PB13 SPI2_SCK - TIM1_CH1N FDCAN1_TX TIM15_CH1N I2C2_SCL EVENTOUT
SART3_NSS
 Table 15. Port B alternate function mapping (AF0 to AF7) (continued)

STM32C091xB/xC STM32C092xB/xC
Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

USART3_RTS/U
PB14 SPI2_MISO - TIM1_CH2N - SART3_DE/USA TIM15_CH1 I2C2_SDA EVENTOUT
RT3_CK
PB15 SPI2_MOSI - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT

Table 16. Port B alternate function mapping (AF8 to AF15)

Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PB0 - - - - - - - -
PB1 - - - - - - - -
PB2 - - - - - - - -
PB3 - - - - - - - -
DS14720 Rev 1

PB4 - - - - - - - -
PB5 - - - - - - - -
SPI1_MOSI/ SPI1_MISO/ SPI1_SCK/
PB6 TIM1_CH2 TIM3_CH1 TIM3_CH2 TIM16_BKIN FDCAN1_TX
I2S1_SD I2S1_MCK I2S1_CK
USART2_CTS/
PB7 - TIM16_CH1 TIM3_CH1 - - I2C1_SCL -
USART2_NSS
PB8 FDCAN1_RX - - - - - - -
PB9 FDCAN1_TX - - - - - - -
PB10 - - - - - - - -
PB11 - - - - - - - -
PB12 - - - - - - - -
PB13 - - - - - - - -
PB14 - - - - - - - -
PB15 - - - - - - - -
41/123
 Table 17. Port C alternate function mapping (AF0 to AF7)
42/123 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PC0 - USART4_RX - - USART3_TX - - -

PC1 - USART4_TX TIM15_CH1 - USART3_RX - - -
PC2 SPI2_MISO - TIM15_CH2 - FDCAN1_RX - - -
PC3 SPI2_MOSI - - - FDCAN1_TX - - -
TIM2_ETR/
PC4 USART3_TX USART1_TX - FDCAN1_RX - - -
TIM2_CH1
PC5 USART3_RX USART1_RX - TIM2_CH2 FDCAN1_TX - - -
PC6 - TIM3_CH1 - TIM2_CH3 - - - -
PC7 - TIM3_CH2 - TIM2_CH4 - - - -
PC8 - TIM3_CH3 TIM1_CH1 - - - - -
DS14720 Rev 1

PC9 - TIM3_CH4 TIM1_CH2 - - I2S_CKIN - -

PC10 USART3_TX USART4_TX TIM1_CH3 - - - - -
PC11 USART3_RX USART4_RX TIM1_CH4 - - - - -
PC12 TIM14_CH1 - - - - - - -
PC13 - TIM1_ETR TIM1_BKIN - - - - -
PC14 USART1_TX TIM1_ETR TIM1_BKIN2 - - - - USART3_TX

STM32C091xB/xC STM32C092xB/xC
PC15 OSC32_EN OSC_EN TIM1_ETR TIM3_CH3 TIM15_BKIN - - -

Table 18. Port C alternate function mapping (AF8 to AF15)

Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PC0 - - - - - - - -
PC1 - - - - - - - -
PC2 - - - - - - - -
PC3 - - - - - - - -
PC4 - - - - - - - -
 Table 18. Port C alternate function mapping (AF8 to AF15) (continued)

STM32C091xB/xC STM32C092xB/xC
Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PC5 - - - - - - - -
PC6 - - - - - - - -
PC7 - - - - - - - -
PC8 - - - - - - - -
PC9 - - - - - - - -
PC10 - - - - - - - -
PC11 - - - - - - - -
PC12 - - - - - - - -
PC13 - - - - - - - -
USART2_RTS/
DS14720 Rev 1

PC14 IR_OUT USART2_DE/ TIM17_CH1 TIM3_CH2 SPI2_NSS FDCAN1_TX I2C1_SDA EVENTOUT

USART2_CK
PC15 - - - - - - - -

Table 19. Port D alternate function mapping (AF0 to AF7)

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PD0 EVENTOUT - TIM16_CH1 SPI2_NSS FDCAN1_RX - - -

PD1 EVENTOUT - TIM17_CH1 SPI2_SCK FDCAN1_TX - - -
USART3_RTS/U
PD2 SART3_DE/USA TIM3_ETR TIM1_CH1N - - - - -
RT3_CK
USART2_CTS/
PD3 - TIM1_CH2N SPI2_MISO - - - -
USART2_NSS
USART2_RTS/
PD4 SPI2_MOSI USART2_DE/ TIM1_CH3N - - - - -
USART2_CK
43/123
 Table 19. Port D alternate function mapping (AF0 to AF7) (continued)
44/123 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1_MISO/
PD5 USART2_TX TIM1_BKIN - - - - -
I2S1_MCK
SPI1_MOSI/
PD6 USART2_RX - - - - - -
I2S1_SD
SPI1_SCK/
PD8 - - - USART3_TX - - -
I2S1_CK
SPI1_NSS/
PD9 - TIM1_BKIN2 - USART3_RX - - -
I2S1_WS

Table 20. Port F alternate function mapping (AF0 to AF7)

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
DS14720 Rev 1

PF0 - - TIM14_CH1 - - - - -
PF1 OSC_EN - TIM15_CH1N - - - - -
PF2 MCO TIM1_CH4 - - - - - -
PF3 - - - - - - - -

STM32C091xB/xC STM32C092xB/xC
STM32C091xB/xC STM32C092xB/xC Electrical characteristics

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
Parameter values defined at temperatures or in temperature ranges out of the ordering
information scope are to be ignored.
Packages used for characterizing certain electrical parameters may differ from the
commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 12.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 13.

Figure 12. Pin loading conditions Figure 13. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

DS14720 Rev 1 45/123

91
Electrical characteristics STM32C091xB/xC STM32C092xB/xC

5.1.6 Power supply scheme

Figure 14. Power supply scheme

RTC

VDD VCORE
VDD/VDDA VDD
Regulator

VDDIO1
OUT

Level shifter
Kernel logic
1 x 100 nF IO (CPU, digital and
GPIOs
+ 1 x 4.7 μF IN
logic memories)

VSS

VDDA
VREF VREF+ VREF+(1)

ADC
VREF-
100 nF
VSSA
VSS/VSSA
MSv55841V2

1. Internally connected to VDDA in devices without the VREF+ pin

Caution: Power supply pin pairs (VDD/VDDA versus VSS/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.

5.1.7 Current consumption measurement

Figure 15. Current consumption measurement scheme

IDD
VDD/VDDA
VDD
(VDDA)

MS55840V1

46/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Electrical characteristics

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 21, Table 22 and Table 23
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability. The device mission profile
(application conditions) is compliant with the JEDEC JESD47 qualification standard.
All voltages are defined with respect to VSS.

Table 21. Voltage characteristics

Symbol Ratings Min Max Unit

VDD External supply voltage - 0.3 4.0 V

VREF+ External voltage on VREF+ pin - 0.3 Min(VDD + 0.4, 4.0) V
(1) - 0.3 (2)(3)
VIN Input voltage on pin VDDIO1 + 4.0 V
1. VIN maximum must always be respected. Refer to Table 22 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. When an FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.

Table 22. Current characteristics

Symbol Ratings Max Unit

IVDD/VDDA Current into VDD/VDDA power pin (source) 100 mA

IVSS/VSSA Current out of VSS/VSSA ground pin (sink) 100 mA
Output current sunk by any I/O and control pin 20
IIO(PIN) mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(1) 80
∑I(PIN) mA
(1)
Total output current sourced by sum of all I/Os and control pins 80
IINJ(PIN)(1)(2) Injected current on a FT_xx pin -5 / NA mA
∑IINJ(PIN) Total injected current (sum of all I/Os and control pins)(3) -25 mA
1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
2. A positive injection is induced by VIN > VDDIO1 while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).

Table 23. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 130 °C

DS14720 Rev 1 47/123

91
Electrical characteristics STM32C091xB/xC STM32C092xB/xC

5.3 Operating conditions

5.3.1 General operating conditions

Table 24. General operating conditions

Symbol Parameter Conditions Min Max Unit

VDD (1)
Standard operating voltage - 2.0 3.6 V
VIN I/O input voltage - -0.3 Min (VDDIO1 + 3.6, 5.5)(2) V
fHCLK AHB clock frequency - - 48 MHz
fPCLK APB clock frequency - - 48 MHz
Suffix 6(4) -40 85
TA Ambient temperature(3) Suffix 7(4) -40 105 °C
Suffix 3(4) -40 125
(4)
Suffix 6 -40 105
TJ Junction temperature Suffix 7(4) -40 125 °C
Suffix 3(4) -40 130
1. When RESET is released, functionality is guaranteed down to VPDR.
2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided
that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.11: Thermal characteristics.
4. Temperature range digit in the order code. See Section 7: Ordering information.

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 24.

Table 25. Operating conditions at power-up / power-down

Symbol Parameter Min Max Unit

VDD rise time rate 0 ∞

tVDD µs/V
VDD fall time rate 10 ∞

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 26 are derived from tests performed under the ambient
temperature conditions summarized in Table 24.

Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tRSTTEMPO(1) POR temporization when VDD crosses VPOR VDD rising - 270 500 µs
VPOR(1) Power-on reset threshold - 1.9 1.94 1.98 V

48/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Electrical characteristics

Table 26. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

VPDR(1) Power-down reset threshold - 1.88 1.92 1.96 V

VDD rising 2.05 2.10 2.18
VBOR1 Brownout reset threshold 1 V
VDD falling 1.95 2.00 2.08
VDD rising 2.20 2.31 2.38
VBOR2 Brownout reset threshold 2 V
VDD falling 2.10 2.21 2.28
VDD rising 2.50 2.62 2.68
VBOR3 Brownout reset threshold 3 V
VDD falling 2.40 2.52 2.58
VDD rising 2.80 2.91 3.00
VBOR4 Brownout reset threshold 4 V
VDD falling 2.70 2.81 2.90
Vhyst_POR_PDR Hysteresis of VPOR and VPDR - - 20 - mV
Vhyst_BOR Hysteresis of VBORx - - 100 - mV
(1)
IDD(BOR) BOR consumption from VDD - - 2.2 2.5 µA
1. Specified by design. Not tested in production.

5.3.4 Embedded voltage reference

The parameters given in Table 27 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.

Table 27. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage - 1.182 1.212 1.232 V

ADC sampling time when reading
tS_vrefint (1)(2) - 4 - - µs
the internal reference voltage
Start time of reference voltage
tstart_vrefint(2) - - 8 12 µs
buffer when ADC is enable
VREFINT buffer consumption from
IDD(VREFINTBUF)(2) - 9 13.5 23 µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT(2) VDD = 3 V - 30 50 mV
over the temperature range
TCoeff Averange temperature coefficient - - 20 70 ppm/°C
ACoeff Long term stability 1000 hours, T = 25 °C - 300 1000 ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200 ppm/V
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design. Not tested in production.

DS14720 Rev 1 49/123

91
Electrical characteristics STM32C091xB/xC STM32C092xB/xC

Figure 16. VREFINT vs. temperature

V
1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 15: Current consumption
measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0490 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
Unless otherwise stated, values given in Table 28 through Table 35 are derived from tests
performed under ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions.

50/123 DS14720 Rev 1

 STM32C091xB/xC STM32C092xB/xC
Table 28. Current consumption in Run mode from flash memory at different die temperatures
Conditions Typ Max(1)
Symbol Parameter Unit
General(2) fHCLK Fetch 25 85 105 125 25 85 105 125
from(3) °C °C °C °C °C °C °C °C
48 MHz 3.550 3.700 3.800 4.050 3.84 4.04 4.33 4.83
32 MHz 2.400 2.550 2.650 2.900 2.60 2.80 3.09 3.74
24 MHz 2.100 2.250 2.350 2.550 2.30 2.49 2.79 3.28
16 MHz 1.450 1.550 1.650 1.900 1.65 1.85 2.08 2.64
fHCLK = fHSE_bypass 8 MHz 0.770 0.870 0.980 1.200 0.85 0.96 1.47 1.92
( > 32.768 kHz),
4 MHz 0.425 0.525 0.630 0.840 0.49 0.74 1.08 1.58
fHCLK = fLSE_bypass
( = 32.768 kHz) 2 MHz 0.255 0.350 0.460 0.665 0.30 0.57 0.86 1.48
1 MHz 0.170 0.265 0.370 0.575 0.21 0.47 0.77 1.39
500 kHz 0.130 0.220 0.330 0.530 0.16 0.42 0.74 1.29
DS14720 Rev 1

Supply 125 kHz 0.096 0.190 0.295 0.500 0.13 0.41 0.71 1.30
Flash
IDD(Run) current in mA
32.768 kHz memory 0.090 0.180 0.285 0.495 0.27 0.40 0.68 1.30
Run mode
48 MHz 3.750 3.850 3.950 4.150 4.04 4.14 4.34 4.83
24 MHz 2.400 2.500 2.600 2.800 2.60 2.70 2.99 3.48
12 MHz 1.450 1.500 1.650 1.800 1.55 1.69 2.04 2.47
fHCLK = fHSI48/HSIDIV 6 MHz 0.955 1.050 1.150 1.350 0.96 1.30 1.60 2.10
( > 32 kHz),
3 MHz 0.710 0.780 0.880 1.100 0.74 0.97 1.28 1.90
fHCLK = fLSI
( = 32 kHz) 1.5 MHz 0.585 0.655 0.755 0.955 0.62 0.86 1.18 1.68
750 kHz 0.525 0.595 0.695 0.895 0.55 0.79 1.09 1.69

Electrical characteristics
375 kHz 0.495 0.565 0.665 0.865 0.52 0.76 1.09 1.59
32 kHz 0.089 0.180 0.285 0.495 0.12 0.40 0.68 1.30
1. Evaluated by characterization. Not tested in production.
2. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
3. Prefetch disabled and cache enabled when fetching from flash memory.
51/123
 Table 29. Current consumption in Run mode from SRAM at different die temperatures
52/123

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
General(2) fHCLK Fetch 25 85 105 125 25 85 105 125
from(3) °C °C °C °C °C °C °C °C
48 MHz 3.150 3.300 3.400 3.600 3.46 3.72 3.86 4.37
32 MHz 2.150 2.250 2.350 2.550 2.36 2.56 2.87 3.30
24 MHz 1.650 1.750 1.850 2.050 1.86 2.06 2.27 2.87
16 MHz 1.100 1.200 1.300 1.550 1.20 1.40 1.70 2.38
fHCLK = fHSE_bypass 8 MHz 0.600 0.700 0.805 1.000 0.67 0.92 1.23 1.80
(>32.768 kHz),
4 MHz 0.345 0.440 0.545 0.750 0.40 0.67 0.96 1.52
fHCLK = fLSE_bypass
(=32.768 kHz) 2 MHz 0.215 0.310 0.415 0.620 0.26 0.53 0.83 1.42
1 MHz 0.150 0.245 0.350 0.555 0.18 0.46 0.76 1.30
500 kHz 0.120 0.210 0.315 0.520 0.16 0.42 0.73 1.30
DS14720 Rev 1

Supply 125 kHz 0.094 0.185 0.295 0.495 0.12 0.41 0.70 1.30
IDD(Run) current in SRAM mA
Run mode 32.768 kHz 0.090 0.180 0.285 0.495 0.13 0.40 0.68 1.32
48 MHz 3.400 3.450 3.550 3.750 3.66 3.66 4.02 4.53
24 MHz 1.900 2.000 2.100 2.300 2.00 2.26 2.57 3.07
12 MHz 1.200 1.250 1.350 1.550 1.30 1.50 1.80 2.30
fHCLK = fHSI48/HSIDIV 6 MHz 0.830 0.900 1.000 1.200 0.86 0.97 1.41 2.00

STM32C091xB/xC STM32C092xB/xC
( > 32 kHz),
3 MHz 0.645 0.715 0.815 1.000 0.68 0.91 1.20 1.80
fHCLK = fLSI
( = 32 kHz) 1.5 MHz 0.555 0.625 0.725 0.920 0.59 0.82 1.20 1.69
750 kHz 0.510 0.580 0.680 0.875 0.54 0.78 1.10 1.69
375 kHz 0.485 0.555 0.655 0.855 0.51 0.75 1.09 1.59
32 kHz 0.088 0.180 0.285 0.495 0.12 0.40 0.68 1.32
1. Evaluated by characterization. Not tested in production.
2. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
3. Code compiled with high optimization for space in SRAM.
STM32C091xB/xC STM32C092xB/xC Electrical characteristics

Table 30. Typical current consumption in Run depending on code executed

Conditions Typ Typ
Symbol Parameter Unit Unit
Fetch
General(1) Code 25 °C 25 °C
from(2)

Reduced code 3.95 82.3

Coremark 3.60 75.0
Flash
Dhrystone 3.65 76.0
memory
Fibonacci 2.90 60.4
fHCLK = fHSE_bypass = WhileLoop 1.95 40.6
48 MHz Reduced code 3.15 65.6
Coremark 2.90 60.4
Dhrystone SRAM 2.95 61.5
Fibonacci 3.10 64.6
WhileLoop 2.30 47.9
Reduced code 1.45 90.6
Coremark 1.30 81.3
Flash
Dhrystone 1.30 81.3
memory
Fibonacci 1.000 62.5
Supply WhileLoop 0.700 43.8
fHCLK = fHSE_bypass =
IDD(Run) current in mA μA/MHz
16 MHz Reduced code 1.100 68.8
Run mode
Coremark 1.050 65.6
Dhrystone SRAM 1.050 65.6
Fibonacci 1.10 68.8
WhileLoop 0.830 51.9
Reduced code 0.255 127.5
Coremark 0.235 117.5
Flash
Dhrystone 0.235 117.5
memory
Fibonacci 0.200 100.0
fHCLK = fHSE_bypass = WhileLoop 0.160 80.0
2 MHz Reduced code 0.215 107.5
Coremark 0.205 102.5
Dhrystone SRAM 0.205 102.5
Fibonacci 0.210 105.0
WhileLoop 0.180 90.0

DS14720 Rev 1 53/123

91
Electrical characteristics STM32C091xB/xC STM32C092xB/xC

Table 30. Typical current consumption in Run depending on code executed (continued)
Conditions Typ Typ
Symbol Parameter Unit Unit
Fetch
General(1) Code 25 °C 25 °C
from(2)

Reduced code 4.15 86.5

Coremark 3.80 79.2
Flash
Dhrystone 3.85 80.2
memory
Fibonacci 3.15 65.6
fHCLK = fHSI48/HSIDIV WhileLoop 2.15 44.8
= 48 MHz
(HSIDIV = 1) Reduced code 3.40 70.8
Coremark 3.15 65.6
Dhrystone SRAM 3.15 65.6
Fibonacci 3.30 68.8
WhileLoop 2.55 53.1
Reduced code 1.45 120.8
Coremark 1.35 112.5
Flash
Dhrystone 1.35 112.5
memory
Fibonacci 1.10 91.7
Supply fHCLK = fHSI48/HSIDIV WhileLoop 0.88 73.3
IDD(Run) current in = 12 MHz mA μA/MHz
(HSIDIV = 4) Reduced code 1.20 100.0
Run mode
Coremark 1.15 95.8
Dhrystone SRAM 1.15 95.8
Fibonacci 1.20 100.0
WhileLoop 0.98 81.7
Reduced code 0.705 235.0
Coremark 0.680 226.7
Flash
Dhrystone 0.680 226.7
memory
Fibonacci 0.625 208.3
fHCLK = fHSI48/HSIDIV WhileLoop 0.565 188.3
= 3 MHz
Reduced code 0.645 215.0
(HSIDIV = 16)
Coremark 0.630 210.0
Dhrystone SRAM 0.630 210.0
Fibonacci 0.640 213.3
WhileLoop 0.590 196.7
1. VDD = 3.0 V, all peripherals disabled
2. Prefetch and cache enabled when fetching from flash

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 STM32C091xB/xC STM32C092xB/xC
Table 31. Current consumption in Sleep mode
Conditions Typ Max(1)
Symbol Parameter 25 85 105 125 25 85 105 125 Unit
General fHCLK
°C °C °C °C °C °C °C °C
48 MHz 0.740 0.845 0.960 1.150 0.94 1.27 1.58 2.02
32 MHz 0.520 0.620 0.730 0.930 0.71 0.94 1.28 1.75
24 MHz 0.410 0.510 0.615 0.815 0.56 0.80 1.18 1.65
16 MHz 0.305 0.400 0.505 0.705 0.41 0.67 0.96 1.56
8 MHz 0.195 0.290 0.395 0.595 0.27 0.52 0.82 1.38
Flash memory enabled 4 MHz 0.140 0.230 0.340 0.535 0.20 0.46 0.76 1.27
2 MHz 0.115 0.205 0.310 0.510 0.16 0.44 0.72 1.28
1 MHz 0.100 0.190 0.300 0.495 0.14 0.40 0.71 1.28
500 kHz 0.093 0.185 0.290 0.490 0.13 0.41 0.70 1.29
All peripherals
DS14720 Rev 1

125 kHz 0.088 0.180 0.285 0.485 0.12 0.40 0.70 1.29
disabled,
Supply fHCLK = fHSE_bypass 32,768 Hz 0.087 0.180 0.285 0.485 0.13 0.40 0.69 1.29
IDD(Sleep) current in mA
( > 32.768 kHz), 48 MHz 0.735 0.840 0.955 1.150 0.93 1.27 1.58 2.02
Sleep mode
fHCLK = fLSE_bypass 32 MHz 0.515 0.610 0.725 0.925 0.70 0.92 1.28 1.75
( = 32.768 kHz)
24 MHz 0.405 0.500 0.610 0.810 0.55 0.79 1.09 1.65
16 MHz 0.295 0.390 0.500 0.700 0.41 0.66 0.96 1.47
8 MHz 0.190 0.280 0.390 0.590 0.27 0.52 0.81 1.38
Flash memory disabled
(flash memory power- 4 MHz 0.135 0.225 0.335 0.530 0.19 0.45 0.77 1.28
down sleep mode) 2 MHz 0.105 0.200 0.305 0.505 0.15 0.43 0.73 1.29
1 MHz 0.093 0.185 0.290 0.490 0.13 0.42 0.71 1.29

Electrical characteristics
500 kHz 0.087 0.175 0.285 0.485 0.12 0.38 0.70 1.29
125 kHz 0.081 0.170 0.280 0.475 0.11 0.37 0.69 1.28
32,768 Hz 0.080 0.170 0.280 0.475 0.11 0.39 0.69 1.28
55/123
 Table 31. Current consumption in Sleep mode (continued)
56/123

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter 25 85 105 125 25 85 105 125 Unit
General fHCLK
°C °C °C °C °C °C °C °C
48 MHz 0.950 1.000 1.100 1.300 1.15 1.34 1.63 2.12
All peripherals 24 MHz 0.705 0.775 0.875 1.050 0.80 1.07 1.37 1.82
disabled, 12 MHz 0.585 0.655 0.755 0.945 0.65 0.88 1.18 1.76
Supply fHCLK = fHSI48/HSIDIV
IDD(Sleep) current in Flash memory enabled 6 MHz 0.525 0.595 0.695 0.885 0.57 0.80 1.09 1.67 mA
( > 32 kHz),
Sleep mode 1.5 MHz 0.480 0.550 0.650 0.840 0.52 0.75 1.10 1.58
fHCLK = fLSI
( = 32 kHz) 375 kHz 0.465 0.535 0.635 0.830 0.49 0.73 1.09 1.58
32 kHz 0.087 0.180 0.285 0.485 0.12 0.40 0.69 1.29
1. Evaluated by characterization. Not tested in production.
DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC
 Table 32. Current consumption in Stop mode

STM32C091xB/xC STM32C092xB/xC
Typ Max(1)
Symbol Parameter Conditions VDD 25 85 105 125 25 85 105 125 Unit
°C °C °C °C °C °C °C °C
2V 83.0 170 275 470 110 360 650 1200
2.4 V 84.0 175 275 475 120 360 650 1200
All clocks off
3V 85.5 175 280 480 120 360 650 1200
3.6 V 87.0 175 285 485 120 360 650 1200
2V 76.5 165 270 465 110 360 640 1200
All clocks off 2.4 V 77.5 165 270 470 110 360 640 1200
Flash memory in power-down stop
mode 3V 79.0 170 270 475 110 360 640 1200
3.6 V 81.0 170 275 480 110 360 640 1200
2V 83.0 170 275 470 110 360 650 1200
Supply current RTC enabled and supplied with 2.4 V 84.5 175 275 475 120 360 650 1200
IDD(Stop) µA
in Stop mode LSE bypass (32.768 kHz)
DS14720 Rev 1

3V 86.0 175 280 480 120 360 650 1200

3.6 V 87.5 175 285 485 120 360 650 1200
2V 77.0 165 270 465 110 360 650 1200
RTC enabled and supplied with
LSE bypass (32.768 kHz) 2.4 V 78.0 165 270 470 110 360 650 1200
Flash memory in power-down stop 3V 79.5 170 270 470 110 360 650 1200
mode
3.6 V 81.5 170 275 480 110 360 650 1200
2V 440 505 600 785 480 710 980 1500
2.4 V 440 510 605 795 490 710 980 1500
HSI Kernel on
3V 445 510 610 800 490 710 980 1500
3.6 V 445 515 610 805 490 710 980 1500

Electrical characteristics
1. Evaluated by characterization. Not tested in production.
57/123
 Table 33. Current consumption in Standby mode
58/123

Electrical characteristics
Typ Max(1)
Symbol Parameter Conditions VDD 25 85 105 125 25 85 105 125 Unit
°C °C °C °C °C °C °C °C
2V 6.70 8.10 9.50 13.60 7.8 9.5 12.0 18.4
2.4 V 6.95 8.40 9.90 14.00 8.0 9.8 12.3 18.9
All clocks off
3V 7.35 8.75 10.50 15.50 8.4 10.2 12.9 19.9
Supply
current in 3.6 V 7.80 9.60 12.10 18.62 9.6 11.7 14.7 22.6
IDD(Standby) µA
Standby 2V 7.20 8.70 10.00 14.00 8.3 10.2 12.8 19.7
mode IWDG
enabled and 2.4 V 7.45 9.00 10.43 14.40 8.5 10.3 13.1 20.1
clocked by 3V 7.90 9.45 11.50 16.50 9.0 11.0 13.8 21.3
LSI
3.6 V 8.35 10.45 12.45 18.90 11.0 13.4 16.9 26.0
1. Evaluated by characterization. Not tested in production.
DS14720 Rev 1

Table 34. Current consumption in Shutdown mode

Typ Max(1)
Symbol Parameter Conditions VDD Unit
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
2V 14 550 1750 5570 93 1400 4350 12200
Supply
current in All clocks 2.4 V 17 620 1970 6150 95 1450 4560 12400
IDD(Shutdown) nA
Shutdown off 3.0 V 25 770 2390 7370 99 1600 4900 13150

STM32C091xB/xC STM32C092xB/xC
mode
2V 39 1060 3290 9860 134 2020 6150 17700
1. Evaluated by characterization. Not tested in production.
STM32C091xB/xC STM32C092xB/xC Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up or pull-down resistor generate current consumption
when the pin is externally held low or high, respectively. The value of this current
consumption can be simply computed by using the pull-up/pull-down resistors values given
in Table 50: I/O static characteristics.
For the output pins, any pull-up or pull-down device (internal and external) and external load
must also be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Current consumption of peripherals), the I/Os used by an application also
contribute to the current consumption. When an I/O pin switches, it uses the current from
the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive
load (internal and external) of the pin:

I SW = V DDIO1 × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIO1 is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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Electrical characteristics STM32C091xB/xC STM32C092xB/xC

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 21:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the
following table. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.

Table 35. Current consumption of peripherals

Consumption in
Peripheral Bus
µA/MHz
IOPORT bus 0.1
GPIOA 1.5
GPIOB 1.5
IOPORT
GPIOC 1.5
GPIOD 1.5
GPIOF 0.7
Bus matrix 0.3
All AHB peripherals 10.1
DMA1 3.7
AHB
FLASH 5.3
SRAM1 0.7
CRC1 0.4

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STM32C091xB/xC STM32C092xB/xC Electrical characteristics

Table 35. Current consumption of peripherals (continued)

Consumption in
Peripheral Bus
µA/MHz
All APB peripherals 47.2
AHB to APB bridge (2) 0.3
TIM3 3.5
RTCAPB 1.4
WWDG1 0.3
USART2 1.8
USART3 1.9
USART4 1.9
I2C1 0.8
I2C1 independent clock domain 2.4
I2C2 0.8
DBGMCU1 0.1
PWR 0.4
SYSCFG 0.5
TIM1 APB 6.2
TIM2 4.3
SPI1 2.1
SPI1 independent clock domain 0.6
SPI2 1.9
USART1 2.2
USART1 independent clock domain 5.2
TIM14 1.5
TIM15 1.1
TIM16 2.7
TIM17 2.7
ADC1 1.2
ADC1 independent clock domain 0.1
FDCAN 8.4
FDCAN independent clock domain 2.8
All peripherals 67.5

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91
Electrical characteristics STM32C091xB/xC STM32C092xB/xC

5.3.6 Wake-up time from low-power modes

The wake-up times given in Table 36 are the latency between the event and the execution of
the first user instruction.

Table 36. Low-power mode wake-up times

Symbol Parameter(1) Conditions Typ Max Unit
Transiting to Run-mode execution in CPU
flash memory powered during Sleep 10 12 clock
Wake-up time
HCLK = HSI48/4 = mode cycles
tWUSLEEP from Sleep to Run
12 MHz Transiting to Run-mode execution in
mode
flash memory not powered during 4.74 5.02 µs
Sleep mode

Transiting to Run-mode execution in

flash memory powered during Stop 2.7 3.1
Clock after mode
Wake-up time wake-up is HCLK Transiting to Run-mode execution in
tWULPSTOP
from Stop mode = HSI48/4 = 12 flash memory not powered during 5.9 6.4
MHz Stop mode
Transiting to Run-mode execution in µs
2.5 2.9
SRAM
Wake-up time Clock after wake-
tWUSTBY from Standby up is HCLK = Transiting to Run mode 23.0 35.0
mode HSI48/4 = 12 MHz
Wake-up time Clock after wake-
tWUSHDN from Shutdown up is HCLK = Transiting to Run mode 385.0 466.0
mode HSI48/4 = 12 MHz
1. Evaluated by characterization. Not tested in production.

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.13. See
Figure 17 for recommended clock input waveform.

Table 37. High-speed external user clock characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

User external clock source

fHSE_ext - - 8 48 MHz
frequency
Digital OSC_IN input pin high
VHSEH - 0.7 × VDD - VDD
level voltage
V
Digital OSC_IN input pin low
VHSEL - VSS - 0.3 × VDD
level voltage
tw(HSEH)/
Digital OSC_IN high or low time - 7 - - ns
tw(HSEL)

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STM32C091xB/xC STM32C092xB/xC Electrical characteristics

1. Specified by design. Not tested in production.

Figure 17. High-speed external clock source AC timing diagram

tw(HSEH)

VHSEH
90%
10%
VHSEL

tr(HSE) t
tf(HSE) tw(HSEL)
THSE

MS19214V2

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.13. See
Figure 18 for recommended clock input waveform.

Table 38. Low-speed external user clock characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 × VDDIO1 - VDDIO1
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 × VDDIO1
tw(LSEH)/
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
1. Specified by design. Not tested in production.

Figure 18. Low-speed external clock source AC timing diagram

tw(LSEH)

VLSEH
90%
10%
VLSEL

tr(LSE) t
tf(LSE) tw(LSEL)
TLSE

MS19215V2

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Electrical characteristics STM32C091xB/xC STM32C092xB/xC

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 39. HSE oscillator characteristics

Symbol Parameter(1) Conditions(2) Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 13
VDD = 3 V,
Rm = 30 Ω, - 0.62 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.67 -
CL = 10 pF@8 MHz

IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 1.15 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.75 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 5.0 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Specified by design. Not tested in production.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 19). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.

64/123 DS14720 Rev 1

STM32C091xB/xC STM32C092xB/xC Electrical characteristics

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 19. Typical application with an 8 MHz crystal

Resonator with integrated

capacitors
CL1

OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain

REXT (1) OSC_OUT

CL2

MS19876V1

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 40. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)

Symbol Parameter Conditions(1) Min(2) Typ(2) Max(2) Unit

LSEDRV = 0
- 500 -
Medium high drive capability
IDD(LSE) LSE current consumption nA
LSEDRV = 1
- 630 -
High drive capability
LSEDRV = 0
- - 1.7
Maximum critical crystal Medium high drive capability
Gmcritmax µA/V
gm LSEDRV = 1
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Specified by design. Not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

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Electrical characteristics STM32C091xB/xC STM32C092xB/xC

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 20. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

5.3.8 Internal clock source characteristics

The parameters given in Table 41 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI48) RC oscillator

Table 41. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 Frequency VDD=3.0 V, TA=30 °C 47.92 - 48.40 MHz

HSI48 oscillator frequency TA= 0 to 85 °C -1 - 1 %
∆Temp(HSI)(1) drift over temperature and
VDD full voltage range TA= -40 to 125 °C -2.5 - 2 %
From code 127 to
-8 -6 -4
128
From code 63 to 64
HSI48 oscillator frequency
TRIM(1) From code 191 to -5.8 -3.8 -1.8 %
user trimming step
192
For all other code
0.2 0.3 0.4
increments
DHSI48(2) Duty cycle - 45 - 55 %
tsu(HSI48)(2) HSI48 oscillator start-up time - - 1.4 1.8 μs
HSI48 oscillator stabilization at 1% of target
tstab(HSI48)(2) - 1.5 3.6 μs
time frequency
HSI48 oscillator power
IDD(HSI48)(1) - - 525 570 μA
consumption

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STM32C091xB/xC STM32C092xB/xC Electrical characteristics

1. Based on characterization results, not tested in production

2. Specified by design. Not tested in production.

Figure 21. HSI48 frequency versus temperature

Frequency [MHz]

Temperature

MS55839V1

Low-speed internal (LSI) RC oscillator

Table 42. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.3 V, TA = 25 °C 31.04 32 32.96

fLSI LSI frequency kHz
VDD = 2 V to 3.6 V, TA = -40 to 125 °C 29.5(1) - 34(1)
tSU(LSI)(2) LSI oscillator start-up time - - 80 130 μs
tSTAB(LSI)(2) LSI oscillator stabilization time 5% of final frequency - 125 180 μs
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
1. Evaluated by characterization. Not tested in production.
2. Specified by design. Not tested in production.

5.3.9 Flash memory characteristics

Table 43. Flash memory characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

tprog Word programming time 64 bits - 85.0 125.0 µs

Row (32 double word) Normal programming - 2.7 4.6

tprog_row ms
programming time Fast programming - 1.7 2.8

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91
Electrical characteristics STM32C091xB/xC STM32C092xB/xC

Table 43. Flash memory characteristics (continued)

Symbol Parameter(1) Conditions Min Typ Max Unit

Page (2 Kbyte) programming Normal programming - 21.8 36.6

tprog_page ms
time Fast programming - 13.7 22.4
tERASE Page (2 Kbyte) erase time - - 22.0 40.0 ms

Bank (256 Kbyte(2)) Normal programming - 0.7 1.2

tprog_bank s
programming time Fast programming - 0.5 0.7
tME Mass erase time - - 22.1 40.1 ms
Programming - 3.0 -
Average consumption from
IDD(FlashA) Page erase - 3.0 - mA
VDD
Mass erase - 5.0 -
Programming, 2 µs peak
- 7.0 -
IDD(FlashP) Maximum current (peak) duration mA
Erase, 41 µs peak duration - 7.0 -
1. Specified by design. Not tested in production.
2. Values provided also apply to devices with less flash memory than one 256 Kbyte bank

Table 44. Flash memory endurance and data retention

Symbol Parameter(1) Conditions Min Unit

NEND Endurance TJ = -40 to +130 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
1 kcycle(2) at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10
1. Evaluated by characterization. Not tested in production..
2. Cycling performed over the whole temperature range.

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5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.

Table 45. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHSE = fHCLK = 48 MHz, LQFP64, 2B
induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be applied VDD = 3.3 V, TA = +25 °C,
VFTB through 100 pF on VDD and VSS pins to induce a fHSE = fHCLK = 48 MHz, LQFP64, 4B
functional disturbance conforming to IEC 61000-4-2

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (for example control registers)

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Electrical characteristics STM32C091xB/xC STM32C092xB/xC

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
The following table gives the EMI characteristics for fHSI48 and fHCLK of 48 MHz.

Table 46. EMI characteristics

Max vs.
[fHSE/fCPU]
Monitored
Symbol Parameter Conditions Unit
frequency band
48 MHz /
48 MHz

0.1 MHz to 30 MHz 3

30 MHz to 130 MHz 8
Peak(1) VDD = 3.6 V, TA = 25 °C, dBµV
SEMI LQFP64 package 130 MHz to 1 GHz 6
compliant with IEC 61967-2
1 GHz to 2 GHz 7
Level(2) 0.1 MHz to 2 GHz 2 -
1. Refer to AN1709, section EMI radiated test
2. Refer to AN1709, section EMI level classification

5.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

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Table 47. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic
TA = +25 °C, conforming to
VESD(HBM) discharge voltage 2 2000
ANSI/ESDA/JEDEC JS-001
(human body model)
V
Electrostatic
TA = +25 °C, conforming to
VESD(CDM) discharge voltage C2a 500
ANSI/ESDA/JEDEC JS-002
(charge device model)
1. Evaluated by characterization. Not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 48. Electrical sensitivity

Symbol Parameter Conditions Class

LU Static latch-up class TA = +125 °C conforming to JESD78 II Level A

5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter: ADC error above a certain limit
(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional
limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.

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Table 49. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on
IINJ Any IO 5(1) NA mA
pin
1. Evaluated by characterization. Not tested in production.

5.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 24: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
For information on GPIO configuration, refer to the application note AN4899 STM32 GPIO
configuration for hardware settings and low-power consumption, available on the ST
website www.st.com.

Table 50. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

I/O input low level

VIL(1) All 2.0 V < VDDIO1 < 3.6 V - - 0.3 × VDDIO1 V
voltage
I/O input high level
VIH(1) All 2.0 V < VDDIO1 < 3.6 V 0.7 × VDDIO1 - - V
voltage
Vhys(2) I/O input hysteresis - - 200 - mV
0 < VIN ≤ VDDIO1 - - ±70
(3) Input leakage
Ilkg VDDIO1 ≤ VIN ≤ VDDIO1 +1 V - - 600 nA
current(3)
VDDIO1 + 1 V ≤ VIN - - 150
Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 kΩ
(4)

Weak pull-down
RPD V = VDDIO1 25 40 55 kΩ
equivalent resistor(4) IN
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 22: I/O input characteristics.
2. Specified by design. Not tested in production.
3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_leak_max = 10 μA + [number of I/Os where VIN is applied on the pad] × Ilkg(Max).
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).

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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 22.

Figure 22. I/O input characteristics

2.5 VIH spec 70 %

TTL requirement VIH (min) = 2 V VIH

2 VIH spec TTL
x
V DDIO
0. 7x
Voltage

(m in) =
1.5 nt V IH
ir eme 2
S requ > 1.6 VIL
C MO for V DDIOx
tion + 0.26
pro duc V DD IOx
VIL spec 30 %
1 d in .49 x x>
1.62
te )=0 for VDDIO
Tes V IH (m
in
- 0.06
lation VD DIOx
simu 0.39 x VIL spec TTL
d on ax) =
Base tion VIL
(m
0.3 x VDD TTL requirement VIL (max) = 0.8 V
n simu
la
VIL (max) =
0.5 Based
o irement
on CM OS requ
in producti
Tested

0
1 1.5 2 2.5 3 3.5
MSv72572V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to
±15 mA with relaxed VOL/VOH.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
• The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 21: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 21:
Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).

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Table 51. Output voltage characteristics(1)

Symbol Parameter Conditions Min Max Unit

VOL Output low level voltage CMOS port(2) - 0.4 V

|IIO| = 8 mA
VOH Output high level voltage VDDIO1 ≥ 2.7 V VDD - 0.4 - V

VOL(3) Output low level voltage TTL port(2) - 0.4 V

|IIO| = 8 mA
VOH(3) Output high level voltage VDDIO1 ≥ 2.7 V 2.4 - V

VOL(3) Output low level voltage All I/Os - 1.3 V

|IIO| = 20 mA
VOH(3) Output high level voltage VDDIO1 ≥ 2.7 V VDD- 1.3 - V

VOL(3) Output low level voltage |IIO| = 4 mA - 0.45 V

VOH(3) Output high level voltage VDDIO1 ≥ 2.0 V VDD - 0.45 - V
|IIO| = 20 mA
- 0.4
VOLFM+ Output low level voltage for an FT I/O VDDIO1 ≥ 2.7 V
(3) V
pin in FM+ mode |IIO| = 10 mA
- 0.4
VDDIO1 ≥ 2.0 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics. The sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ∑IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design. Not tested in production.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and
Table 52, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 24: General
operating conditions.

Table 52. I/O AC characteristics

Speed Symbol Parameter(1)(2) Conditions Min Max Unit
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 0.35
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 3.00
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 0.45
00
C=50 pF,2.7 V ≤ VDDIO1 ≤ 3.6 V - 100.00
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 225.00
Tr/Tf Output rise and fall time(3) ns
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 75.00
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 150.00

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Table 52. I/O AC characteristics (continued)

Speed Symbol Parameter(1)(2) Conditions Min Max Unit
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 10.00
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 2.00
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15.00
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 2.50
01
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30.00
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 60.00
Tr/Tf Output rise and fall time(3) ns
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15.00
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 30.00
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30.00
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 15.00
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60.00(4)
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 30.00
10
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 11.00
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 22.00
Tr/Tf Output rise and fall time(3) ns
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 4.00
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 8.00
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60.00(4)
C=30 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 30.00
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 80.00(4)
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 40.00
11
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 5.50
C=30 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 11.00
Tr/Tf Output rise and fall time(3) ns
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2.50
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 5.00
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0490 reference manual for a description of GPIO Port configuration register.
2. Specified by design. Not tested in production.
3. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.
4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.

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Figure 23. I/O AC characteristics definition(1)

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.

1. Refer to Table 52: I/O AC characteristics.

5.3.14 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU.
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 24: General operating conditions.

Table 53. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

NRST input low level

VIL(NRST) - - - 0.3 × VDD V
voltage
NRST input high level
VIH(NRST) - 0.7 × VDD - - V
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU(1) VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input filtered
VF(NRST) (1) 2.0 V < VDD < 3.6 V - - 70 ns
pulse
NRST input not filtered
VNF(NRST)(1) 2.0 V < VDD < 3.6 V 350 - - ns
pulse
1. Specified by design. Not tested in production..
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).

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Figure 24. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF(3)

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that, upon power-on, the level on the NRST pin can exceed the minimum VIH(NRST)
level specified in Table 53: NRST pin characteristics. Otherwise, the device does not exit the power-on
reset. This applies to any NRST configuration set through the NRST_MODE[1:0] bitfield, the GPIO mode
inclusive.
3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.15 Extended interrupt and event controller input (EXTI) characteristics

Table 54. EXTI input characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

PLEC Pulse length to event controller - 20 - - ns

1. Specified by design. Not tested in production.

5.3.16 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 55 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 24: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 55. ADC characteristics

(1)
Symbol Parameter Conditions Min Typ Max Unit

Analog supply
VDDA - 2.0 - 3.6 V
voltage
Positive reference
VREF+ - 2 - VDD V
voltage
ADC clock
fADC - 0.14 - 35 MHz
frequency
12 bits - - 2.50
10 bits - - 2.92
fs Sampling rate MSps
8 bits - - 3.50
6 bits - - 4.38

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Table 55. ADC characteristics (continued)

Symbol Parameter(1) Conditions Min Typ Max Unit

External trigger fADC = 35 MHz; 12 bits - - 2.33

fTRIG MHz
frequency 12 bits - - fADC/15
Conversion voltage
VAIN - 0 - VREF+(2) V
range
External input
RAIN - - - 50 kΩ
impedance
Internal sample and
CADC - - 5 - pF
hold capacitor
Conversion
tSTAB ADC power-up time LDO already started 2
cycle
fADC = 35 MHz 2.35 µs
tCAL Calibration time
- 82 1/fADC
1.5/fADC 1.5/fADC
CKMODE = 00 - -
+ 2/fPCLK + 3/fPCLK
ADC_DR register CKMODE = 01 4.5
WLATENCY
write latency
CKMODE = 10 8.5 1/fPCLK
CKMODE = 11 2.5
Trigger conversion CKMODE = 00 2 - 3 1/fADC
latency for regular
CKMODE = 01 6.5
and injected
tLATR
channels without CKMODE = 10 12.5 1/fPCLK
aborting the
conversion CKMODE = 11 3.5

0.043 - 4.59 µs
ts Sampling time fADC = 35 MHz
1.5 - 160.5 1/fADC
ADC voltage
tADCVREG regulator start-up - - - 20 µs
_STUP time
fADC = 35 MHz
Total conversion 0.40 - 4.95 µs
Resolution = 12 bits
time
tCONV ts + 12.5 cycles for successive
(including sampling
time) Resolution = 12 bits approximation 1/fADC
= 14 to 173
Laps of time allowed
between two
tIDLE - - - 100 µs
conversions without
rearm
fs = 2.5 MSps - 410 -
ADC consumption
IDDA(ADC) fs = 1 MSps - 164 - µA
from VDDA
fs = 10 kSps - 17 -

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Table 55. ADC characteristics (continued)

Symbol Parameter(1) Conditions Min Typ Max Unit

fs = 2.5 MSps - 65 -
ADC consumption
IDDV(ADC) fs = 1 MSps - 26 - µA
from VREF+
fs = 10 kSps - 0.26 -
1. Specified by design. Not tested in production.
2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate
functions for further details.

Table 56. Maximum ADC RAIN .

Sampling time at 35 MHz Max. RAIN(1)
Resolution Sampling cycle at 35 MHz
(ns) (Ω)

1.5 43 50
3.5 100 680
7.5 214 2200
12.5 357 4700
12 bits
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000
1.5 43 68
3.5 100 820
7.5 214 3300
12.5 357 5600
10 bits
19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000
1.5 43 82
3.5 100 1500
7.5 214 3900
12.5 357 6800
8 bits
19.5 557 12000
39.5 1129 27000
79.5 2271 50000
160.5 4586 50000

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Table 56. Maximum ADC RAIN . (continued)

Sampling time at 35 MHz Max. RAIN(1)
Resolution Sampling cycle at 35 MHz
(ns) (Ω)

1.5 43 390
3.5 100 2200
7.5 214 5600
12.5 357 10000
6 bits
19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000
1. Specified by design. Not tested in production.

Table 57. ADC accuracy

Symbol Parameter(1)(2) Conditions Min Typ Max Unit

VDDA = VREF+ = 3 V
Total - ±3 ±4
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C
ET unadjusted LSB
error 2 V < VDDA = VREF+ < 3.6 V
- ±3 ±6.5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
- ±1.5 ±2
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C
EO Offset error LSB
2 V < VDDA = VREF+ < 3.6 V
- ±1.5 ±4.5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
- ±3 ±3.5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
EG Gain error LSB
2 V < VDDA = VREF+ < 3.6 V
- ±3 ±5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
- ±1.2 ±1.5
Differential fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
ED LSB
linearity error 2 V < VDDA = VREF+ < 3.6 V
- ±1.2 ±1.5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
- ±2.5 ±3
Integral linearity fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
EL LSB
error 2V<V =V < 3.6 V
DDA REF+ - ±2.5 ±3
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
10.1 10.2 -
Effective fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
ENOB bit
number of bits 2 V < VDDA = VREF+ < 3.6 V
9.6 10.2 -
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range

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Table 57. ADC accuracy (continued)

Symbol Parameter(1)(2) Conditions Min Typ Max Unit

VDDA = VREF+ = 3 V
Signal-to-noise f 62.5 63 -
ADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
SINAD and distortion dB
ratio 2 V < VDDA = VREF+ < 3.6 V
59.5 63 -
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
63 64 -
Signal-to-noise ADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
f
SNR dB
ratio 2V<V =V < 3.6 V
DDA REF+ 60 64 -
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
- -74 -73
Total harmonic fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
THD dB
distortion 2 V < VDDA = VREF+ < 3.6 V
- -74 -70
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
1. Evaluated by characterization. Not tested in production.
2. ADC DC accuracy values are measured after internal calibration.

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Figure 25. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
n
(1) Example of an actual transfer curve
2 -1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

Figure 26. ADC typical connection diagram

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 55: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 50: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 50: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 2: Power supply overview.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 14: Power supply
scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.

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5.3.17 Temperature sensor characteristics

Table 58. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±5 °C

(2)
Avg_Slope Average slope from VSENSE voltage 2.4 2.53 2.65 mV/°C
V30(3) Voltage at 30°C (±5 °C) 0.742 0.76 0.786 V

tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode - 8 15 µs

tSTART(1) Start-up time when entering in continuous mode - 70 120 µs

tS_temp(1) ADC sampling time when reading the temperature 5 - - µs

Temperature sensor consumption from VDD, when

isens (1) - 4.7 7.0 µA
selected by ADC
1. Specified by design. Not tested in production.
2. Evaluated by characterization. Not tested in production.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.

5.3.18 Timer characteristics

The parameters given in the following tables are specified by design.
Note: TIMx is used as a general term to refer to a timer (for example, TIM1).
Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 59. TIMx characteristics

Symbol Parameter Conditions Min(1) Max(1) Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz 20.833 - ns
Timer external clock frequency
fEXT - 0 fTIMxCLK/4 MHz
on CH1 to CH4
TIMx other than TIM2 - 16
ResTIM Timer resolution bit
TIM2 - 32
TIMx other than TIM2 1 216
tCOUNTER Counter clock period tTIMxCLK
TIM2 1 232
1. Specified by design. Not tested in production.

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Table 60. IWDG min/max timeout period at 32 kHz LSI clock

Min timeout(1) Max timeout(1)
Prescaler divider PR[2:0] bits Unit
RL[11:0]= 0x000 RL[11:0] = 0xFFF

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an
uncertainty of one RC period.

5.3.19 Characteristics of communication interfaces

I2C-bus interface characteristics
The I2C-bus interface meets timing requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The timings are specified by design as long as the I2C peripheral is properly configured
(refer to the reference manual RM0490) and when the I2CCLK frequency is greater than the
minimum shown in the following table.

Table 61. Minimum I2CCLK frequency

Symbol Parameter Condition Typ Unit

Standard-mode 2
Analog filter enabled
9
DNF = 0
Fast-mode
Minimum I2CCLK Analog filter disabled
frequency for correct 9
fI2CCLK(min) DNF = 1 MHz
operation of I2C
peripheral Analog filter enabled
19
DNF = 0
Fast-mode Plus
Analog filter disabled
16
DNF = 1

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins

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support Fm+ low-level output current maximum requirement. Refer to Section 5.3.13: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its
characteristics:

Table 62. I2C analog filter characteristics

Symbol Parameter(1) Min Max Unit

Maximum pulse width of spikes that are

tAF 50(2) 150(3) ns
suppressed by the analog filter
1. Evaluated by characterization. Not tested in production.
2. Spikes with widths below tAF (min) are filtered.
3. Spikes with widths above tAF (max) are not filtered.

USART (SPI mode) characteristics

Unless otherwise specified, the parameters given in Table 63 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 24: General operating conditions. The additional general
conditions are:
• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 × VDD
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, and RX for USART).

Table 63. USART (SPI mode) characteristics

Symbol Parameter Conditions Min Typ Max Unit

Master mode
- - 6.0
2.0 V < VDD < 3.6 V
Slave receiver mode
fCK USART clock frequency - - 16.0 MHz
2.0 V < VDD < 3.6 V
Slave transmitter mode
- - 16.0
2.0 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode Tker(1) + 1 - - ns
th(NSS) NSS hold time Slave mode 2 - - ns
tw(CKH) CK high time 1 / fCK / 2 1 / fCK / 2
Master mode 1 / fCK / 2 ns
tw(CKL) CK low time -1 +1

Master mode
18.5 - -
2.0 V < VDD < 3.6 V
tsu(RX) ns
Slave mode 1.5 - -
Data input setup time
Master mode 0 - -
th(RX) Data input hold time ns
Slave mode 1.5 - -

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Table 63. USART (SPI mode) characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Slave mode
- 21.5
2.0 V < VDD < 3.6 V
13.5 ns
tv(TX) Data output valid time Slave mode
- 18
2.7 V < VDD < 3.6 V

Master mode - 2.0 4

Slave mode 11.5 - -

th(TX) Data output hold time ns
Master mode 0.5 - -
1. Tker is the usart_ker_ck_pres clock period

Figure 27. USART timing diagram in SPI master mode

1/fCK
tw(CKH)
CPHA=0
CK output

CPOL=0

CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output

CPOL=0

CPHA=1
CPOL=1
tsu(RX) th(RX)

RX input MSB IN BIT6 IN LSB IN

TX output MSB OUT BIT1 OUT LSB OUT

tv(TX) th(TX) MSv65386V6

Figure 28. USART timing diagram in SPI slave mode

NSS input

1/fCK th(NSS)

tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input

CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

tsu(RX) th(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V6

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SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 64 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 24: General operating conditions. The additional general conditions
are:
• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 × VDD
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 64. SPI characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit
Master mode
24
2 V < VDD < 3.6 V
SPI clock frequency Slave receiver mode 24
fSCK (2)
Slave transmitter mode/full duplex - - MHz
1/tc(SCK) 24
2.7 V < VDD < 3.6 V
Slave transmitter mode/full duplex(2)
22
2 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode 4 * TPCLK - - ns
th(NSS) NSS hold time Slave mode 2 * TPCLK - - ns
tw(SCKH) (3) (3)
TSCK2 TSCK2
SCK high and low times Master mode TPCLK ns
tw(SCKL) -1 +1
Data input setup time in
tsu(MI) - 4.5 - - ns
master mode
Data input setup time in
tsu(SI) - 2.5 - - ns
slave mode
Data input hold time in
th(MI) - 2.5 - - ns
master mode
Data input hold time in
th(SI) - 3 - - ns
slave mode
Data output access
ta(SO) - 10 - 34 ns
time in slave mode
Data output disable
tdis(SO) - 9 - 16 ns
time in slave mode
2.7 V < VDD < 3.6 V - 12 16
tv(SO) Data output valid time ns
2 V < VDD < 3.6 V - 12 22
in slave mode
Data output valid time
tv(MO) - - 3 5.5 ns
in master mode
Data output hold time in
th(SO) - 10 - - ns
slave mode
Data output hold time in
th(MO) - 1.5 - - ns
master mode
1. Evaluated by characterization. Not tested in production.

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2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
3. TSCK2 = TPCLK * prescaler / 2

Figure 29. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

Figure 30. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK)

tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V1

1. Measurement points are done at 0.5 VDD and with external CL = 30 pF.

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Figure 31. SPI timing diagram - master mode

High
NSS input
tc(SCK)
SCK Output

CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT

tv(MO) th(MO)

ai14136c

1. Measurement points are done at 0.5 VDD and with external CL = 30 pF.

Table 65. I2S characteristics

Symbol Parameter(1) Conditions Min Max Unit

fMCK I2S main clock output - - 48 MHz

Master TX - 12
Master RX - 12
fCK I2S clock frequency MHz
Slave TX - 15
Slave RX - 48

tv(WS) WS valid time Master mode - 5 ns

th(WS) WS hold time Master mode 0 - ns

tsu(WS) WS setup time Slave mode 3.5 - ns

th(WS) WS hold time Slave mode 1 - ns

tsu(SD_MR) Master receiver 5 - ns
Data input setup time
tsu(SD_SR) Slave receiver 2.5 - ns
th(SD_MR) Master receiver 2.5 - ns
Data input hold time
th(SD_SR) Slave receiver 1 - ns

tv(SD_ST) Slave transmitter (after enable edge) - 19.5 ns

Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 5 ns

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Table 65. I2S characteristics

Symbol Parameter(1) Conditions Min Max Unit

th(SD_ST) Slave transmitter (after enable edge) 11 - ns

Data output hold time
th(SD_MT) Master transmitter (after enable edge) 1 - ns

1. Evaluated by characterization. Not tested in production.

Figure 32. I2S slave timing diagram (Philips protocol)

tc(CK)

CPOL = 0
CK Input

CPOL = 1

tw(CKH) tw(CKL) th(WS)

WS input

tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit LSB transmit(2) MSB transmit Bitn transmit

tsu(SD_SR) th(SD_SR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

MSv39721V1

1. Measurement points are done at CMOS levels: 0.3 × VDDIO1 and 0.7 × VDDIO1.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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Figure 33. I2S master timing diagram (Philips protocol)

90%
10%
tf(CK) tr(CK)

tc(CK)
CK output

CPOL = 0
tw(CKH)

CPOL = 1
tv(WS) tw(CKL) th(WS)

WS output

tv(SD_MT) th(SD_MT)

SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_MR) th(SD_MR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

MSv39720V1

1. Evaluated by characterization. Not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.
1. Drawing is not to scale.

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6.2 TSSOP20 package information (YA)

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch.

Figure 34. TSSOP20 – Outline

20 11
c

E1 E
SEATING 0.25 mm
PLANE GAUGE PLANE
C
1 10

PIN 1
IDENTIFICATION
k
aaa C A1 L
A A2
L1

b e

YA_ME_V3

1. Drawing is not to scale.

Table 66. TSSOP20 – Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
D(2) 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.

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Figure 35. TSSOP20 – Footprint example

0.25
6.25
20 11

1.35

0.25

7.10 4.40

1.35

1 10

0.40 0.65 YA_FP_V1

1. Dimensions are expressed in millimeters.

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6.3 WLCSP24 package information (B0Q3)

This WLCSP is a 24-ball, 2.61 x 1.73 mm, 0.35 mm pitch, wafer level chip scale package.

Figure 36. WLCSP24 - Outline

Back side coating bbb C A3

E1
(Datum A)
A1 ball corner Silicon
7 5 3 1
eD 6 4 2 A2

A
Solder balls
B
C A1

D Seating plane
D1
SD (Datum B) E
C ccc C
F
eS G

DETAIL A
eE Ø b (N balls)
SE Øddd M C A B

BOTTOM VIEW
(balls side)
Detail A
A

Seating plane

FRONT VIEW

E A

(Datum B)

aaa C
B
(4x) (Datum A)
A1 ball corner
TOP VIEW
(marking side)
B0Q3_WLCSP24_ME_V1

1. Drawing is not to scale.

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Table 67. WLCSP24 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) - - 0.60 - - 0.0236
(3)
A1 0.12 - - 0.0047 - -
A2 - 0.38 - - 0.0150 -
A3 - 0.025 - - 0.0010 -
b(4) 0.19 0.23 0.26 0.0075 0.0091 0.0102
(5) 2.61 BSC
D 0.1028 BSC

D1(5) 1.82 BSC 0.0717 BSC

(5)
E 1.73 BSC 0.0681 BSC
(5)
E1 1.05 BSC 0.0413 BSC
eD(5)(6) 0.61 BSC 0.0240 BSC
eE(5)(6) 0.35 BSC 0.0138 BSC
(5)(6)
eS 0.35 BSC 0.0138 BSC
N(7) 24
SD(5)(8) 0.61 BSC 0.0240 BSC
SE(5)(8) 0.35 BSC 0.0138 BSC
aaa(9) 0.02 0.0008
(9)
bbb 0.06 0.0024
ccc(9) 0.03 0.0012
ddd(9) 0.015 0.0006
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The profile height A is the distance from the seating plane to the highest point on the package. It is
measured perpendicular to the seating plane.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to Datum C.
5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For
tolerances, refer to form and position table. On the drawing, these dimensions are framed. For the
tolerances, refer to form and position values.
6. e represents the solder balls grid pitch(es).
7. N represents the total number of balls.
8. Basic dimensions SD & SE are defining the ball matrix position with respect to datums A and B.
9. Tolerance of form and position drawing.

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Figure 37. Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 68. WLCSP24 - Example of PCB design rules

Dimension Recommended values

Pitch 0.35 mm
Dpad 0.200 mm
Dsm 0.275 mm
Stencil thickness 0.08 mm

Marking example
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks that identify the parts throughout supply chain
operations, are not indicated.

Figure 38. WLCSP24 package marking example

Pin 1 identifier

C091C Product identifier

Date code Y WW Additional information

MSv66181V2

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6.4 UFQFPN28 package information (A0B0)

UFQFPN28 is a 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 39. UFQFPN28 - Outline

D Detail Y

D1

E1

Detail Z
A0B0_ME_V5

1. Drawing is not to scale.

Table 69. UFQFPN28 – Mechanical data(1)

millimeters inches
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 - 0.000 0.050 - 0.0000 0.0020
D 3.900 4.000 4.100 0.1535 0.1575 0.1614
D1 2.900 3.000 3.100 0.1142 0.1181 0.1220
E 3.900 4.000 4.100 0.1535 0.1575 0.1614
E1 2.900 3.000 3.100 0.1142 0.1181 0.1220
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
L1 0.250 0.350 0.450 0.0098 0.0138 0.0177
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 40. UFQFPN28 – Footprint example

3.30

0.50

0.21

3.20
0.20
4.30
3.20 3.30

0.21
0.30
0.50
0.55
0.50

3.30

A0B0_FP_V3

1. Dimensions are expressed in millimeters.

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6.5 LQFP32 package information (5V)

This LQFP is a 32-pin, 7 x 7 mm, low-profile quad flat package.
Note: Figure 41 is not to scale.
Refer to the notes section for the list of notes on Figure 41 and Table 70.

Figure 41. LQFP32 - Outline

BOTTOM VIEW

2 1
(2)
(6) R1

D 1/4 H
R2

B
B-
N
O
TI
E 1/4

C
SE
B GAUGE PLANE
4x N/4 TIPS

0.25
aaa C A-B D bbb H A-B D 4x S
N B
L
3
(L1)
(1) (11)

SECTION A-A

(N – 4)x e (13)

C
A

A2 A1 b ddd C A-B D
0.05 (12) ccc C

D (4)
(9) (11)
(2) (5)
b WITH PLATING
D1
D (3)
(10)

(11) c
1
c1(11)
2 E 1/4
(3) A B
3
D 1/4
E1 E b1 BASE METAL
(6) (2) (4) (11)
(3) (5)

A A SECTION B-B
(Section A-A)

TOP VIEW 5V_LQFP32_ME_V1

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Table 70. LQFP32 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b(9)(11) 0.30 0.37 0.45 0.0118 0.0146 0.0177
(11)
b1 0.30 0.35 0.40 0.0118 0.0128 0.0157
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
D1(2)(5) 7.00 BSC 0.2756 BSC
e 0.80 BSC 0.0315 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 32
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7)(15) 0.20 0.0079
(1)(7)(15)
bbb 0.20 0.0079
ccc(1)(7)(15) 0.10 0.0039
(1)(7)(15)
ddd 0.20 0.0079

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. The minimum space
between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch
packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Recommended values and tolerances.

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Figure 42. LQFP32 – Footprint example

0.45 0.8

32 25
1.2 REF
1 24

7.4

9.8
8 17

9 16

7.4

9.8

Soldering area

Solder resist opening

5V_LQFP32_FP_V4

1. Dimensions are expressed in millimeters.

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6.6 UFQFPN32 package information (A0B8)

This UFQFPN is a 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.

Figure 43. UFQFPN32 - Outline

K fff CAB
D2 EXPOSED PAD

b
fff CAB

bbb CA B
ddd C

E2
e 2xR

Detail A
b
L
PIN 1 identifier

e L
Detail A

BOTTOM VIEW

A
ccc C
A1
SEATING
eee C PLANE
C

Detail B
FRONT VIEW
A1
B
PIN 1 identifier

Detail B
E

D A

TOP VIEW
A0B8_UFQFPN32_ME_V5

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.

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Table 71. UFQFPN32 - Mechanical data

millimeters(1) inches(2)
Symbol
Min Typ Max Min Typ Max

A(3)(4) 0.50 0.55 0.60 0.0197 0.0217 0.0236

(5)
A1 0.00 - 0.05 0.000 - 0.0020
b(6) 0.18 0.25 0.30 0.0071 0.0098 0.0118
D(7) 5.00 BSC 0.1969 BSC
(8)
D2 See Table 73: Exposed pad variation
(7)
E 5.00 BSC 0.1969 BSC
E2(8) See Table 73: Exposed pad variation
e 0.50 BSC 0.0197 BSC
(9)
N 32
L 0.30 - 0.50 0.0118 - 0.0197
R 0.09 - - 0.0035 - -
1. All dimensions are in millimeters. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2018
except European.
2. Values in inches are converted from mm and rounded to four decimal digits.
3. UFQFPN stands for ultra thin fine pitch quad flat package no lead: A ≤ 0.60 mm / Fine pitch e ≤ 1.00 mm.
4. The profile height, A, is the distance from the seating plane to the highest point on the package. It is
measured perpendicular to the seating plane.
5. A1 is the vertical distance from the bottom surface of the plastic body to the nearest metalized package
feature.
6. Dimension b applies to metalized terminal. If the terminal has the optional radius on the other end of the
terminal, the dimension b must not be measured in that radius area.
7. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For
tolerances, refer to Table 72.
8. Dimensions D2 and E2 refer to the exposed pad. For variance, refer to Table 73.
9. N represents the total number of terminals.

Table 72. Tolerance of form and position

Symbol Millimeters(1) Inches(2)

aaa 0.15 0.0059

bbb 0.10 0.0039
ccc 0.10 0.0039
ddd 0.05 0.0020
eee 0.08 0.0315
fff 0.10 0.0039
1. All dimensions are in millimeters. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2018
except European.
2. Values in inches are converted from mm and rounded to four decimal digits.

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Table 73. Exposed pad variation

D2 E2
Option
Min Typ Max Min Typ Max

1 3.40 3.50 3.60 3.40 3.50 3.60

2 3.50 3.60 3.70 3.50 3.60 3.70
3 3.60 3.70 3.80 3.60 3.70 3.80

Figure 44. UFQFPN32 - Footprint example

5.50

3.75

0.65

3.60

5.50 3.75

3.60
0.50
0.25

3.75
A0B8_UFQFPN32_FP_V1

1. Dimensions are expressed in millimeters.

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6.7 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 45. LQFP48 - Outline(15)

BOTTOM VIEW

4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1

H
R2

B
B-
D 1/4

N
O
(6)

TI
C
SE
B GAUGE PLANE
E 1/4

0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)

A A2 C SECTION A-A

(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING

1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)

SECTION B-B

TOP VIEW

5B_LQFP48_ME_V1

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Table 74. LQFP48 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 46. LQFP48 - Footprint example

0.50
1.20

36 25
37 24 0.30

0.20

9.70 7.30

48 13
1 12

5.80

9.70
5B_LQFP48_FP_V1

1. Dimensions are expressed in millimeters.

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6.8 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 47. UFQFPN48 – Outline

D1 EXPOSED PAD

E2 E1
e

PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE

C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW

A1 A
SEATING PLANE

ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA

TOP VIEW

A0B9_UFQFPN48_ME_V4

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.

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Table 75. UFQFPN48 – Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.

Figure 48. UFQFPN48 – Footprint example

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3

1. Dimensions are expressed in millimeters.

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6.9 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 49. LQFP64 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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Table 76. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
E1(2)(5) 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
q 0° 3.5° 7° 0° 3.5° 7°
q1 0° - - 0° - -
q2 10° 12° 14° 10° 12° 14°
q3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
bbb(1) 0.20 0.0079
(1)
ccc 0.08 0.0031
(1)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 50. LQFP64 - Footprint example

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

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6.10 UFBGA64 package information (A019)

This UFBGA is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 51. UFBGA64 – Outline(13)

E1

e SE

H
G
SD F
E e
D1
D
C
B
A

1 2 3 4 5 6 7 8
Øb (N balls)
A1 ball pad corner Ø eee M C A B
Ø fff M C
Mold resin
ccc C

Substrate

Detail A A
SIDE VIEW Seating plane

(8)

A1 A2
B C
E A Detail A
A1 ball pad corner ddd C
(9) Solder balls

(DATUM A)

(DATUM B)

aaa C
TOP VIEW (4X)
A019_UFBGA64_ME_V2

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Table 77. UFBGA64 – Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 0.60 - - 0.0236

(4)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(5)
b 0.23 0.28 0.33 0.0090 0.0110 0.0130
(6)
D 5.00 BSC 0.1969 BSC
D1 3.50 BSC 0.1378 BSC
E 5.00 BSC 0.1969 BSC
E1 3.50 BSC 0.1378 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(11) 64
SD(12) 0.25 BSC 0.0098 BSC
SE(12) 0.25 BSC 0.0098 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. UFBGA stands for ultra profile fine pitch ball grid array: 0.5 mm < A ≤ 0.65 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 52. UFBGA64 – Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 78. UFBGA64 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.5 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

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6.11 Thermal characteristics

The operating junction temperature TJ must never exceed the maximum given in Table 24:
General operating conditions.
The maximum junction temperature in °C that the device can reach if respecting the
operating conditions, is:
TJ(max) = TA(max) + PD(max) x ΘJA
where:
• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O,
– PINT is power dissipation contribution from product of IDD and VDD
– PI/O is power dissipation contribution from output ports where
PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL
/ IOL and VOH / IOH of the I/Os at low and high level in the application.

Table 79. Thermal resistance

Symbol Parameter Package(1) Value Unit
TSSOP20 81
WLCSP24 92.2
UFQFPN28 57.2
UFQFPN32 42
Thermal resistance
ΘJA LQFP32 51.4 °C/W
junction-ambient
UFQFPN48 31.9
LQFP48 51.7
LQFP64 43
UFBGA64 66.5
TSSOP20 54.7
WLCSP24 60.7
UFQFPN28 22.2
UFQFPN32 23.9
Thermal resistance
ΘJB LQFP32 28.5 °C/W
junction-board
UFQFPN48 16.2
LQFP48 28.8
LQFP64 25.3
UFBGA64 49.3

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Table 79. Thermal resistance

Symbol Parameter Package(1) Value Unit
TSSOP20 26.6
WLCSP24 7
UFQFPN28 25.4
UFQFPN32 17.2
Thermal resistance
ΘJC LQFP32 16.3 °C/W
junction-case
UFQFPN48 12.8
LQFP48 16.6
LQFP64 12.6
UFBGA64 23.2
1. Refer to Section 6: Package information for package dimensions

6.11.1 Reference documents

[1] Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection
(Still Air) (JESD51-2A), JEDEC, January 2008. Available from www.jedec.org.

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7 Ordering information

Example STM32 C 09x R C T 3 xyy

Device family
STM32 = Arm® based 32-bit microcontroller

Product type
C = general-purpose

Device subfamily
09x = 091 (STM32C091) or 092 (STM32C092)

Pin count
F = 20
E = 24
G = 28
K = 32
C = 48
R = 64

Flash memory size

B = 128 Kbytes
C = 256 Kbytes

Package type
I = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
P = TSSOP

Temperature range
6 = -40 to 85°C (105°C junction)
7 = -40 to 105°C (125°C junction)
3 = -40 to 125°C (130°C junction)

Options
TR = tape and reel packing
= tray packing
other = 3-character ID incl. custom flash memory code and packing information

For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact your nearest ST sales office.

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8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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9 Revision history

Table 80. Document revision history

Date Revision Changes

02-Dec-2024 1 Initial release.

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IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.

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