50 programs-

Verilog module

aruNaCHala
College oF
eNgiNeeriNg For
WomeN

VaisHNaVi s m
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 Verilog allows circuit design
Verilog using three different modeling
Verilog is a Hardware styles:
Description Language (HDL) Structural Modeling (Gate-Level)
used to design and model digital
circuits. Unlike regular Dataflow Modeling (Equation-
programming languages, Verilog Based)
describes how hardware (like Behavioral Modeling (High-
logic gates, multiplexers, Level Code)
registers, and processors) should
Structural Modeling = Like
function. It allows engineers to: physically wiring gates in
hardware.
Dataflow Modeling = Like
Design digital circuits (e.g.,
writing equations for circuits.
adders, multiplexers, processors) Behavioral Modeling = Like
Simulate circuits before coding circuit behavior with if-
manufacturing them else and loops.
Implement hardware on FPGAs
or ASICs

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aNd gate struCtural
module and_gate_structural
BeHaVior (input A, input B, output Y);
module or_gate (
input A, B, and (Y, A, B);
output reg Y
); endmodule
always @(A or B) begin
Y = A&&B;
end
endmodule

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or gate struCtural
BeHaViour module OR_Gate_Structural
(input A, input B, output Y);
or (Y, A, B);
module or_gate (
endmodule
input A, B,
output reg Y
);
always @(A or B) begin
Y = A | B;
end
endmodule

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Not gate struCtural
BeHaViour module NOT_GATE_Structural
(input A, output Y);
module NOT_gate (
not (Y, A);
input A,
endmodule
output reg Y
);
always @(A ) begin
Y =~A;
end
endmodule

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NaNd gate struCtural
BeHaViour module
NAND_GATE_Structural (input
module NOT_gate ( A,inputB output Y);
input A,B, nand (Y, A, B);
output reg Y endmodule
);
always @(A or B) begin
Y =~(A & B);
end
endmodule

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Nor gate struCtural
BeHaViour module NOR_GATE_Structural
(input A,input B output Y);
module NOR_gate (
nor (Y, A, B);
input A,B,
endmodule
output reg Y
);
always @(A or B) begin
Y =~(A|B);
end
endmodule

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Xor gate struCtural
BeHaViour module XOR_GATE_Structural
(input A,input B output Y);
module XOR_gate (
xor (Y, A, B);
input A,B,
endmodule
output reg Y
);
always @(A or B) begin
Y =(A^B);
end
endmodule

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XNor gate struCtural
BeHaViour module
XNOR_GATE_Structural (input
module XNOR_gate ( A,input B output Y);
input A,B, xnor (Y, A, B);
output reg Y endmodule
);
always @(A or B) begin
Y =^(A~B);
end
endmodule

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HalF adder struCtural
BeHaViour module half_adder_structural (
input wire a, b,
module half_adder_behavioral (
output wire sum, carry
input A, B,
);
output reg sum, carry
xor(sum, a, b);
);
and(carry, a, b);
always @(A or B) begin
endmodule
sum = A ^ B;
carry = A & B;
end
endmodule

data FloW

module half_adder_dataflow (
input wire a, b,
output wire sum, carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule

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Full adder struCtural
BeHaViour module full_adder_structural (
input A, B, Cin,
module full_adder_behavioral (
output Sum, Cout
input A, B, Cin,
);
output reg Sum, Cout
xor (Sum, A, B, Cin);
);
or (Cout, (A & B), (B & Cin),
always @(A or B or Cin) begin
(A & Cin));
Sum = A ^ B ^ Cin;
endmodule
Cout = (A & B) | (B & Cin) |
(A & Cin);
end
endmodule

data FloW
module full_adder_dataflow (
input A, B, Cin,
output wire Sum, Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B &
Cin) | (A & Cin);
endmodule

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suBtraCtor less = 0;

module subtractor(a, b, diff, end else begin

borrow); greater = 0;
input a, b; equal = 0;
output diff, borrow; less = 1;
reg y; end
end
always @ (a or b)
{borrow, diff} = a - b; endmodule
endmodule

Comparator
module comparator(a, b, greater,
equal, less);
input [3:0] a, b;
output reg greater, equal, less;

always @(*) begin

if (a > b) begin
greater = 1;
equal = 0;
less = 0;
end else if (a == b) begin
greater = 0;
equal = 1;

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paritY eNCoder
module encoder_4to2(input [3:0] t FlipFlop
data, output reg [1:0] encoded); module T_flipflop ( input T, clk,
output reg Q
always @(data) begin );
case (data) always @(posedge clk) begin
4'b1000: encoded = 2'b11; if (T == 1)
4'b0100: encoded = Q <= ~Q;
2'b10; else
4'b0010: encoded = Q <= Q;
2'b01;
end
4'b0001: encoded =
2'b00; endmodule

default: encoded = 2'bxx; JK FlipFlop

endcase module jk_flipflop (
end input clk,
endmodule input j,
arraY multiplier input k,

module array_multiplier ( input reset,

input [3:0] A, B, output reg q,

output [7:0] P output reg qbar

); );

assign P = A * B;
endmodule always @(posedge clk or
posedge reset) begin

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 if (reset) begin always @(posedge clk or
q <= 0; posedge reset) begin

qbar <= 1; if (reset)

end else begin q <= 4'b0000;

case ({j, k}) else

2'b00: q <= q; q <= {q[2:0], d};

2'b01: q <= 0; end

2'b10: q <= 1;
2'b11: q <= ~q; endmodule

endcase up CouNter
qbar <= ~q; module up_counter (
end input clk,
end input reset,
endmodule output reg [3:0] q
);

sHiFt registers
module shift_register ( always @(posedge clk or
posedge reset) begin
input clk,
if (reset)
input reset,
q <= 4'b0000;
input d,
else
output reg [3:0] q
q <= q + 1;
);
end

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endmodule input d,

up doWN CouNter input enable,

output reg q,
module updown_counter (
output qbar
input clk,
);
input reset,
assign qbar = ~q;
input up_down,
output reg [3:0] q
always @(*) begin
);
if (enable)

always @(posedge clk or q <= d;

posedge reset) begin end
if (reset) endmodule
q <= 4'b0000; struCture model
else if (up_down) module d_latch_structural (
q <= q + 1; input d, clk,
else output q, qbar
q <= q - 1; );
end wire dbar, r1, r2;
not (dbar, d);
endmodule nand (r1, d, clk);
d latCH nand (r2, dbar, clk);

BeHaViour model nand (q, r1, qbar);

nand (qbar, r2, q);
module d_latch (
endmodule

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d FlipFlop output q, qbar
);
BeHaViour model
module d_flipflop (
wire dbar, r1, r2, r3, r4, s1, s2;
input clk,
not (dbar, d);
input reset,
nand (r1, d, clk);
input d,
nand (r2, dbar, clk);
output reg q,
nand (s1, r1, s2);
output qbar
nand (s2, r2, s1);
);

nand (r3, s1, reset);

assign qbar = ~q;
nand (r4, s2, reset);
nand (q, r3, qbar);
always @(posedge clk or
nand (qbar, r4, q);
posedge reset) begin
endmodule
if (reset)
q <= 0; sr FlipFlop
else module sr_flipflop (
q <= d; input clk,
end input reset,
endmodule input s,

struCtural model input r,

output reg q,
module d_flipflop_structural (
output qbar
input d, clk, reset,
);

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 assign product = a * b;
assign qbar = ~q;
endmodule
always @(posedge clk or 1:2 demultipleXer
posedge reset) begin
module demux_1to2 (
if (reset)
input din,
q <= 0;
input sel,
else begin
output reg d0,
case ({s, r})
output reg d1
2'b00: q <= q;
);
2'b01: q <= 0;
2'b10: q <= 1;
always @(din, sel) begin
2'b11: q <= 1'bx;
if (sel == 0) begin
endcase
d0 = din;
end
d1 = 0;
end
end else begin
endmodule
d0 = 0;
multiplier d1 = din;
module multiplier ( end
input [3:0] a, end
input [3:0] b,
output [7:0] product endmodule
);
demultipleXer

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module demux_1to4 ( input [1:0] sel,
input din, output reg dout
input [1:0] sel, );
output reg [3:0] dout
); always @(din or sel) begin
case (sel)
always @(din or sel) begin 2'b00: dout = din[0];
dout = 4'b0000; 2'b01: dout = din[1];
case (sel) 2'b10: dout = din[2];
2'b00: dout[0] = din; 2'b11: dout = din[3];
2'b01: dout[1] = din; endcase
2'b10: dout[2] = din; end
2'b11: dout[3] = din; endmodule
endcase BeHaVioral model
end (usiNg iF-else
statemeNt)
endmodule
module mux_4to1_if_else (
4:1 multipleXer input [3:0] din,
BeHaVioral model input [1:0] sel,

(usiNg Case output reg dout

statemeNt) );

module mux_4to1_behavioral (
always @(din or sel) begin
input [3:0] din,
if (sel == 2'b00)

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 dout = din[0]; endmodule
else if (sel == 2'b01) struCtural modeliNg
dout = din[1]; module mux_4to1_structural (
else if (sel == 2'b10) input [3:0] din,
dout = din[2]; input [1:0] sel,
else output dout
dout = din[3]; );
end

wire s0, s1, y0, y1, y2, y3;

endmodule

dataFloW model not (s0, sel[0]);

(usiNg assigN not (s1, sel[1]);
statemeNt)
module mux_4to1_dataflow ( and (y0, din[0], s1, s0);
input [3:0] din, and (y1, din[1], s1, sel[0]);
input [1:0] sel, and (y2, din[2], sel[1], s0);
output dout and (y3, din[3], sel[1], sel[0]);
);
or (dout, y0, y1, y2, y3);
assign dout = (sel == 2'b00 &
din[0]) | endmodule
(sel == 2'b01 & din[1]) |
2:1 multipleXer
(sel == 2'b10 & din[2]) |
(sel == 2'b11 & din[3]);

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BeHaVioral model always @(d0 or d1 or sel) begin

(usiNg Case) if (sel == 0)

dout = d0;
module mux_2to1_case (
else
input d0, d1,
dout = d1;
input sel,
end
output reg dout
endmodule
);
dataFloW model
always @(d0 or d1 or sel) begin module mux_2to1_dataflow (
case (sel) input d0, d1,
1'b0: dout = d0; input sel,
1'b1: dout = d1; output dout
endcase );
end assign dout = (sel & d1) | (~sel &
d0);
endmodule
endmodule
BeHaVioral model
(usiNg iF-else) struCtural model
module mux_2to1_structural (
module mux_2to1_if_else (
input d0, d1,
input d0, d1,
input sel,
input sel,
output dout
output reg dout
);
);

wire not_sel, y0, y1;

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 3'b111: dout = din[7];
not (not_sel, sel); endcase
and (y0, d0, not_sel); end
and (y1, d1, sel); endmodule
or (dout, y0, y1); BeHaVioral model
endmodule (usiNg iF-else)
multipleXer module mux_8to1_if_else (

BeHaVioral model input [7:0] din,

(usiNg Case) input [2:0] sel,

output reg dout
module mux_8to1_case (
);
input [7:0] din,
always @(din or sel) begin
input [2:0] sel,
if (sel == 3'b000) dout =
output reg dout
din[0];
);
else if (sel == 3'b001) dout =
always @(din or sel) begin din[1];
case (sel) else if (sel == 3'b010) dout =
3'b000: dout = din[0]; din[2];
3'b001: dout = din[1]; else if (sel == 3'b011) dout =
din[3];
3'b010: dout = din[2];
else if (sel == 3'b100) dout =
3'b011: dout = din[3];
din[4];
3'b100: dout = din[4];
else if (sel == 3'b101) dout =
3'b101: dout = din[5]; din[5];
3'b110: dout = din[6]; else if (sel == 3'b110) dout =
din[6];

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 else dout = din[7]; CopyEdit struCtural
end model
endmodule
module mux_8to1_structural (
dataFloW model input [7:0] din,
module mux_8to1_dataflow ( input [2:0] sel,
input [7:0] din, output dout
input [2:0] sel, );
output dout wire s0, s1, s2;
); wire y0, y1, y2, y3, y4, y5, y6,
assign dout = (sel == 3'b000 & y7;
din[0]) |
(sel == 3'b001 & din[1]) not (s0, sel[0]);
| not (s1, sel[1]);
(sel == 3'b010 & din[2])
not (s2, sel[2]);
|
(sel == 3'b011 & din[3])
| and (y0, din[0], s2, s1, s0);
(sel == 3'b100 & din[4]) and (y1, din[1], s2, s1, sel[0]);
| and (y2, din[2], s2, sel[1], s0);
(sel == 3'b101 & din[5]) and (y3, din[3], s2, sel[1], sel[0]);
|
and (y4, din[4], sel[2], s1, s0);
(sel == 3'b110 & din[6])
and (y5, din[5], sel[2], s1, sel[0]);
|
and (y6, din[6], sel[2], sel[1], s0);
(sel == 3'b111 & din[7]);
and (y7, din[7], sel[2], sel[1],
Endmodule
sel[0]);
verilog

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 output reg [3:0] bin
or (dout, y0, y1, y2, y3, y4, y5, );
y6, y7);
endmodule always @(gray) begin
BiNarY to graY Code bin[3] = gray[3];
CoNVerter bin[2] = bin[3] ^ gray[2];
(BeHaVioral model) bin[1] = bin[2] ^ gray[1];
module binary_to_gray ( bin[0] = bin[1] ^ gray[0];
input [3:0] bin, end
output reg [3:0] gray endmodule
); ripple CarrY adder
BeHaVioral model
always @(bin) begin
(usiNg alWaYs
gray[3] = bin[3];
BloCK)
gray[2] = bin[3] ^ bin[2];
module
gray[1] = bin[2] ^ bin[1]; ripple_carry_adder_behavioral (
gray[0] = bin[1] ^ bin[0]; input [3:0] a, b,
end input cin,
endmodule output reg [3:0] sum,
graY to BiNarY Code output reg cout
CoNVerter );
(BeHaVioral model)
module gray_to_binary ( always @(a or b or cin) begin
input [3:0] gray, {cout, sum} = a + b + cin;

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end module
endmodule ripple_carry_adder_structural (
input [3:0] a, b,
dataFloW model
input cin,
(usiNg assigN)
output [3:0] sum,
module
output cout
ripple_carry_adder_dataflow (
);
input [3:0] a, b,
wire c1, c2, c3;
input cin,
full_adder FA0 (a[0], b[0], cin,
output [3:0] sum,
sum[0], c1);
output cout
full_adder FA1 (a[1], b[1], c1,
); sum[1], c2);
assign {cout, sum} = a + b + cin; full_adder FA2 (a[2], b[2], c2,
endmodule sum[2], c3);
full_adder FA3 (a[3], b[3], c3,
struCtural model
sum[3], cout);
(usiNg Full adders) endmodule
module full_adder (
input a, b, cin,
BootH arraY
output sum, cout
multiplier
);
module booth_multiplier (
assign sum = a ^ b ^ cin;
input [3:0] multiplicand,
assign cout = (a & b) | (b & cin) |
(a & cin); input [3:0] multiplier,
endmodule output [7:0] product
);

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reg [7:0] p;
integer i;
reg prev_bit;
always @(multiplicand,
multiplier) begin
p = 0;
prev_bit = 0;
for (i = 0; i < 4; i = i + 1) begin
case ({multiplier[i],
prev_bit})
2'b10: p = p -
(multiplicand << i);
2'b01: p = p +
(multiplicand << i);
2'b00: p = p;
2'b11: p = p;
endcase
prev_bit = multiplier[i];
end
end
assign product = p;
endmodule

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