Ahmad GHANAATIAN-JAHROMI1, Adib ABRISHAMIFAR1, Ali MEDI2

Iran University of Science and Technology (1), Sharif University of Technology (2)

A novel voltage-to-voltage logarithmic converter with high

accuracy

Abstract. A novel BiCMOS voltage-to-voltage converter with logarithmic characteristics and very high accuracy is presented. The relationship
between the emitter current and the base-emitter voltage in bipolar transistors is used to realize the logarithmic function. With 1.8 supply voltage, the
total power consumption is less than 15.75 mW and a Log error of < -36dB is shown in the ADS simulations. Compared to the other method in the
literature, very better accuracy in logarithm calculation is achieved. The proposed method can be used in arithmetical operation circuits like analog
processors.

Streszczenie. Przedstawiono nowy przetwornik logarytmujący w technologii BiCMOS. Do realizacji funkcji logarytmującej użyto zależności między
prądem emitera i napięciem baza-emiter w tranzystorze bipolarnym. Przy napięciu zasilającym 1.8V pobór mocy był mniejszy niż 15.75 mW a błąd
logarytmowania był mniejszy niż -36dB. W porównaniu z podobnymi układami prezentowanymi w literaturze Osiągnięto lepszą dokładność.
(Przetwornik logarytmujący o dużej dokładności).

Keywords: Arithmetical circuits; Logarithmic Amplifier; Logarithmic converter.

Słowa kluczowe: wzmacniacz logarytmujący, układy arytmetyczne.

Introduction
Logarithmic functions are widely used in instrumentation
telecommunications, medical equipments, radar receivers
and arithmetical operation circuits [1-3]. Logarithmic circuits
need to have high input dynamic range to compress the
large amplitude of the signals in the radar receivers input,
high accuracy for arithmetical operation functions and low
power consumption in order to be useful in communication
circuits [1]. A square-law characteristic in strong inversion of
MOS transistors cannot lead to logarithmic function while
the bipolar transistors behavior can be used to generate it Fig.2. Parallel amplification topology
easily. On the other hand, good performance bipolar
transistors are not available in CMOS-based technologies By taking advantages of the above approaches
[4]. Moreover, utilizing MOS transistors in the weak combination, which are the subdivisions of parallel-
inversion region which has the exponential behavior will summation technique, [1] got better properties in
reduce the input dynamic range significantly. approximating logarithmic function piecewise. All reviewed
Several approaches of generating logarithmic functions approaches which are based on piecewise approximation,
for different applications have been proposed in the can be employed where high input dynamic range
literature which are discussed here. Fig. 1 shows the compression is needed but are not useful in basic arithmetic
progressive–compression structure which was used in [5], function circuits as they are complicated while suffer from
[6]. In this approach several auxiliary voltages are created poor accuracy.
using series of linear-limit amplifiers. A current proportional Motivated by the need for good accuracy, some other
to the voltage of each stage is generated by taking techniques like Taylor series [9],[10] and current conveyors
advantage of a transconductance element. The summation [11] were utilized to attain logarithmic and exponential
of all these currents with proper transconductance ratio can behaviors, but none of them could be realized with a simple
approximate the logarithmic function piecewise. With a little structure. However, utilizing a single MOS transistor with
systematic difference with the previous method, the parallel gate-to-substrate biasing technique in [2] can solve the
amplification type circuit was used in [7],[8]. Fig. 2 presents complicated circuit and accuracy problems simultaneously,
the system diagram of this approach. High symmetry in but a very poor input dynamic range of about 1.5uA makes
different path which is lead to the good phase and group it impractical.
delay matching is the strength of this method, while its input In this paper, a simple circuit based on intrinsic
dynamic range is lower than the previous on [1]. exponential characteristic of the bipolar devices is
proposed. At first a MOS transistor is used in order to
convert voltage to current and then logarithmic
characteristic is obtained by injecting the current to a bipolar
transistor. Simulation results in ADS software using TSMC
0.18um BiCMOS process models confirm the well
acceptable accuracy for arithmetic functions applications. In
section 2 the basis of logarithmic behaviors will be
considered and completed with the circuit design procedure
and the simulation results in section 3. Concluding remarks
are provided in section 4.

The basis of logarithmic behavior

Exponential function can be obtained via the relationship
Fig.1. Progressive-compression topology between emitter current and base-emitter voltage in a
bipolar transistor.

150 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 87 NR 4/2011

 topology has two issues discussed below. The first one is
  VBE  about the linear voltage to current converting which is not
(1) I E  I S  e Vt  1
  accessible in this case and can be obtained if the input
  voltage is equaled to (Vgs-VT). Furthermore in this
technology, the P-channel transistor characteristics are not
Therefore, logarithmic characteristics can be achieved as well as the N-channel. As the accurate square-law
by a little change in (1). behavior is needed for the accurate logarithmic function
according to mathematical equations, The NMOS transistor
I  is a better choice for the circuit input actually.
Vt
(2) VBE  ln  E  while IE IS The second issue is the low output dynamic range. Big
  IS  changes in the collector current value will cause low
alteration in the base-emitter voltage due to the exponential
(2) can be written as below, too. relationship. The lower output dynamic range requires
higher gain for the next stage to achieve logarithmic
converter. The problems are solved in the new topology
Vt Vt
(3) VBE  ln I E  ln I S  a ln I E  b which is depicted in Fig. 4. Another stage should be added
  for amplifying and level shifting. Fig. 5 shows the final
circuit.
So a linear relationship between VBE and ln(IE) is
available. Thus far logarithmic current to voltage converter
is available by a single bipolar transistor; however, voltage
to voltage converter is the final goal. In this case, a voltage
to current converter is also needed. This can be done by
means of a single MOS transistor. Because of the logarithm
function characteristics, a square-law behavior in strong
inversion region of the MOS elements cannot destroy
logarithmic relationship.

I D  k Vgs  VT 
2
(4)

Using (4) instead of IE in (3):

(5) VBE  a ln  k Vgs  VT    b  2a ln  k Vgs  VT    b

2 Fig.4. Repaired Logarithmic converter
 
 2a ln  k   2a ln V gs  VT   b  p ln Vgs  VT   q

Using proper dimensions (w/l) for MOS element may

cause the q to become zero while it can be made zero by
taking advantage of DC level shifting in the output stage,
too. In this section, it is demonstrated that logarithmic
converter can be realized using a MOS element for voltage
to current converting and a bipolar transistor for logarithmic
behaving.

Circuit design and simulation results

Circuit-level implementation of the proposed method is
presented here in Fig. 3.

Fig.5. Final Circuit for logarithmic converter

To enclose the operation of the proposed circuit it

should be expressed that the logarithm of all positive
numbers can be calculated using the logarithm of numbers
between 1 to e. (6) shows how all positive numbers can be
mapped in to the [1,e] zone.

(6) x  y.e k  ln( x)  ln( y )  k

If x is a real positive number and k is an integer, y will be
a real number between 1 and e. So logarithm of y is
sufficient to calculate the logarithm of x. For this reason the
Fig.3. Simple logarithmic converter input dynamic range of the proposed circuit is determined
between 1 and e. The equaled resistors are used to divide
Logarithmic behavior in the output voltage can be the input voltage by two, because the positive supply
achieved through feeding the current which is in proportion voltage of 1.3 volt is not enough to support the dynamic
to the input voltage, into a bipolar transistor. The simple range of [1,e]. Also, as the threshold voltage of the

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 87 NR 4/2011 151

transistors in the used technology is about 0.5 volt, the 1.0
minus supply voltage is fixed to -0.5 volt to recoup the input
voltage. It is manifestly shown in (7). 0.8

0.6
(7) Id  (vgs  vT )  I d  (v A  vEE  vT )

Volt
0.4
vss vT
  Id  vA  I d  vin
0.2

Fig. 6 shows the simulation results of proposed circuit -0.0

and an ideal logarithmic converter in 100MHz.
-0.2
1.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
Input (volt)
0.8
Fig.8. Proposed circuit output in two different frequencies
0.6
Volt

0.4 Moreover, Fig. 8 shows the Log error increases as the

frequency goes up. Thus, Fig. 9 is provided to report the
0.2 details.
-0.0
0
-0.2 ‐5
10 50 100 150 200 250 300 350 400

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

‐10
Input (volt) ‐15

‐20
Fig.6. Simulation result of proposed circuit and ideal logarithmic
converter in 100MHz ‐25

‐30
Time domain simulation is depicted in Fig. 7 to verify the
‐35
proper operation of the designed circuit.
‐40

3.0
Fig.9. Log error of proposed circuit
2.5
2.0 Very low Log error especially before 100MHz shows that
the presented approach is very promising for arithmetical
1.5
applications. Table 1 shows a comparison of this work with
Volt

1.0 some other logarithmic amplifiers.

0.5
Conclusion
0.0 In this paper, a novel voltage to voltage logarithmic
-0.5 converter for arithmetical circuits was proposed. The idea
was originated from the intrinsic characteristics of bipolar
0 20 40 60 80 100
transistors. Very low error in logarithm calculation which is
Time (nsec) so important for arithmetical circuits, show the strength of
Fig.7. Input and output of the proposed logarithmic converter the proposed. Additionally, a method of mapping the whole
positive real numbers in to the (1, e) zone was used to
The behavior of the proposed logarithmic converter over show that the large input dynamic range is not necessary.
different frequencies will be changed. It can have a different
rise and fall shape and of course it is not unexpected
because of the accumulated charges in the base of bipolar
devices and short channel effects in the MOS elements.
Fig. 8 demonstrates the output in 200MHz and 400MHz.

Table 1. This work and some other logarithmic amplifiers characteristics

[1] [9] [12] This work

Technology 35GHz Silicon Bipolar 0.25um CMOS 0.35um CMOS 0.18um BiCMOS
Technique Piecewise approximation Taylor series Taylor series Bipolar intrinsic Behavior
Supply voltage -5 V 1.5 V 1.5 V -0.5 v , 1.3 V
power 0.75 W 0.8 mW 0.8 mW 15.75 mW
Error @ low Freq 2 dB 0.5 dB 0.5 dB -36 dB
Applications Radar Input Stage Arithmetical circuit, AGC Arithmetical circuit, AGC Arithmetical circuit

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