Lecture-3 (8085 Microprocessor-Internal Architecture)
Lecture-3 (8085 Microprocessor-Internal Architecture)
Internal Architecture
Course Teacher:
Md. Obaidur Rahman, Ph.D.
Professor
Department of Computer Science and Engineering (CSE)
Dhaka University of Engineering & Technology (DUET), Gazipur.
Lecture Materials:
IBM PC Organization, CAP/IT221
Address bus
ALU Register
Section
Data bus
Arithmetic H L
and Logic Instruction
Stack Pointer
Unit decoder
Program Counter
Controller for
Address latch
Sign Flag: If the result of the latest arithmetic operation is having MSB
(most- significant byte) ‘1’ (meaning it is a negative number), then the sign
flag is set to ‘1’. Otherwise, it is reset to ‘0’ which means it is a positive
number.
Zero Flag: If the result of the latest operation is zero, then zero flag will be
set to ‘1’; otherwise it be reset to ‘0’.
Auxiliary Carry Flag: This flag is not accessible to programmer. This flag
will be used by the system during BCD (binary-coded decimal) operations.
Parity Flag: If the result of the latest operation is having even number of
‘1’s, then this flag will be set to ‘1’ Otherwise this will be reset to ‘0’. This
is used for error checking.
Carry Flag: If the result of the latest operations exceeds 8-bits then this flag
will be set to ‘1’. Otherwise it be reset to ‘0’.
9 CSE-4503: Microprocessors and Assembly Language
Islamic University of Technology (IUT)
Simple Assembly Program in 8085
MVI A, 32H Memory Contents Contents Operation
MVI B , 48H Address (Binary) (Hex)
ADD B 2000h 0011 1110 3E Load Reg.
Acc.
OUT 01H
2001h 0011 0010 32 Value is 32h
HLT
2002h 0000 0110 06 Load Reg. B
2003h 0100 1000 48 Value is 48h
Task:
2004h 1000 0000 80 Add B with
Derive the
A & Store in
flag values A
after the
2005h 1101 0011 D3 Display
ADD
instructions 2006h 0000 0001 01 Port Id 01h
2007h 0111 1100 76 End
Copy SP to B, Increment SP B C
12 F3