1) DESIGN FIR FILTER USING HDL AND IMPLEMENT

IT ON FPGA

AIM:

To design and implement a Finite Impulse Response (FIR)

filter using Hardware Description Language (HDL) and verify its functionality
on an FPGA.

TOOLS REQUIRED:

1. Hardware:
 FPGA Development Board (e.g., Xilinx, Intel
Altera)
 Oscilloscope (for output verification, if needed)
 JTAG Programmer

2. Software:

 HDL (VHDL/Verilog) Development Environment

(e.g., Xilinx Vivado, Intel Quartus, ModelSim)
 MATLAB (for filter coefficient generation)

THEORY:

DEFINITION:

The term FIR abbreviation is “Finite Impulse Response”

and it is one of two main types of digital filters used in DSP
applications. Filters are signal conditioners and function of each filter is, it
allows an AC components and blocks DC components. The best example of
the filter is a phone line, which acts as a filter. Because, it limits frequencies
to a rage significantly smaller than the range of human beings can hear
frequencies.
LOGICAL STRUCTURE OF FIR FILTER:

A FIR filter is used to implement almost any type of

digital frequency response. Usually these filters are designed with a
multiplier, adders and a series of delays to create the output of the filter. The
following figure shows the basic FIR filter diagram with N length. The result of
delays operates on input samples. The values of hk are the coefficients which
are used for multiplication. So that the o/p at a time and that is the
summation of all the delayed samples multiplied by the appropriate
coefficients.

PROCEDURE:

Step 1: Define FIR Filter Specifications

1. Choose the filter type: Low-pass, High-pass, Band-pass, or Band-

stop.
 2. Define the filter order (N) and cutoff frequency (Fc).

3. Select the windowing method (e.g., Hamming, Hanning,

Blackman).

Step 2: Generate FIR Filter Coefficients

1. Use MATLAB to calculate the FIR filter coefficients:

N = 7; % Filter order

Fc = 0.3; % Normalized cutoff frequency

h = fir1(N, Fc, 'low'); % Low-pass FIR filter

2. Store the coefficients for implementation in HDL.

Step 3: Write HDL Code (Verilog/VHDL)

1. Define inputs and outputs:

Clock (clk), Reset (rst), Input Signal (x), Output Signal (y).

2. Implement shift registers for delay elements.

3. Multiply input samples with filter coefficients and accumulate

results.

Step 4: Simulate the FIR Filter in HDL

1. Use Xilinx Simulator.

2. Apply test signals (e.g., sine wave, step input).

3. Verify that the output matches the expected filtered signal.

Step 5: Synthesize and Implement on FPGA

1. Open Xilinx and create a new project.

2. Add the FIR filter HDL code.

3. Synthesize the design and check for errors.

4. Generate the bitstream and program the FPGA.

Step 6: Test the FIR Filter on FPGA

1. Apply an input signal using a signal generator or an ADC interface.

2. Capture the output using an oscilloscope or DAC interface.

 3. Verify if the FIR filter is correctly filtering the signal.

PROGRAM:

Module fir_filter (

Input clk,

Input reset,

Input [15:0] x,

Output reg [31:0] y

);

Reg [15:0] h[0:2];

Reg [31:0] shift_reg[0:2];

Integer I;

Initial begin

h[0] = 16’d1;

h1] = 16’d2;

h[2] = 16’d3;

End

Always @(posedge clk or posedge reset) begin

If (reset) begin

Y <= 32’d0;

Shift_reg[0] <= 32’d30;

Shift_reg[1] <= 32’d20;

Shift_reg[2] <= 32’d10;

End else begin

 Shift_reg[2] <= shift_reg[1];

Shift_reg[1] <= shift_reg[0];

Shift_reg[0] <= x;

Y <= (h[0] * shift_reg[0] + h[1] * shift_reg[1] + h[2] * shift_reg[2]);

End

End

Endmodule

TESTBENCH CODE:

Module fir_filter_tb;

Reg clk;

Reg reset;

Reg [15:0] x;

Wire [31:0] y;

Fir_filter uut (

.clk(clk),

.reset(reset),

.x(x),

.y(y)

);

Initial begin

Clk = 0;

Forever #5 clk = ~clk;

 End

Initial begin

Reset = 1;

X = 16’d0;

#10;

Reset = 0;

#10;

X = 16’d10;

#10;

X = 16’d20;

#10;

X = 16’d30;

#10;

X = 16’d40;

#10;

X = 16’d50;

#10;

$finish;

End

Initial begin

$monitor(“At time %t, x = %d, y = %d”, $time, x, y);

$dumpfile(“fir_filter_tb.vcd”);

$dumpvars(1, fir_filter_tb);

End

Endmodule
RESULT:

The FIR filter was successfully designed using HDL and

implemented on an FPGA. The output was verified through simulation and
hardware testing.

2) DESIGN A DIGITAL-CLOCK USING HDL AND IMPLEMENT

IT ON FPGA

AIM:

To design a digital clock using Hardware Description

Language (HDL) and implement it on an FPGA for real-time display of hours,
minutes, and seconds.

TOOLS REQUIRED:

1. Hardware:
 FPGA Development Board (e.g., Xilinx, Intel Altera)
 Seven-Segment Display (if using hardware display)
 Clock Source (On-board or external)
 JTAG Programmer
2. Software:
 HDL Development Environment (e.g., Xilinx)

THEORY:

A "digital clock" in digital design refers to an

electronic circuit built using logic gates and other digital components to
display time digitally, typically using a seven-segment display, where the
time is represented by numerical digits rather than hands on a dial, and
relies on a stable "clock signal" to synchronize its internal operations and
accurately count time intervals; essentially, it's a circuit that counts seconds,
minutes, and hours using the consistent rhythm of the clock signal.
 A digital clock consists of counters to track hours,
minutes, and seconds based on a 1 Hz clock signal. The FPGA’s internal clock
runs at a much higher frequency (e.g., 50 MHz), so a frequency divider is
used to generate a 1 Hz clock. The clock counts seconds, minutes, and hours
using modulo counters:

 Seconds Counter: Counts from 0 to 59, then resets and increments the
minutes counter.
 Minutes Counter: Counts from 0 to 59, then resets and increments the
hours counter.
 Hours Counter: Counts from 0 to 23 (for 24-hour format) and then
resets.

F
igure 1: Digital Clock Block Diagram

PROCEDURE:

Step 1: Define the Clock Specifications

The FPGA’s internal clock operates at a high frequency (e.g., 50 MHz).

A frequency divider is required to generate a 1 Hz clock pulse for time

counting.

The clock should display hours, minutes, and seconds in a 24-hour

format.

Step 2: Design the Frequency Divider

Since the FPGA operates at 50 MHz, the clock must be divided down
to 1 Hz:

Formula:

Required Count = FPGA Clock / Desired Clock

Count = 50,000,000 / 1 = 50,000,000 cycles

 A counter is implemented to generate a 1 Hz clock pulse.

Step 3: Implement Time Counters

Seconds Counter: Counts from 0 to 59, resets to 0, and increments the

minutes counter.

Minutes Counter: Counts from 0 to 59, resets to 0, and increments the

hours counter.

Hours Counter: Counts from 0 to 23 (for a 24-hour format) and resets

to 0.

The minutes and hours counters follow a similar logic, with cascading
carry signals.

Step 4: Combine the Modules

Instantiate clock_divider, seconds_counter, minutes_counter, and

hours_counter.

Connect the carry signals properly to increment each time unit.

Step 5: Simulation in Xilinx.

1. Write a testbench to apply clock and reset signals.

2. Observe seconds, minutes, and hours incrementing correctly.

3. Verify carry signals propagate properly.

Step 6: FPGA Implementation

1. Synthesize the design in Xilinx.

2. Generate the bitstream file.

3. Program the FPGA using a JTAG programmer.

4. If using a seven-segment display, map the sec, min, and hour

outputs to a BCD to Seven-Segment Decoder.

Step 7: Testing on FPGA

1. Observe the time increments every second.

2. Reset the clock and check if it starts from 00:00:00.

3. Verify that hours roll over correctly after 23:59:59.

PROGRAM:

Module digital_clock(

Input wire clk,

Input wire reset,

Output reg [5:0] sec,

Output reg [5:0] min,

Output reg [4:0] hour

);

Reg [31:0] count;

Reg tick;

Always @(posedge clk or posedge reset) begin

If (reset) begin

Count <= 0;

Tick <= 0;

End else begin

If (count == 50000000) begin

Tick <= 1;

Count <= 0;

End else begin

Tick <= 0;

Count <= count + 1;

End

End

End
 Always @(posedge tick or posedge reset) begin

If (reset) begin

Sec <= 0;

Min <= 0;

Hour <= 0;

End else begin

If (sec == 59) begin

Sec <= 0;

If (min == 59) begin

Min <= 0;

If (hour == 23) begin

Hour <= 0;

End else begin

Hour <= hour + 1;

End

End else begin

Min <= min + 1;

End

End else begin

Sec <= sec + 1;

End

End

End

Endmodule

TESTBENCH CODE:

Module digital_clock_tb;
 Reg clk_tb;
Reg reset_tb;
Wire [5:0] sec_tb;
Wire [5:0] min_tb;
Wire [4:0] hour_tb;

Digital_clock uut (
.clk(clk_tb),
.reset(reset_tb),
.sec(sec_tb),
.min(min_tb),
.hour(hour_tb)
);

Always begin
#10 clk_tb = ~clk_tb;
End

Initial begin
Clk_tb = 0;
Reset_tb = 0;

Reset_tb = 1;
#20 reset_tb = 0;

$monitor(“Time: %2d:%2d:%2d”, hour_tb, min_tb, sec_tb);

$dumpfile(“digital_clock_tb.vcd”);
$dumpvars(1, digital_clock_tb);

#1000;
$finish;
End
Endmodule
RESULT:

The digital clock was successfully designed using HDL and

implemented on FPGA, displaying real-time hours, minutes, and
seconds correctly.

3) DESIGN A FSM BASED VENDING MACHINE AND

IMPLEMENT IT ON FPGA

AIM:

To design and implement a Finite State Machine (FSM) based

vending machine using Hardware Description Language (HDL) and deploy it
on an FPGA platform.

APPARATUS REQUIRED:

1. Hardware:
 FPGA Development Board (e.g., Xilinx, Intel Altera)
 Push Buttons (for coin inputs)
 Seven-Segment Display or LED Indicators (for output
display)
 JTAG Programmer

2. Software:

 HDL Development Environment (Xilinx)

 Simulation Tool (ModelSim, ISim)

THEORY:

A Finite State Machine (FSM) is a computational model used to

design digital systems. It consists of a set of states, inputs, outputs, and
transitions between states. The FSM is commonly used in sequential circuit
design to control the flow of operations based on input sequences.

In the vending machine example, the system’s states represent

the different stages of the vending machine, such as "Idle," "Coin Inserted,"
"Item Selected," and "Change Given." The system transitions between these
states based on inputs (coin values, item selection) and outputs (item
dispense, change give-back).

The system must:

1. Accept coins of various denominations.

2. Dispense an item based on the amount inserted.

3. Provide change if needed.

4. Reset after an item is dispensed or when the transaction is canceled.

FSM Design:

The design involves the following states:

1. Idle: No coins inserted; waiting for user input.

2. Coin Inserted: Coin has been inserted.

3. Item Selected: A valid item is selected after enough money is

inserted.

4. Dispense Item: The item is dispensed, and change is returned.

5. Change Given: The change is given back to the user.

Inputs:

 Coin input: Simulated with switches (representing different coin

denominations).

 Item selection: Buttons to select different items.

Outputs:

 7-Segment display: Shows the current amount inserted.

 LEDs: Indicate the machine's state (idle, item dispensed, etc.).

 Fig 1: VMC Block Diagram

PROCEDURE:

Step 1: Define the FSM and System Requirements

A Finite State Machine (FSM) is used to control the vending machine.

The vending machine accepts 5¢ and 10¢ coins and dispenses a

product when 20¢ is inserted.

The FSM should handle state transitions based on the coin input.

Step 2: Write the HDL Code for the FSM

Step 3: Simulate the FSM in Xilinx.

1. Write a Testbench:

Apply clock and reset signals.

Insert coins (5¢ and 10¢) in different orders.

Check state transitions and dispense output.

2. Run the Simulation:

Verify if the machine dispenses after 20 cents.

 Confirm correct FSM behavior.

Step 4: Implement on FPGA

1. Synthesize the Verilog Code using Xilinx.

2. Assign FPGA Pins:

 coin_5 → Push Button 1

 coin_10 → Push Button 2
 dispense → LED Output

3. Generate a Bitstream and Program the FPGA.

Step 5: Hardware Testing on FPGA

1. Press Button 1 (5¢) and Button 2 (10¢) and observe LED output.

2. Check if the LED lights up when 20 cents are reached.

3. Reset the system and verify correct FSM behavior.

PROGRAM:

Module vending_machine (

Input clk,

Input reset,

Input [1:0] product_select,

Input [3:0] money_in,

Output reg product_dispensed,

Output reg [1:0] dispensed_product,

Output reg error

);

Typedef enum reg [2:0] {

IDLE = 3’b000,

SELECT_PRODUCT = 3’b001,
 INSERT_MONEY = 3’b010,

DISPENSE = 3’b011,

ERROR = 3’b100

} state_t;

State_t current_state, next_state;

Parameter PRICE_PRODUCT_1 = 4’d5;

Parameter PRICE_PRODUCT_2 = 4’d7;

Parameter PRICE_PRODUCT_3 = 4’d9;

Always @(posedge clk or posedge reset) begin

If (reset) begin

Current_state <= IDLE;

End else begin

Current_state <= next_state;

End

End

Always @(*) begin

Case (current_state)

IDLE: begin

Product_dispensed = 0;

Dispensed_product = 2’b00;

Error = 0;

If (product_select != 2’b00)

Next_state = SELECT_PRODUCT;
 Else

Next_state = IDLE;

End

SELECT_PRODUCT: begin

Error = 0;

If (product_select == 2’b00)

Next_state = ERROR;

Else

Next_state = INSERT_MONEY;

End

INSERT_MONEY: begin

If ((product_select == 2’b01 && money_in >= PRICE_PRODUCT_1)

||

(product_select == 2’b10 && money_in >= PRICE_PRODUCT_2)

||

(product_select == 2’b11 && money_in >= PRICE_PRODUCT_3))

begin

Next_state = DISPENSE;

End else begin

Next_state = INSERT_MONEY;

End

End

DISPENSE: begin

Product_dispensed = 1;

Dispensed_product = product_select;
 Next_state = IDLE;

End

ERROR: begin

Error = 1;

Next_state = IDLE;

End

Default: next_state = IDLE;

Endcase

End

Endmodule

TESTBENCH CODE:

Module tb_vending_machine;

Reg clk;

Reg reset;

Reg [1:0] product_select;

Reg [3:0] money_in;

Wire product_dispensed;

Wire [1:0] dispensed_product;

Wire error;

Vending_machine uut (

.clk(clk),

.reset(reset),
 .product_select(product_select),

.money_in(money_in),

.product_dispensed(product_dispensed),

.dispensed_product(dispensed_product),

.error(error)

);

Always begin

#5 clk = ~clk;

End

Initial begin

Clk = 0;

Reset = 0;

Product_select = 2’b00;

Money_in = 4’b0000;

Reset = 1;

#10 reset = 0;

Product_select = 2’b01;

Money_in = 4’d5;

#10;

Product_select = 2’b10;

Money_in = 4’d3;

#10;
 Product_select = 2’b11;

Money_in = 4’d9;

#10;

Product_select = 2’b00;

Money_in = 4’d5;

#10;

$finish;

End

Initial begin

$dumpfile(“dump.vcd”);

$dumpvars(1);

End

Endmodule
RESULT:

The FSM-based vending machine was successfully designed,

simulated, and implemented on FPGA, demonstrating correct coin input
handling and product dispensing behavior.

4) DESIGN A TIC TAC TOE GAME USING HDL AND

IMPLEMENT IT ON FPGA

AIM:

To design and implement a Tic-Tac-Toe game using

Hardware Description Language (HDL) and deploy it on an FPGA to allow two
players to play interactively.

TOOLS REQUIRED:

1. Hardware:
 FPGA Development Board (Xilinx, Intel Altera)
 Push buttons (for player input)
 LEDs/Seven-Segment Display (to show the game state)
 VGA Display (optional) for graphical interface
 JTAG Programmer
2. Software:
 HDL Development Environment (Xilinx Vivado, Intel
Quartus)
 Simulation Tool (ModelSim, ISim)

THEORY:
Tic-Tac-Toe Overview:

Tic-Tac-Toe is a two-player game played on a 3×3 grid.

Players alternate turns, marking ‘X’ or ‘O’ in an empty grid cell. The player
who first gets three marks in a row (horizontally, vertically, or diagonally)
wins the game.

FSM Design for Tic-Tac-Toe:

The game is controlled using a Finite State Machine (FSM).

The FSM handles player moves, checks for a win, and resets
the board.

FSM States:

1. Idle (S0) - Waiting for player input.

2. Player X Move (S1) - Accepts move from Player X.

3. Player O Move (S2) - Accepts move from Player O.

4. Check Win (S3) - Verifies if any player has won.

5. Game Over (S4) - Declares winner or draw.

6. Reset (S5) - Resets the board for a new game.

 Fig 1: Tic-Tac-Toe Block Diagram

PROCEDURE:

Step 1: Define the Game Logic

The game consists of a 3×3 grid where two players take turns
placing X (Player 1) or O (Player 2).

The system should track moves, check for a win, and handle
draws.
 The design will use a Finite State Machine (FSM) to control the
game flow.

FSM States:

1. Idle (S0) – Waiting for the first move.

2. Player X Move (S1) – Accepts input from Player X.

3. Player O Move (S2) – Accepts input from Player O.

4. Check Win (S3) – Verifies if any player has won.

5. Game Over (S4) – Declares winner or draw.

6. Reset (S5) – Resets the game for a new round.

Step 2: Write HDL Code (Verilog)

1. Create a 3×3 grid using a 9-bit register array.

2. Design state transitions based on player input and win conditions.

3. Implement logic to detect winning conditions (rows, columns,

diagonals).

Step 3: Simulate the Design in ModelSim/Vivado

1. Write a testbench to apply clock, reset, and player moves.

2. Verify correct player turns and move registration.

3. Check if the game detects a win or draw correctly.

Step 4: Implement on FPGA

1. Synthesize the Verilog code using Xilinx.

2. Assign FPGA pins:

Push Buttons: Select grid positions.

Switches: Select Player X or O.

LEDs/Seven-Segment Display: Show board state.

VGA Display (optional): Display graphical board.

3. Generate Bitstream and Program the FPGA.

Step 5: Hardware Testing

 1. Players take turns pressing buttons to select positions.

2. Check LED/VGA display updates correctly.

3. Confirm win or draw detection works.

4. Press Reset to restart the game.

PROGRAM:

Module tic_tac_toe(

Input clk,

Input rst_n,

Input [1:0] player,

Input [3:0] row,

Input [3:0] col,

Input make_move,

Output reg [8:0] board,

Output reg game_over,

Output reg [1:0] winner

);

Parameter PLAYER_1 = 2’b01;

Parameter PLAYER_2 = 2’b10;

Reg [8:0] board_next;

Reg [1:0] current_player;

Always @(posedge clk or negedge rst_n) begin

If (!rst_n) begin

Board <= 9’b0;

 Game_over <= 0;

Winner <= 2’b00;

Current_player <= PLAYER_1;

End else if (make_move && !game_over) begin

If (board[(row*3) + col] == 0) begin

Board_next = board | (current_player << ((row*3) + col));

Board <= board_next;

If (check_win(board_next)) begin

Game_over <= 1;

Winner <= current_player;

End else begin

Current_player <= (current_player == PLAYER_1) ? PLAYER_2 :

PLAYER_1;

End

End

End

End

Function check_win;

Input [8:0] b;

Begin

Check_win = (b[0] && b[1] && b[2]) || (b[3] && b[4] && b[5]) || (b[6]
&& b[7] && b[8]);

Check_win = check_win || (b[0] && b[3] && b[6]) || (b[1] && b[4] &&
b[7]) || (b[2] && b[5] && b[8]);

Check_win = check_win || (b[0] && b[4] && b[8]) || (b[2] && b[4] &&
b[6]);
 End

Endfunction

Endmodule

TESTBENCH CODE:

Module tb_tic_tac_toe;

Reg clk;

Reg rst_n;

Reg [1:0] player;

Reg [3:0] row, col;

Reg make_move;

Wire [8:0] board;

Wire game_over;

Wire [1:0] winner;

Tic_tac_toe uut (

.clk(clk),

.rst_n(rst_n),

.player(player),

.row(row),

.col(col),

.make_move(make_move),

.board(board),

.game_over(game_over),
 .winner(winner)

);

Always begin

#5 clk = ~clk;

End

Initial begin

Clk = 0;

Rst_n = 0;

Player = 2’b01;

Row = 0;

Col = 0;

Make_move = 0;

#10 rst_n = 1;

#10 row = 0; col = 0; make_move = 1;

#10 make_move = 0;

#10 player = 2’b10; row = 0; col = 1; make_move = 1;

#10 make_move = 0;

#10 player = 2’b01; row = 1; col = 0; make_move = 1;

#10 make_move = 0;

#10 player = 2’b10; row = 1; col = 1; make_move = 1;

 #10 make_move = 0;

#10 player = 2’b01; row = 2; col = 0; make_move = 1;

#10 make_move = 0;

#20 $finish;

End

Initial begin

$monitor(“Time: %0t | Player: %b | Row: %d | Col: %d | Board: %b |

Game Over: %b | Winner: %b”,

$time, player, row, col, board, game_over, winner);

$dumpfile(“tic_tac_toe.vcd”);

$dumpvars(1, tb_tic_tac_toe);

End

Endmodule
RESULT:

The Tic-Tac-Toe game was successfully designed, simulated,

and implemented on FPGA, allowing two players to interactively play, with
correct move registration, win detection, and game reset functionality.

5) WRITE A PROGRAM IN HDL TO READ IMAGE

AND TO IMPLEMENT PROCESSING ALGORITHM

AIM:

To write a program in HDL (Hardware Description Language) to

read an image and implement an image processing algorithm.

TOOLS REQUIRED:
 1. Computer with HDL development environment (such as Xilinx
Vivado, Quartus Prime, or ModelSim)

2. Verilog or VHDL compiler and simulator

3. Image processing software (MATLAB, Python with OpenCV) for

preprocessing

4. FPGA board (optional for hardware implementation)

5. Memory module (such as BRAM in FPGA) to store the image

6. Testbench for simulation

THEORY:

Image processing using HDL involves reading pixel data from

an image file, processing it, and outputting the modified image. This is
typically done using:

1. Image Representation:
 Images are stored as pixel arrays, where each pixel
contains color/intensity values.
 Grayscale images use 8-bit intensity values, while RGB
images use 24-bit values (8 bits per channel).
2. Image Storage in HDL:
 Images are stored in memory modules like BRAM in
FPGAs or external RAM.The HDL code reads pixel values
from memory, processes them, and writes them back.
3. Common Image Processing Algorithms:
 Edge Detection: Uses Sobel or Prewitt filters to detect
edges.
 Image Thresholding: Converts an image to black and
white based on intensity values.
 Image Smoothing: Uses a moving average or Gaussian
filter to reduce noise.
 Contrast Enhancement: Modifies pixel intensity to
improve visibility.
4. HDL Implementation:
 HDL cannot directly read image files like Python or
MATLAB. Instead, the image is converted into pixel
 values and stored in memory (using an initialization file
or a memory block).
 HDL processes the pixels sequentially and produces the
output in a similar format.

Fig 1: Image Processing

PROCEDURE:

1. Convert Image to Pixel Data:

Use Python (OpenCV) or MATLAB to convert an image into a

text file or binary format containing pixel values.

2. Store Pixel Data in Memory:

Use memory initialization files (.mif or .coe) to store pixel

values in HDL-compatible RAM.

3. Write HDL Code:

Implement a module to read pixel values from memory.

Apply the chosen image processing algorithm (e.g., edge

detection, filtering).
 Write the processed pixel values back to memory.

4. Testbench Simulation:

Create a testbench in Verilog/VHDL to verify the processing.

Load the input pixel values and observe the output.

5. Hardware Implementation (Optional):

Synthesize the HDL code and implement it on an FPGA.

Use VGA/HDMI interface for displaying the processed image.

6. Convert Processed Data Back to Image:

Export the processed pixel values from HDL simulation.

Convert them back into an image using Python or MATLAB.

PROGRAM:

Module image_processing #(

Parameter WIDTH = 640,

Parameter HEIGHT = 480

)(

Input clk,

Input rst_n,

Input [23:0] pixel_in,

Input valid_in,

Output reg [23:0] pixel_out,

Output reg valid_out

);

Always @(posedge clk or negedge rst_n) begin

If (~rst_n) begin

Pixel_out <= 24’b0;

 Valid_out <= 0;

End else if (valid_in) begin

Pixel_out <= ((pixel_in[23:16] + pixel_in[15:8] + pixel_in[7:0]) / 3) |

((pixel_in[23:16] + pixel_in[15:8] + pixel_in[7:0]) / 3) << 8 |

((pixel_in[23:16] + pixel_in[15:8] + pixel_in[7:0]) / 3) << 16;

Valid_out <= 1;

End else begin

Valid_out <= 0;

End

End

Endmodule

TESTBENCH CODE:

Module tb_image_processing;

Localparam WIDTH = 640;

Localparam HEIGHT = 480;

Reg clk;

Reg rst_n;

Reg [23:0] pixel_in;

Reg valid_in;

Wire [23:0] pixel_out;

Wire valid_out;

Image_processing uut (
 .clk(clk),

.rst_n(rst_n),

.pixel_in(pixel_in),

.valid_in(valid_in),

.pixel_out(pixel_out),

.valid_out(valid_out)

);

Always begin

#5 clk = ~clk;

End

Task reset;

Begin

Rst_n = 0;

#10 rst_n = 1;

End

Endtask

Task test_image;

Integer I;

Begin

For (I = 0; I < 4; I = I + 1) begin

Pixel_in = (I == 0) ? 24’hFF0000 :

(I == 1) ? 24’h00FF00 :

(I == 2) ? 24’h0000FF :

24’hFFFFFF;
 Valid_in = 1;

#10 valid_in = 0;

#10;

End

End

Endtask

Initial begin

Clk = 0;

Rst_n = 0;

Pixel_in = 0;

Valid_in = 0;

Reset;

Test_image;

$dumpfile(“image_processing.vcd”);

$dumpvars(1, tb_image_processing);

#100 $finish;

End

Endmodule
RESULT:

The HDL code successfully reads an image, applies the

selected image processing algorithm, and outputs the processed image data.
The correctness of the algorithm is verified through simulation or FPGA
implementation.

6) DESIGN A SIMPLE BURGLAR ALARM USING HDL THAT

ACTIVATES A SIREN IF EITHER A MOTION SENSOR
DETECTS MOTION OR A SENSOR ON WINDOW DETECTS
THAT THE WINDOW IS OPEN.

AIM:

To design and implement a simple burglar alarm system using

HDL that activates a siren when motion is detected or a window is opened.

TOOLS REQUIRED:
 1. HDL Development Environment (Xilinx Vivado, Quartus Prime,
ModelSim, etc.)
2. Verilog or VHDL Compiler and Simulator
3. FPGA Board (Optional for hardware implementation)
4. Motion Sensor (PIR Sensor)
5. Window Sensor (Magnetic Reed Switch)
6. Siren or LED Indicator for Alarm

THEORY:

A burglar alarm, also called an intruder alarm or security

alarm, is an electronic system designed to detect and alert of an
unauthorized entry or intrusion. Sensors monitor doors, windows, motion,
glass breakage or other activity and notify users by sounding loud sirens or
bells.

For a security system to qualify as a burglar alarm, it needs

to include sensors on entry points and interior areas, audible alarms like
sirens sufficient to frighten away intruders and the ability to trigger calls or
dispatches to authorities.

A burglar alarm system typically consists of sensors

detecting unauthorized access and triggering an alarm. In this design:

 A motion sensor (PIR sensor) detects movement in a

secured area.
 A window sensor (reed switch) detects if a window is
open.
 If either sensor is activated, the alarm (siren) is turned
ON.
 If both sensors are inactive, the alarm remains OFF.
 This is implemented using a simple OR gate logic, where
the alarm is triggered when either input is HIGH (logic
1).
 Fig 1: Simple Burglar Alarm

PROCEDURE:

1. Write the Verilog Code: Implement the logic using an OR gate

to activate the alarm.

2. Create the Testbench: Simulate different input scenarios to

verify the design.

3. Simulate in an HDL Simulator: Use ModelSim or Vivado to verify

output correctness.

4. Synthesize for FPGA Implementation (Optional): Upload the

design to an FPGA and connect real sensors.

5. Test the System with Real Sensors:

Connect a PIR sensor and a window sensor to FPGA

input pins.

Connect a buzzer or LED to the siren output.

 Verify that the alarm activates correctly based on
sensor inputs.

PROGRAM:

Module burglar_alarm (

Input wire clk,

Input wire reset,

Input wire motion_detected,

Output reg alarm_triggered

);

Typedef enum reg [1:0] {

IDLE = 2’b00,

MOTION = 2’b01,

ALARM = 2’b10

} state_t;

State_t state, next_state;

Always @(posedge clk or posedge reset) begin

If (reset) begin

State <= IDLE;

End else begin

State <= next_state;

End

End
Always @(*) begin

Case(state)

IDLE: begin

If (motion_detected)

Next_state = MOTION;

Else

Next_state = IDLE;

End

MOTION: begin

Next_state = ALARM;

End

ALARM: begin

Next_state = ALARM;

End

Default: next_state = IDLE;

Endcase

End

Always @(posedge clk or posedge reset) begin

If (reset) begin

Alarm_triggered <= 0;

End else begin

If (state == ALARM)

Alarm_triggered <= 1;

Else

Alarm_triggered <= 0;

End
End

Endmodule

TESTBENCH CODE:

Module tb_burglar_alarm;

Reg clk;

Reg reset;

Reg motion_detected;

Wire alarm_triggered;

Burglar_alarm uut (

.clk(clk),

.reset(reset),

.motion_detected(motion_detected),

.alarm_triggered(alarm_triggered)

);

Always #5 clk = ~clk;

Initial begin

Clk = 0;

Reset = 0;

Motion_detected = 0;
 $monitor(“Time: %0t | Reset: %b | Motion: %b | Alarm: %b”, $time,
reset, motion_detected, alarm_triggered);

Reset = 1;

#10;

Reset = 0;

Motion_detected = 0;

#20;

Motion_detected = 1;

#10;

Motion_detected = 0;

#30;

Reset = 1;

#10;

Reset = 0;

$finish;

End

Initial begin

$dumpfile(“burglar_alarm.vcd”);

$dumpvars(1, tb_burglar_alarm);

End
Endmodule

RESULT:

The burglar alarm system is successfully designed and

simulated. The siren activates when either the motion sensor detects
movement or the window sensor detects that the window is open.