ADC Research Paper - Final - Draft
ADC Research Paper - Final - Draft
*Note: Sub-titles are not captured in Xplore and should not be used
I. INTRODUCTION B. Channel
In this research, we explore the modeling of • AWGN Channel with Frequency Offset and
practical parameters that affect signal processing in Variable Time Delay - Applies the frequency offset,
everyday life, such as static frequency offset, timing drift, a timing drift, and additive white Gaussian noise to
and Gaussian noise (as discussed in our lectures). Starting the signal
from a foundational example model that processes at
complex baseband, we present a practical digital receiver C. Receiver
design incorporating correlation-based coarse frequency • Raised Cosine Receive Filter - Uses a roll off
compensation, PLL-based fine frequency compensation, factor of 0.5
PLL-based symbol timing recovery, frame synchronization, • Coarse Frequency Compensation - Estimates an
and phase ambiguity resolution. Utilizing various approximate frequency offset of the received signal
synchronization algorithms from the Communications and corrects it
Toolbox™, this study aims to address these common • Symbol Synchronizer - Resamples the input signal
impairments, enhancing the reliability and performance of according to a recovered timing strobe so that
digital communication systems. symbol decisions are made at the optimum
sampling instants
II. MOTIVATION
• Carrier Synchronizer - Compensates for the
In the field of digital communications, challenges residual frequency offset and the phase offset
such as frequency shifts, timing errors, and Additive White • Frame Synchronizer - Aligns the frame boundaries
Gaussian Noise (AWGN) often reduce system performance, at the known frame header
particularly in wireless environments. Addressing these • Data Decoding - Resolves the phase ambiguity
issues is vital for ensuring reliable data transmission. The caused by the Carrier Synchronizer, demodulates
motivation behind this research evolves from the need to the signal, and decodes the text message
develop robust communication systems that can maintain
high-quality signal reception, despite above mentioned V. BLOCKS
factors. By modeling and simulating a QPSK-based system
with practical compensation techniques, this study aims to A. Carrier Synchronization
enhance the performance of digital receivers. After symbol synchronization, we expect our signal to
have a consistent amplitude due to AGC(Automatic Gain
III. EASE OF USE Control)-block. And frequency corrected due to Coarse
Frequency Compensation. And reduced inter-symbol
A. Abbreviations & Acronyms interference with the help of symbol synchronization.
[Add list of abbreviations to prevent extra words helping
in page limit] The next block we pass our signal through is Carrier
Synchronizer.
• CFO - Coarse Frequency Compensator
This block has the following parameters:
• FFT – Fast Fourier Transform
• BER – Bit Error Rate • Modulation type: This is required to demodulate the
incoming signal by following the modulation
B. Values Simplification
scheme. In our case QPSK(Quadrature Phase Shift
Values like 1.002e-5 simply means 1.002*10^(-5) Keying) is used and so we’ve selected the specific
demodulation scheme to demodulate the signal.
IV. STRUCTURE OF SIMULINK DIAGRAM:
• Modulation offset: This is the phase offset that
A. Transmitter occurs due to type of modulation that is used and
several other natural reasons (for e.g. Doppler’s
• Bit Generation - Generates the bits for each frame
Effect). Removing this offset is the reason why we
• QPSK Modulator - Modulates the bits into QPSK are using a carrier synchronizer. We may also use a
symbols PLL (will be discussing it after a few parameters). To
• Raised Cosine Transmit Filter - Uses a roll off remove this phase offset the system we are currently
factor of 0.5, and up samples the QPSK symbols by working on has set it to ‘auto’. We can use the
two constellation diagram to analyze the phase offset.
Then we calculate the offset by checking the
difference between measured offset and ideal offset