See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/254239001

An emulated computer with assembler for teaching undergraduate computer

architecture

Article · June 2005

DOI: 10.1145/1275604.1275615

CITATIONS READS
14 421

2 authors, including:

Timothy D. Stanley
Utah Valley University
25 PUBLICATIONS 207 CITATIONS

SEE PROFILE

All content following this page was uploaded by Timothy D. Stanley on 05 March 2015.

The user has requested enhancement of the downloaded file.

 An Emulated Computer with Assembler for
Teaching Undergraduate Computer Architecture

Timothy Daryl Stanley, PhD Mu Wang

Brigham Young University Hawaii, #1854 Brigham Young University Hawaii, #1854
55-220 Kulanui Street 55-220 Kulanui Street
Laie, Hawaii 96762-1294 Laie, Hawaii 96762-1294
(808) 293-3388
[email protected] [email protected]

Abstract This paper provides details of this computer design,

An eight-bit computer has been designed using an open assembler and example programs as well as descriptions of
source logic emulation package called “Multimedia Logic” designs submitted by students.
from www.softronix.com. The intent of the project was to
make clear to computer science students how the data path Categories and Subject Descriptors
and control lines work to provide computer functionality. B.6 Hardware / Logic Design / Simulation.
This computer is an excellent teaching aid because: C.1.1 Computer Systems Organization / Computer
Architectures
1. All registers, ALU outputs, control lines, and
memory outputs are instrumented.
General Terms
2. Instructions can be executed with a single step Design, Human Factors, Theory
switch or run with a clock.
3. The architecture is quite simple, with separate Keywords
memory devices for data and instructions. Logic Simulation, Computer Design, Binary Visualization,
Multimedia Logic
4. It is supported with an assembler patterned after
the MIPS assembler used with the SPIM
simulator. 1. Introduction
5. An ASCII output display is available. The concepts of computer architecture are some times very
difficult for beginning computer science students to
The instruction set designed for this computer includes: visualize because the action is all happening at the electron
Add from memory, Add immediate, Load from memory to level in microscopic circuits. By building on knowledge
the input register, save from the output register to memory, from other courses students may be able to visualize what
jump to the address given by the immediate, jump to the is happening in circuits, but many layers of abstraction are
address given by the immediate if the last add produced a involved. For example, if one builds a computer with TTL
zero result, and halt. circuits, there is a level of abstraction in the relation ship
The design includes an instruction format of three bits of between circuit pin outs and logic elements. There is also a
operation code followed by five bits of immediate. complex chain of detail between circuits that is visible only
with logic probes or additional expensive instrumentations.
Using this design as a launching point, students have been Also when a student has spent the time to understand and
encouraged to design their own computers. Some master the breadboard circuit the semester is over, the
excellent designs have been submitted. These include an circuit is disassembled and used for the next class.
elaborate multi-cycle 16-bit design, and many application
specific designs. The emulated logic approach the authors have developed
overcomes these limitations in understanding the details of
computer architecture. The circuits are designed by
“wiring” up logic elements with all data inputs coming in
on the left, control signals coming in from the bottom, and
outputs exiting from the right. The high level devices like This is a nice project to start with as it builds on the ALU
memory circuits and ALU’s look like the devices in device example that is provided with Multimedia Logic.
schematic diagrams, making these devices easier to
The learning outcomes of this project are: familiarity with
visualize. By designing simple circuits the operation of the
the ALU, comparing hexadecimal and binary, exploring
individual components can be understood. At the
properties of binary numbers under operations like the 5-6
completion of the class the students can take the design
operation shown in figure 1 to see the two’s complement
with them.
binary notation of a negative one.
While the focus of this paper is an emulated computer for
teaching architecture, a series of introductory circuits used 2.2 Scanned Memory to Output Display
to develop an understanding of the components that make
up a digital computer are also provided. Many of the
concepts of digital logic are difficult to grasp without
practical experience. Some use prototyping boards with
small scale digital circuits to design and build examples of
digital devices [1]. Others use a hardware design language,
like Verilog, to illustrate and teach digital logic concepts
[5]. One school even uses students actors to emulate
instruction flow in a computer [6].
Figure 2. Scanned Memory to Output Display
The 8-bit computer will be thoroughly documented starting
in section three. This project, shown figure 2, connects the output of a
memory device to an ANSII display device. Then by
2. Component Learning Projects and sequentially scanning the memory addresses with a counter
Outcomes connected to a clock, the content of the memory is sent to
A number of projects built and demonstrated by students the display. In this case the content of the memory is “
will be given in this section. We will start with simple HELLO WORLD! ”. For this project, only the first sixteen
projects and advance to more complex designs. Each locations in memory are used, however, with an 8-bit
design will be demonstrated with the presentation of this counter, 256 locations could be used.
paper at the conference. In Multimedia Logic the memory contents can be read from
a “text” file or written to during the simulation. In this case
2.1 Calculator with Binary and Hexadecimal the memory contents are loaded from a file and the
Outputs memory is treated as a read-only memory (ROM).
Learning outcomes from this project are: an understanding
of the relationship between memory address lines and data
output lines, understanding counters, and clock oscillators,
and synchronous data transfer from memory to display.

2.3 Programmable Calculator

Figure 1. Calculator with Binary and

Hexadecimal Outputs
The first project, illustrated in fig 1, is a calculator that
takes two four-bit inputs, from hexadecimal keypads, and
provides an output in both binary and hexadecimal, based
on a function selected. The function is selected with the
selector switch. The functions available in the ALU are: Figure 3. Programmable Calculator
addition, subtraction, multiplication, division, equal, less
than, shift right and shift left. This project, shown in figure 3, is a combination of the first
two, using scanned memory to provide functions and data
to an ALU. This project begins the comparison to a real
computer, with the upper memory serving as data memory, 2.5 Four-Bit ALU
the lower memory which provides functions to the ALU as This project, shown in figure 5, illustrates the complexity
a program memory, and the counter as a program counter. in the design of an ALU. This ALU, designed after the
The learning outcomes of this design are observation of the one-bit ALU from Patterson (Figure 6), can And, Or, Add,
different things that a series of binary lines can be, from and Subtract. It is very useful for illustrating the bitwise
instructions to data to addresses, to clock pulses. This is operations of And and Or. For example the output
where we also learn about data paths and control paths. illustrated above is the bit wise And of 3 and 5.
Binvert Operation
CarryIn
2.4 Four-Bit Adder
a
0

1
Result

b 0 2

CarryOut

Figure 4. Four-bit Adder Figure 6. One-bit ALU from Patterson [4]

These next two projects are designed to understand the Learning outcomes of this project include an appreciation
inner workings of an ALU. The first, shown in figure 4, is of how multiplexers make possible the control path in a
a ripple carry binary adder. Two four-bit values are computer—and again, an appreciation of how gates can be
provided on the hexadecimal key pads and the results of combined to produce computer functions.
the addition are displayed on the seven segment displays.
By inverting the B inputs and making the C input for the 3. An Emulated Computer for Teaching
first stage one the adder can be converted to a subtraction Computer Architecture
unit, illustrating the algorithm for converting a binary
number to its two’s complement negative. Providing a computer that is very well instrumented,
visible on one page and easy to demonstrate, was the main
goal of this design effort. In my computer architecture
classes I ask my students to design an emulated computer.
This design was one I produced to illustrate what I wanted
from my students. I suggested they start with an
instruction set and register design and build a computer
from this foundation. For this eight-bit computer, an
instruction format of three bits of operation code and five
bits of immediate was chosen. This instruction format
provides for eight instructions. These with mnemonics are:
1. adi - Add the immediate value to the input register
and place in the output register,
2. adm - Add memory location addressed by the
immediate to the input register and place in the
output register,
3. lmi - Load the contents of the memory location
Figure 5. Four-bit ALU addressed by the immediate value to the input
register,
The most important learning outcome of this design is an
appreciation for how logic circuits can perform the kinds of 4. som - Save the output register to the memory
operations we see computers perform. location addressed by the immediate value,
5. ji - Jump to the location given in the immediate,
 6. jzi - Jump to the location given by the immediate registers and memory are writing enabled. This enables
if the result of the last addition was zero, demonstration of the inputs to commands being set up and
then the operation being executed.
7. om - Output the data from the memory location
addressed by the immediate to the output display One non-physical device available in the logic emulator
device, used is a binary controlled text display. This device can be
seen just below the vertical column of control line
8. hlt - Halt operation.
indicators. This display shows one of sixteen lines of text,
The physical architecture was to use two separate depending on the binary inputs to the device. In this case
memories, to hold the data and program. This parallels the the device is used to show the operation being set up in the
MIPS emulator PC SPIM which has a “.data” segment of computer.
memory holding constant data and a “.text” segment that
The memory devices can be used as read-only devices
contains the machine instructions. This construction
reading content from an underlying file, or they can be
simplifies the data path of the computer, but limits the
initialized with a file and altered dynamically during
capability to do recursion. The design includes an input
program execution. For registers memory devices with all
register and an output register.
address lines grounded are used.
This design is a complete eight-bit, single cycle, stored
One limitation of this emulation package is the absence of a
program computer. The data paths are connected at the
2-by-8 multiplexer. As a result the multiplexers are
start of the clock cycle at then at the clock transition
assembled by stacking a series of 1-by-2 multiplexers

Figure 7. Eight-bit teaching computer design implemented in multimedia logic

partially overlapping one another. Since this emulator is 00 zero (not used)
published with its source code, I have built versions of this
computer using a version of the software with a modified 19 Hex for character count in alphabet
ALU that has an A out and a B out instruction. Then the ff Twos complement negative one
multiplexer stacks can be replaced with ALUs. I have not fe Twos complement negative two (not used)
included this design because it uses ALUs in a non-
standard way and because the design could not be used 41 ASCII code for letter A
with the emulator down loaded from the emulator’s web 41 (not used)
site.
41 "

4. Sample Programs for the Computer 00 "

00 "
With this set of instructions a number of demonstration
programs have been written. The file underlying the 00 "
memory has a format that includes two hexadecimal digits
that are the memory content for each line. The memory
Table 1. Data memory content for program 1
ignores any additional information on the line. So
following the operation code or data a comment can be
given. This allows instruction documentation information
to be included with each line. These include a program to c4 Output from memory location 04
send a string in data memory to the output display device, a 44 Load input register from memory location 4
program with an up counting loop and a down counting 01 Add I (01) to input register
loop to display the letters of the alphabet and halt at Z, and
a program to display various size boxes on the display. 64 Save output register in memory location 04
c4 Output from memory location 04
The design includes two ALUs, one incrementing the
program counter and one performing the additions. 41 load input register from memory location 01
Memory devices include a data memory, program memory, 22 Add from memory location 02
input register, output register, program counter, and an
61 Save output register to memory location 02
operation decode ROM. The nicest feature of
implementing a computer design this way, rather that in a aa Jump if last calculation result was zero to 0a
breadboard, is the much greater instrumentation of 80 Jump to memory location 00(+1)
registers, and data lines. One can see each value as the
e0 Halt execution
computer steps through the program.
Three sample programs are included in this section.
Table 2. Program memory content
4.1 Sample Program 1, ABCs. for program 1
This first program was designed to be simple but use all
eight of the operations of this computer. It consists of a
loop that counts up one memory location from ASCII A to
ASCII Z, and counts down in another location to halt the 4.2 Sample Program 2, Hello World.
computer after 26 letters. To implement this program the The second program was to be the simplest possible, like
memory contents in the following tables are place into the the “Hello World” used to introduce all programming
data and program memories. Note that in these tables that languages. For this program a string in the data memory is
the two hex digits in each line are the actual output from sent character by character to the output screen and then
the memory device and the rest of the line is a comment. the program loops back to the beginning. The lack of
Data and program memory files are shown if tables 1 and 2 instructions to update program memory based on
below. The output is shown with figure 7 above. calculations prevents the use of simple iteration to
implement this program. The data and program memory
files are show in tables 3 and 4 and the output is shown in
figure 8.
 20 Space on the output screen. Data and program memory files are
given below and the output is shown in figure 8.
20 Space
48 H
06 column (size of triangle)
45 E
03 row (not used in program)
4c L
00 column step
4c L
00 row step
4f O
ff negative one (allows decrementing )
20 Space
00 zero
57 W
2a symbol "*"
4f O
0d new line
52 R
4c L Table 5. Data memory content for program 3
44 D
21 !
0d New Line 45 Load input register from memory location 5 (zero)
20 Add memory location 0 (column) to input register
Table 3. Data memory content for program 2 62 Save result in memory location 2 (column step)
63 Save result in memory location 3 (row step)
c6 lp1: Output from memory location 6 (symbol "*")
44 Load input register from memory location 4 (neg
c0 Output from memory location 00 one)
c1 Output from memory location 01 22 Add from memory location 2 (column step)
c2 Output from memory location 02 62 Save result in memory location 2 (colmn step)
c3 Output from memory location 03 a9 Jump on zero to lp2:
c4 Output from memory location 04 83 Jump to lp1:
c5 Output from memory location 05 23 lp2: Add from memory location 3 (row step)
c6 Output from memory location 06 63 Save result in memory location 3 (row step)
c7 Output from memory location 07 b6 Jump on zero to :hlt
c8 Output from memory location 08 c7 Output from memory location 7 (new line)
c9 Output from memory location 09 45 Load input register from memory location 5 (zero)
ca Output from memory location 0A 20 Add memory location 0 (column) to input register
cb Output from memory location 0B 44 Load input register from memory location 4 (neg
cc Output from memory location 0C one)
cd Output from memory location 0D 20 Add memory location 0 (column) to input register
ce Output from memory location 0e 60 Save result in memory location 0 (column)
80 Jump to Zero (+1) 45 Load input register from memory location 4 (neg
one)
20 Add memory location 0 (column) to input register
Table 4. Program memory content
for program 2 62 Save result in memory location 2 (column step)
83 Jump to lp1:
eo hlt: Halt

4.3 Sample Program 3, Triangle. Table 6. Program memory content for program 3
This program was written to test the assembler discussed in
the next section. It uses two nested loops to print a triangle
 ********** Operation Code **********
******************************************
********* adi- Add Immediate *********
********* adm- Add Memory *********
********* lmi- Load Mem -> Ri *********
********* som- Save Ro-> Mem *********
********* ji- Jump Immediate *********
********* jzi- J on z Im *********
********* om- Out Mem Im *********
********* Hlt- Halt *********
******************************************

************* Sample Input **************

Figure 8. Output screens for programs 2 and 3 ******************************************
.data
(PLease Input Data for DataMem.)
5. The Assembler in PERL numlet:26d
negone:ffh
To add to the utility of this computer, an assembler was acode:41h
designed in the PERL language. As the assembler runs it .text
generates text files that can be loaded into the data and (PLease Input Data for ProgramMem.)
program memory in the simulated computer. The omi acode
start:lmi acode
assembler allows symbolic linking between the data and adi 01d
the program and allows symbolic naming of jump som acode
locations. The assembler was patterned after the assembler om acode
imbedded in the MIPS emulator PC SPIM. lmi negone
adm numlet
This assembler starts execution by asking the user for data som numlet
and program memory file names. Then the user sees the jzi stop
screen from the table below which gives a review of the ji start
stop:hlt
instruction set of this computer and then provides a sample ********************************************
input file to show the syntax that must be used. When the Table 7. Assembler Output
line with the stop command is given, the program closes
the files and returns.

6. Student Computer Designs 7. Comments from Students

Using this computer and its design process as an example, In this section, student’s comments are provided to show
computer architecture students have been required to the value of this approach to teaching the inner-workings
design a computer of their own from the registers and of a computer. One student, Daniel McCallum, wrote in an
instruction set to layout and implementation with example email [2] after completing Computer Organization:
programs. The first design from a student team was an
elaborate 16-bit design that used eight cycles to decode and “Multimedia Logic has helped me a lot to comprehend
execute each instruction with the idea of demonstrating a many of the complex ideas behind the workings of a
pipeline implementation. This computer consisted of eight computer. It helps me see things visually and can look at
pages of logic. While this computer represents a great deal things one step at a time. For example how an ALU works
of effort on the part of the students involved, it is not as made a lot more sense when I could put it together and take
useful for demonstration because parts of the display are on it apart myself, using Multimedia Logic. Another big
separate pages and can not be viewed simultaneously. aspect of Multimedia Logic was that I can see all the
different switches, gates, etc. visually and have come to
Some students had difficulty designing a computer starting understand how basically a computer does what it does.”
with operations and layout. For these students the
approach that seemed to work best was to start with an Several students commented that they now understood how
application they would like to demonstrate on their circuits make computers and how computer functions can
computer and then design a computer to meet that be made from simple switching logic devices. Students
requirement. Some examples of the application-motivated that previously used breadboard devices commented that
designs were for an electronic door lock and a “Whack a understanding what was going on was much easier in the
Mole” game. emulated environment because each register can be
instrumented individually.
 8. Limitations of Multimedia Logic And a special thanks to the faculty and students of our
computer science department who have encouraged me in
One difficulty encountered with Multimedia Logic is the this effort by their enthusiastic support.
unexplained dropping of wires from saved files. This
occurs the first time a new file is saved and seems to be a
11. References
problem with overlapping components. For example a
horizontal row of eight light-emitting diodes will lose [1] Hoffman, Mark E., The Case for More Digital Logic in
connection to every other light when saved, if they are Computer Architecture, Conferences in Research and
placed adjacent to each other and are vertically lined up. Practice in Information Technology, Vol. 30.
The “work-around” for this problem is to stagger the lights [2] McCallum, Daniel, Email of 6/25/2004.
slightly in the vertical direction. This vertical staggering
can be seen in figures 1, 3 and 5. [3] Mills, George, www.softronix.com, Multimedia Logic
download kit and source kit.
9. Summary [4] Patterson, David A., and Hennessy, John L. Computer
Organization and Design, the Hardware/Software
A number of designs built in Multimedia Logic have Interface, 2nd Edition, Morgan Kaufmann Publishers .
shown to be useful to students in gaining an understanding
the inner workings of a computer and related technology. [5] Patterson, David A., and Hennessy, John L. Computer
Students in computer architecture classes have successfully Organization and Design, the Hardware/Software
used this tool to design many eight-bit and even two Interface, 3nd Edition, Morgan Kaufmann Publishers .
sixteen-bit computers, most with single cycle designs, but [6] Powers, Kris D., “Teaching Computer Architecture in
two with multi-cycle designs. Through this experience the Introductory Computing: Why? And How?” Sixth
details of how switches can make computers becomes very Australasian Computing Education Conference
clear. (ACE2004), Dunedin.
[7] Wolffe, Greg, Yurcik, William, Osborne, Hugh, and
10. Acknowledgments Holliday, Mark, “Teaching Computer
Thanks to George Mills of www.softronix.com, who has Organization/Architecture With Limited Resources
graciously made his product, Multimedia Logic, available Using Simulators”, SIGCSE 2002, ACM Press,
for free download and included the source code. Northern Kentucky USA, Feb/March 2002.

View publication stats