BEEE102L BASIC ELECTRICAL

AND ELECTRONICS
ENGINEERING

Dr.S.ALBERT ALEXANDER
SCHOOL OF ELECTRICAL ENGINEERING
[email protected]

Dr.S.ALBERT ALEXANDER-
SELECT-VIT 1
Module 5
◼ Number base conversion
◼ Binary arithmetic
◼ Boolean algebra
◼ Simplification of Boolean functions using K-maps
◼ Logic gates
◼ Design of basic combinational circuits:
◼ Adders (Half adder & Full adder)
◼ Multiplexers & De-multiplexers

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 2
5.1 Number Base Conversion
❖ The number systems are used quite frequently in the field
of digital electronics and computers
❖ However the type of number system used in computers
could be different at different stages of the usage
❖ For example, when a user key-in some data into the
computer, he/she will do it using decimal number system
❖ i.e. the system we all have used for several years for doing
arithmetic problems
❖ But when the information goes inside the computer, it
needs to be converted to a form suitable for processing
data by the digital circuitry
❖ When the data has to be displayed on the monitor for the
user, it has to be again in the decimal number system
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 3
 Types
There are several number systems but the following are the
important ones in the field of digital electronics:
❖ Decimal number system

❖ Binary number system

❖ Octal number system

❖ Hexadecimal number system

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 4
Binary to Decimal Conversion
❖ Following is the procedure for converting an integer (or
whole) binary number to its equivalent decimal number

❖ Step 1. Write the binary number

❖ Step 2. Directly under the binary number, write the position
values or weights of each bit working from right to left
❖ Step 3. If a zero appears in a digit position, cross-out the
weight for that position
❖ Step 4. Add the remaining weights to obtain the decimal
equivalent

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 5
 Exercise-1
Convert each of the following binary numbers to their decimal
equivalents : (a)101, (b) 10101, (c) 01010110.
SOLUTION:
a) 1 0 1

22 21 20
= 22+ 20= 4+1=5

b) 10101= 24 + 22 + 20 = 16 + 4 + 1 = 21

c) 01010110 = 26 + 24 + 22 + 21 = 64 + 16 + 4 + 2 = 86

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 6
 Exercise-2
Convert each of the following fractional binary numbers to
their decimal equivalents: (a) 0.1010, (b) 0.1100.
SOLUTION:
a) .1 0 1 0

2-1 2-2 2-3 2-4

= 2-1+ 2-3= 0.5+0.125=0.625

b) 0.1100= 2-1+ 2-2= 0.5+0.25=0.75

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 7
 Decimal to Binary Conversion
❖ The conversion from decimal-to-binary is usually
performed by a digital computer for ease of interpretation
by the person reading the number
❖ On the other hand, when a person enters a decimal
number into a digital computer, that number must be
converted to binary before it can be operated on

There are two methods of decimal-to-binary conversion:

❖ (1) Sum-of-weights method and

❖ (2) Repeated division by-2 method

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 8
 Exercise-3
Convert each of the following decimal numbers to their binary
equivalents using sum-of-weights methods: (a) 17, (b) 24, (c)
61, (d) 93.
SOLUTION:
a) 17= 16+1 = 24+20
24 23 22 21 20

1 0 0 0 1 = (10001)2
b) 24= 16+8 = 24+23 = (11000)2
c) 61= 32+16+8+4+1 = 25+24 +23 +22 +20 = (111101)2
d) 93= 64+16+8+4+1 = 26+24 +23 +22 +20 = (1011101)2

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 9
 Exercise-4
Convert the decimal fraction a) 0.375 and b) 0.625 by using
sum-of-weights method to its equivalent binary fraction.
SOLUTION:
a) 0.375= 0.25+0.125 = 2-2+2-3
20 2-1 2-2 2-3

0 0 1 1 = (0.011)2

b) 0.625= 0.5+0.125 = 2-1+2-3 = (0.1011)2

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 10
 Exercise-5
Convert each of the following decimal numbers using
repeated-division by-2 method. (a) 19 and (b) 45.
SOLUTION:
a) 19 ÷ 2 = 9 with a remainder 1 (LSB)
❖ 9 ÷ 2 = 4 with a remainder 1
❖ 4 ÷ 2 = 2 with a remainder 0
❖ 2 ÷ 2 = 1 with a remainder 0
❖ 1 ÷ 2 = 0 with a remainder 1 (MSB)
= (10011)2

b) 45=(101101)2

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 11
 Exercise-6
Convert the decimal fraction a) 0.9028 and b) 0.8125 to its
equivalent binary fraction (up to 4 binary places) using
repeated multiplication-by-2 method.
SOLUTION:
a) 0.9028 × 2 = 1.8056 = 0.8056 with a carry of 1 (LSB)
❖ 0.8056 × 2 = 1.6112 = 0.6112 with a carry of 1

❖ 0.6112 × 2 = 1.2224 = 0.2224 with a carry of 1

❖ 0.2224 × 2 = 0.4448 = 0.4448 with a carry of 0 (MSB)

= (0.1110)2

b) 0.8125 =(0.11010)2

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 12
Octal Number System

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 13
 Exercise-7
Convert the octal number a) 2374 and b) 326 to its equivalent
decimal.
SOLUTION:
a) 2 3 7 4

83 82 81 80
2x 83 +3x 82 +7x 81+4x80 = 1276

b) 3 2 6

82 81 80
3x 82 +2x 81+6x80 = 214
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 14
 Exercise-8
Convert the decimal number a) 266 and b) 435 to its
equivalent octal.
SOLUTION:
a) (266)10= (412)8
❖ 266 ÷ 8 = 33.25 with a remainder 0.25 →0.25 × 8 = 2 LSD
❖ 33 ÷ 8 = 4.125 with a remainder 0.125 → 0.125 × 8 = 1
❖ 4 ÷ 8 = 0.5 = 0 with remainder 0.5 →0.5 ×8= 4 MSD

b) (435)10= (663)8
❖ 435÷8 = 54.375 = 54 with a remainder 0.375→0.375 × 8 = 3 LSD

❖ 54 ÷ 8 = 6.75 = 6 with a remainder 0.75→ 0.75 × 8 = 6

❖ 6 ÷ 8 = 0.75 = 0 with a remainder 0.75→ 0.75 × 8 = 6 MSD

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 15
Exercise-9
Convert the octal number a) 321, b) 4653, c) 13274 to its
equivalent binary.
SOLUTION:
a) 3→011
2→ 010
1→ 001
= 011010001

b) 4653 → 100110101011

c) 13274 → 001011010111100

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 16
 Exercise-10
Convert the binary number a) 100111010 and b) 10111001 to
its equivalent octal.
SOLUTION:
a) 100→4
111→ 7
010→ 2
= 472

b) 010→ 2
111→ 7
001→ 1
=271
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 17
Hexadecimal Number System

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 18
 Exercise-11
Convert the hexadecimal number a) E5, b) 0.12, c) 2A6 to its
equivalent decimal.
SOLUTION:
a) (Ex161)+(5x160) =229

b) .(1x16-1)+(2x16-2) =0.0703

c) (2x162) (Ax161)+(6x160) =678

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 19
 Exercise-12
Convert the decimal number a) 650, b) 151, c) 498 to its
equivalent hexadecimal.
SOLUTION:
❖ a) 650÷16 = 40.625 = 40 with a remainder 0.625 → 0.625×16 = 10 (= A) LSD
❖ 40 ÷ 16 = 2.5 = 2 with a remainder 0.5 → 0.5 × 16 = 8
❖ 2 ÷ 16 = 0.125 = 0 with a remainder 0.125 → 0.125 × 16= 2 MSD
= 28A

b) 151→ 97

c) 498→ 1F2

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 20
 Exercise-13
Convert the hexadecimal number a) 2D6, b) 9F2, c) 2A6 to its
equivalent binary.
SOLUTION:
❖ a) 2→0010

D→1101
6→0110
=001011010110

b) 9F2→ 100111110010

c) 2A6→ 001010100110

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 21
Exercise-14
Convert the binary number a) 10111, b) 1111 110000, c)
1110.101 to its equivalent hexadecimal.
SOLUTION:
❖ a) 10111 → 00010111 → 17

❖ b) 1111 110000 → 001111 110000

→ 3F0

❖c) 1110.101 → 1110.1010

→EA

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 22
 Exercise-15
Convert the hexadecimal number a) 5C2, b) 8AD9, c) A7.3B
to its equivalent octal.
SOLUTION:
❖ a) 5C2 → 0101 1100 0010 → 2702

❖ b) 8AD9→ 1000 1010 1101 1001 → 42331

❖ c) A7.3B → 01010 0111 0011 10110 → 247.166

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 23
 Exercise-16
Convert the octal number a) 321 and b) 1024 to its equivalent
hexadecimal.
SOLUTION:
❖ a) 321 →011 010 001 → D1

❖ b) 1024→001 000 010 100 → 214

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 24
Exercise-17 (Fill the ?)

Decimal Binary Octal Hexa-decimal

19.6875 ? ? ?

? 11101.111100 ? ?

? ? 255.454 ?

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 25
Exercise-17 (Solution)

Decimal Binary Octal Hexa-decimal

19.6875 10011.10110 23.54 13.B

29.9375 11101.111100 35.74 1D.F

173.5859 10101101.10010110 255.454 AD.96

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 26
5.2 Binary Arithmetic (Addition)
❖ The addition of two binary numbers is performed in exactly
the same manner as the addition of decimal numbers
❖ Let us review the decimal addition: 264+173
1 2 6 4
carry 1 7 3
4 3 7
❖ Unlike decimal addition, there are only four cases that can
occur in binary addition
❖ 0+0=0
❖ 1+0=1
❖ 1 + 1 = 10 = 0 + carry of 1 into next position
❖ 1+ 1 +1 = 11 = 1+ carry of 1 into next position
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 27
 Exercise-18
a) Add 101 and 110.
1 0 1
1 1 0
10 1 1
b) Add 11 and 11.
1 1 1
carry 1 1
11 0
c) Add 100 and 10
1 0 0
1 0
1 1 0
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 28
 Exercise-19
a) Add 11.01 and 101.11.
1 1. 0 1
1 0 1. 1 1
10 0 1. 0 0

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 29
Binary Arithmetic (Subtraction)
❖ 0-0=0
❖ 1-0=1
❖ 1-1=0
❖ 0 - 1 = 1 (with borrow of 1)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 30
 Exercise-20
a) Subtract 101 from 1001.
1 0 0 1
1 0 1
0 1 0 0

b) Subtract 11 from 10000.

1 0 0 0 0
1 1
0 1 1 0 1

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 31
 Exercise-21
a) Subtract 100.10 and 110.01.
1 1 0. 0 1
1 0 0. 1 0
0 0 1. 1 1

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 32
Binary Arithmetic (x and )
❖ 0x0=0
❖ 0x1=0
❖ 1x0=0
❖ 1x1=1

❖ 01=0
❖ 11=1

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 33
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 34
BEEE102L BASIC ELECTRICAL
AND ELECTRONICS
ENGINEERING

Dr.S.ALBERT ALEXANDER
SCHOOL OF ELECTRICAL ENGINEERING
[email protected]

Dr.S.ALBERT ALEXANDER-
SELECT-VIT 1
Module 5
◼ Number base conversion
◼ Binary arithmetic
◼ Boolean algebra
◼ Simplification of Boolean functions using K-maps
◼ Logic gates
◼ Design of basic combinational circuits:
◼ Adders (Half adder & Full adder)
◼ Multiplexers & De-multiplexers

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 2
5.3 Boolean Algebra
❖ Boolean algebra is a convenient and systematic way of
expressing and analyzing the operation of logic circuits
❖ This class session covers the laws, rules and theorems of
Boolean algebra and their application to digital circuits
❖ We will learn to simplify the logic circuits using the methods
of Boolean algebra and Karnaugh maps
❖ Boolean algebra is an important mathematical tool for
designing and analysing digital systems
❖ A basic knowledge of Boolean Algebra is indispensable to
the study and analysis of logic circuits
❖ As in other areas of mathematics, there are certain well
developed rules and laws that must be followed in order to
apply Boolean Algebra properly
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 3
Rules of Boolean Algebra
❖ A.0=0
❖ A.1=A
❖ A+0=A
❖ A+1=1
❖ A+A=A
❖ A+Aഥ =1
❖ A.A=A
❖ ഥ =0
A. A
❖ ന
A=A
❖ A+AB=A
❖ ഥ
A+ AB=A+B
❖ (A+B)(A+C)=A+BC
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 4
Rules of Boolean Algebra
❖ (1) A.0=0
❖ (2) A.1=A
❖ (3) A+0=A
❖ (4) A+1=1
❖ (5) A+A=A
❖ (6) A+Aഥ =1
❖ (7) A.A=A
❖ ഥ =0
(8) A. A
❖ ന
(9) A=A
❖ (10) A+AB=A
❖ ഥ
(11) A+ AB=A+B
❖ (12) (A+B)(A+C)=A+BC
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 5
 Exercise 1
Simplify A+AB.
SOLUTION
❖ A+AB = A (1+B) → Factoring (distributive law)

❖ = A.1 → Rule 4: (1+B) = 1

❖ = A → Rule 2: A.1= A

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 6
 Exercise 2
ഥ B =A+B.
Simplify and show that A + A
SOLUTION
❖ A + Aഥ B = (A+AB)+ Aഥ B → Rule 10: A+AB=A
❖ (AA+AB) + Aഥ B → Rule 7: A.A=A
❖ AA+AB+A.A ഥ+Aഥ B → Rule 8 : A.A ഥ =0
❖ ഥ ) (A+B) → Factoring (distributive law)
(A+ A
❖ ഥ =1
1.(A+B) → Rule 6: A+A
❖ A+B → Rule 2→ A.1=A

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 7
 Exercise 3
Simplify and show that (A+B) (A+C) = A+BC.
SOLUTION
❖ (A+B) (A+C) = AA + AC+ AB + BC → Distributive law

❖ = A + AC + AB + BC → Rule 7: AA = A

❖ = A (1+C)+ AB+ BC → Factoring (distributive law)

❖ = A.1+AB + BC → Rule 4: 1+C =1

❖ = A (1+B) + BC → Factoring (distributive law)

❖ = A. 1 + BC → Rule 4: 1+B =1

❖ = A+ BC → Rule 2: A.1 =A

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 8
 Exercise 4
❖ ഥ
Simplify the expression ABD+A ഥ D.
B ഥ
SOLUTION
ഥ
❖ ABD+A ഥ D.
B ഥ
ഥ
❖ AB(D+ ഥ → Distributive law
D)
ഥ
❖ AB(1) → Rule 5: D+ D ഥ =1
ഥ → Rule 2: A.1 =A
❖ AB

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 9
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 10
BEEE102L BASIC ELECTRICAL
AND ELECTRONICS
ENGINEERING

Dr.S.ALBERT ALEXANDER
SCHOOL OF ELECTRICAL ENGINEERING
[email protected]

Dr.S.ALBERT ALEXANDER-
SELECT-VIT 1
Module 5
◼ Number base conversion
◼ Binary arithmetic
◼ Boolean algebra
◼ Simplification of Boolean functions using K-maps
◼ Logic gates
◼ Design of basic combinational circuits:
◼ Adders (Half adder & Full adder)
◼ Multiplexers & De-multiplexers

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 2
5.4 Standard forms of Boolean
❖ All Boolean expressions, regardless of their form, can be
converted into either of two standard forms : sum-of-
products (SOP) form or the product-of-sums (POS)
form

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 3
 Sum of products form
❖ In Boolean algebra, a product term (also called min-term)
is the product of literals (or Boolean variables)
❖ In logic circuits, a product term is produced by AND
operation with no OR operations.
❖ Few examples of product terms are : AB, AB, ഥ ABC
ഥ ABC, ഥ Dഥ
❖ A product term is equal to 1 if only if each of the literals in
the term is 1
❖ A product term is equal to 0 when one or more of the
literals are 0
❖ When two or more product terms are ORed (i.e. summed
by Boolean addition), the resulting expression is called
Sum-of-Products (SOP)
❖ Few examples of sum-of-products: AB+BCD, AB ഥ + ABC ഥ
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 4
 Sum of products form
❖ It may be carefully noted that sum-of-products expression
can contain a single variable term
❖ In a sum-of-products expression, a single overbar cannot
extend over more than one variable, although more than
one variable in a term can have an overbar
❖ For example, A ഥ BCഥ can be a term in sum-of-products
expression but not ABC
❖ The sum of product express as, in the form of min-term:
❖ = m0 + m1 + m2 + ... mn

❖ where m0, m2 ... are the min-terms

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 5
 SOP Implementation

❖ Notice that the number of AND gates is equal to the

number of terms in the sum-of-products expression
❖ The outputs of AND gates feed into the inputs of an OR
gate
❖ The output X of the OR gate equal the sum-of-products
expression
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 6
 Exercise 1
Convert the following Boolean expressions to SOP form:
ഥ
(A+B)(C+ B)
SOLUTION:
ഥ = AC+AB
a) (A+B)(C+ B) ഥ +BC+BB
ഥ
= AC+ABഥ +BC+0
= AC+ABഥ +BC

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 7
Standard SOP
❖ ഥ
ABCD+ ഥ BC
A ഥ Dഥ + AB ഥ is a standard SOP form because
ഥ CD
all the four variables A,B,C and D appear in each product
term in the expression
❖ SOP expression in which some of the product terms do
not contain all of the variables in the domain, is called
non-standard sum-of-products expression
❖ For example, the expression A ഥ BD
ഥ B C+A ഥ +AB CDഥ has a
domain made up of four variables A,B,C and D
❖ ഥ C
From the expression find that the first two terms (i.e. AB ഥ-
→ D or D ഥ
ഥ is missing and ABD→ ഥ is missing) does not
C or C
have a complete set of four variables in the domain
❖ Standard sum-of-product expressions are important in
constructing truth tables and in K-map simplification
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 8
 Exercise 2
ഥ
Convert the Boolean expression A BC+ ഥ D
BC ഥ D to a
ഥ +A C
standard sum-of products (SOP) form.
SOLUTION
ഥ
❖ ABC+ ഥ D
BC ഥ
ഥ +ACD
❖ ഥ = ABC(D+
ABC ഥ ഥ ABCD+
D)= ഥ ഥ D
ABC ഥ
❖ ഥ D
BC ഥ = BC
ഥ Dഥ (A+A)=
ഥ ABC
ഥ D+
ഥ A
ഥ BC
ഥ D ഥ
❖ ഥ = ACD
ACD ഥ (B+B)=
ഥ ABCDഥ + AB ഥ
ഥ CD
Thus the standard SOP (i.e. sum-of-products) form of the
given expression:
ഥ
= ABCD+ ഥ D+
ABC ഥ ABC
ഥ D+
ഥ A ഥ BC
ഥ D ഥ + AB
ഥ +ABCD ഥ
ഥ CD

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 9
Binary Representation
❖ Standard product term is equal to 1 for only one
combination of variable values
❖ For example the product term ABC ഥ D ഥ is equal to 1 when A =
1, B = 0, C = 1 and D = 0
❖ The product term ABC ഥ D ഥ is 0 for all other combinations of
values for the variables
❖ ABCഥ Dഥ = 101
ത 0ത =1.1.1.1=1
❖ Note that the product term ABC ഥ Dഥ has a binary value 1010
(i.e. decimal 10).
❖ A product term is implemented with an AND gate whose
output is 1 if and only if each of its inputs is 1
❖ INVERTERS are used to produce the complements of the
variables wherever required
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 10
 Exercise 3
Determine the binary values for which the following sum-of-
products (SOP) expression is equal to 1.
ഥ
ABCD+AB ഥ
CD+ ഥB
A ഥC ഥDഥ
SOLUTION
❖ We know that the given SOP expression is equal to 1 when
any or all of the three product terms are equal to 1
❖ The product term ABCD ഥ is equal to 1 when A=1, B=0,C=1,
ഥ
and D = 1, i.e., ABCD =1.0ത .1.1 =1.1.1.1=1
❖ The term ABCD ഥ is equal to 1 when A=1, B=1,C=0 and
D=1, i.e., ABCDഥ =1.1.0ത .1=1.1.1.1=1
❖ The term A ഥB ഥD
ഥC ഥ is equal to 1 when A = 0, B = 0, C = 0 and
ഥB
D = 0, i.e., A ഥCഥD
ഥ = 0.
ത 0.
ത 0.
ത 0ത =1.1.1.1=1

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 11
 Products of Sum form
❖ In Boolean algebra, a sum term (also called a max-term)
is the sum of literals (or Boolean variables)
❖ In logic circuits, a sum term is produced by an OR
operation with no AND operations involved
❖ Some examples of such terms are :
A+B, A+B, ഥ A+B+C
ഥ ഥ
and A+B+ ഥ +D
C
❖ A sum term is equal to 1 when one or more of the literals in
the term are 1
❖ A sum term is equal to 0 if and only if each of the literals is
0
❖ When two or more sum terms are multiplied, the resulting
expression is a product-of-sums (POS)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 12
 Products of Sum form
❖ Some examples of product-of-sums form are:
❖ ഥ A+B+C)
(A+B)( ഥ
❖ ഥ
(A+B)(A+B+C)(A+ ഥ
C)
❖ ഥ
(A+B+ ഥ
C)(C+ ഥ
D+E ഥ
)(B+C+D)
❖ POS expression can contain a single variable term
❖ In POS expression, a single overbar cannot extend over
more than one variable, although more than one variable in
a term can have an overbar
❖ For example, a POS expression can have the term
ഥ
A+B+ ഥ but not A+B + C
C
❖ The product of sums can be express in form of Maxterms,
= M0M1M2 ... Mn, where M0, M1 ... are the maxterms
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 13
 POS Implementation

❖ Notice that the number of OR gates is equal to the number

of terms in the product of sums expression
❖ The output of OR gates feed into the inputs of an AND gate
❖ The output X of the AND gate equals the product-of-sums
expression

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 14
Standard POS
❖ ഥ
(A+B+C+ ഥ (A
D) ഥ
ഥ +B+C+D) ഥ
(A+B+C+D) is a standard POS
form because all the four variables A,B,C and D appear in
each sum term in the expression
❖ POS expression in which some of the sum terms do not
contain all of the variables in the domain, is called non-
standard products of sum expression
❖ ഥ
For example, the expression (A+B+C)(B+C+ D) ഥ
ഥ (A+C+D) is
a non-standard product-of-sums expression, because all
the three sum terms do not have all the four variables
❖ Any non-standard product-of-sums expression can be
converted to the standard form using laws and rules of
Boolean algebra

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 15
 Exercise 4
ഥ (B+C) to a standard
Convert the Boolean expression (A+B)
product-of-sums (POS) form.
SOLUTION
ഥ (B+C)
❖ (A+B)
ഥ = (A+B)
❖ (A+B) ഥ (A+B+C)+
ഥ (C+C)= ഥ ഥ
ഥ C)
(A+B+
ഥ (A+B+C) (A+B+C)
❖ (B+C) = (B+C)(A+A)= ഥ

Thus the standard product-of-sums (POS) form of the given

expression:
ഥ
❖ = (A+B+C) (A+B+ ഥ (A+B+C) (A+B+C)
ഥ C) ഥ

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 16
Binary Representation
❖ Standard sum term is equal to 0 for only one combination
of variable values
❖ For example the sum term A+B+C+ ഥ Dഥ is equal to 0 when A
= 0, B = 1, C = 0 and D = 1
❖ The sum term A+B+C+ ഥ Dഥ is 1 for all other combinations of
values for the variables
❖ ഥ
A+B+C+ ഥ = 010
D ത 1ത =0.0.0.0=0
❖ Note that the sum term A+B+C+ ഥ ഥ has a binary value 0101
D
(i.e. decimal 5)
❖ A sum term is implemented with an OR gate whose output
is 0 if and only if each of its inputs is 0
❖ INVERTERS are used to produce the complements of the
variables wherever required
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 17
 Exercise 5
Determine the binary values for which the following product-
of-sums (POS) expression is equal to 0.
ഥ
(A+B+C+D) ഥ
(A+B+C+D) ഥ B+
(A+ ഥ D)
ഥ C+ ഥ
SOLUTION
❖ We know that the given POS expression is equal to 0 when
any or all of the three product terms are equal to 0
ഥ
❖ The term (A+B+C+D) is equal to 0 when A=0, B=1,C=0,
ഥ
and D = 0, i.e., (A+B+C+D) =0+1ത +0+0 =0+0+0+0=0
❖ The term (A+B+C+D) ഥ is equal to 0 when A=0, B=0,C=1
and D=0, i.e., (A+B+C+D)ഥ =0+0+1ത +0= 0+0+0+0=0
❖ The term (A+ഥ B+ ഥ D)
ഥ C+ ഥ is equal to 1 when A = 1, B = 1, C =
ഥ B+
1 and D = 1, i.e., (A+ ഥ D)
ഥ C+ ഥ =1+
ത 1+
ത 1+
ത 1ത =0+0+0+0=0

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 18
 Exercise 6
ഥ C
Convert into standard SOP and standard POS form:f=AB+B ഥ
SOLUTION
ഥ = AB(C+
SOP: AB ഥ ഥ = ABC+
C) ഥ ഥC
AB ഥ & BC=
ഥ BCഥ (A+A) ഥ + BC
ഥ = BCA ഥAഥ
ഥ C
AB+B ഥ =ABC+
ഥ ABഥCഥ + ABC
ഥ + AB
ഥ Cഥ
ഥ
ABC+ ABഥCഥ + ABCഥ + AB
ഥ C ഥ = 101 + 100 + 110 + 010
❖ There are 3 variables in the domain of this expression (i.e.
A, B and C), hence 23 (=8) possible combinations
❖ The given SOP expression contains four of these
combinations, so the POS must contain the other four
which are 000, 001, 011 and 111 Since these are binary
values that make the sum term 0, therefore the equivalent
ഥ B+
POS expression is, (A+ ഥ C)ഥ (A+
ഥ B+C)
ഥ ഥ
(A+B+C)(A+B+C)
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 19
 Exercise 7
ഥ
Find the maxterms for the expression: F = AC+AB ഥ ABC.
C+ ഥ
SOLUTION
ഥ AB
❖ Standard form: ABC+ ഥ ABC+
ഥ C+ ഥ ABC
ഥ
❖ Combining similar terms: ABC+ഥ AB ഥ ABC
ഥ C+ ഥ
❖ There are 3 variables in the domain of this expression (i.e.
A, B and C), hence 23 (=8) possible combinations
❖ The SOP contains three of these combinations, so the
POS must contain the other five which are 000,001, 010,
101 and 111
❖ Since these are binary values that make the sum term 0,
therefore the equivalent POS expression is, ( A+ ഥ Bഥ +Cഥ)
ഥ B+C)
(A+ ഥ ഥ
(A+B+ ഥ
C)(A+ ഥ
B+C) (A+B+C)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 20
 Exercise 8
Transform the following canonical expression into its other
canonical form in decimal notation.(i) f (x, y, z) = σ 𝑚(1, 3, 5).
SOLUTION
❖ f (x, y, z) = σ 𝑚(1, 3, 5)

❖ There are three variables x, y and z, then the total number

of term 23 (= 8)
❖ In the given SOP there are three terms, 1, 3 and 5

❖ The POS form contain the remaining five term, 0, 2, 4, 6

and 7
❖ The POS form of expression is given below :

❖ f (x, y, z) =M(0, 2, 4, 6, 7)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 21
 Exercise 9
Transform the following canonical expression into its other
canonical form in decimal notation.(ii) f (w, x, y, z) = M (0, 2,
5, 6, 7, 8, 9, 11, 12).
SOLUTION
❖ f (w, x, y, z) = M (0, 2, 5, 6, 7, 8, 9, 11, 12)

❖ In the above expression there are four variables, w, x, y

and z, the total number of term 24 (= 16)
❖ The given function is form of POS and it contain nine
terms. 0, 2, 5, 6, 7, 8, 9, 11 and 12
❖ The SOP form contain the remaining seven term, 1, 3, 4,
10, 13, 14 and 15
❖ The SOP form of expression is given below: f (w, x, y, z) =
σ 𝑚 (1, 3, 4, 10, 13, 14, 15)
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 22
 Exercise 10
Determine, the POS and SOP form of Z = σ 𝑚 (0, 1, 3, 6, 7,
8, 9, 13, 15)
SOLUTION
❖ The given function is form of min terms, so we directly find
out the SOP from the expression
❖ A ഥBഥCഥ D+
ഥ A ഥB ഥ
ഥ CD+ ഥ BCD+
A ഥ ഥ D+
ABC ഥ AB ഥ D+A
ഥC ഥ B ഥ + ABC
ഥ CD ഥ D+
ഥ
ABCD
❖ There are four variables in the domain of this expression
(i.e. A, B, C and D), there are total of 24 (=16) possible
combinations
❖ The SOP expression contains nine of these combinations,
so the POS must contain the other seven term. POS
terms= 0010 + 0100 + 0101 + 1010 + 1011 + 1100 + 1110
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 23
The Karnaugh Map
❖ The Karnaugh map (or simply a K-map) is similar to a truth
table because it presents all the possible values of input
variables and the resulting output for each value
❖ However, instead of being organized into columns and
rows like a truth table, the Karnaugh map is an array of
squares (or cells) in which each square represents a binary
value of the input variables
❖ The squares are arranged in a way so that simplification of
given expression with two, three, four, and five variables
Karnaugh maps to illustrate the principles
❖ The number of squares in a Karnaugh map is equal to the
total number of possible input variable combination (as is
the number of rows in a truth table
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 24
The Karnaugh Map
❖ For two variables, the number of square is 22 =4, for three
variables, the number of squares is 23 = 8 and for four
variables, the number of squares is 24 = 16

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 25
Mapping
Map the following SOP expression on the Karnaugh map :
ഥ BC+
A ഥ ഥ
ABC+AB Cഥ +ABC.
SOLUTION

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 26
 Rules for K-map
❖ The process that result in an expression containing the
minimum number of possible terms with the minimum
number of variables is called simplification or minimization
❖ After the SOP (or the Boolean) expression has been
mapped on the Karnaugh map, there are three steps in the
process of obtaining a minimum SOP expression

The three steps are :

❖ (a) grouping the 1s

❖ (b) determining the product term for each group and

❖ (c) summing the resulting product terms

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 27
Grouping the 1’s
❖ A group must contain either 1, 2, 4, 8 or 16 squares. In the
case of two-variable Karnaugh map, 4 squares is the
maximum group, for three-variable map, 8 squares are the
maximum group and so on
❖ Each square in the group must be adjacent to one or more
squares in that same group but all squares in the same
group do not have to be adjacent to each other
❖ Always include the largest possible number of 1s in a
group in accordance with rule 1
❖ Each 1 on the Karnaugh map must be included in at least
one group
❖ The 1s already in a group can be included in another group
as long as the overlapping groups include noncommon 1s
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 28
 Determining product term
❖ Group the squares that have 1s : Each group of squares
containing 1s creates one product term composed of all
variables that occur in only one form (either
uncomplemented or complemented) within the group are
eliminated. These are known as contradictory variables
❖ In order to determine the minimum product term for each
group, we need to look at the standard methodology for 3-
variable and 4-variable Karnaugh map respectively
(i) For a 3-variable K-map:
(1) for 1-square group we get a three-variable product term,
(2) for a 2-square group, we get a two-variable product term,
(3) for a 4-square product term, we get a one-variable product
term
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 29
 Determining product term
(ii) For a four-variable K-map:
❖ (1) For a 1-square group, we get a four-variable product
term
❖ (2) for a 2-square group, we get a three-variable product
term
❖ (3) for a 4-square group, we get a two-variable product
term
❖ (4) for a 8-square group, we get a one variable product
term

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 30
Summing the resultant terms
❖ When all the minimum product terms are derived from the
Karnaugh map, these are summed to form the minimum
sum-of-products expression
❖ In some cases, there may be more than one way to group
the 1s to form the product terms
❖ Whatever be the way, the minimal expression must have
the same number of product terms and each product term,
the same number of Boolean variables

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 31
Rules Summary

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 32
Rules Summary

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 33
Rules Summary

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 34
Rules Summary

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 35
 Exercise 11
Simplify the following SOP expression using the Karnaugh
mapping procedure:
X=AB ഥ
ഥ CD+ ഥ +A
ഥ CD
AB ഥB ഥ + ABCD
ഥ CD ഥ +ABCD+ABC ഥDഥ
SOLUTION

ഥ + CD
Simplified SOP expression: ABD+ABC ഥ
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 36
 Exercise 12
Simplify the following SOP expression using the K-map:
ഥD
X=BC ഥ + AB ഥ + ABCD
ഥ CD ഥ + ABCD
ഥ +ABCD
SOLUTION
❖ The expression to converted into standard form as,
ഥD
❖ X= BC ഥ (A+A)+
ഥ AB ഥ + ABCD
ഥ CD ഥ + ABCD
ഥ +ABCD
❖ X=ABCഥDഥ + AB
ഥ CഥD
ഥ + AB ഥ + ABCD
ഥ CD ഥ + ABCD
ഥ +ABCD

ഥ +BD
Simplified SOP expression: BC
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 37
 Activity
Write the logic functions for the following:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 38
Activity- Solutions

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 39
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 40
BEEE102L BASIC ELECTRICAL
AND ELECTRONICS
ENGINEERING

Dr.S.ALBERT ALEXANDER
SCHOOL OF ELECTRICAL ENGINEERING
[email protected]

Dr.S.ALBERT ALEXANDER-
SELECT-VIT 1
Module 5
◼ Number base conversion
◼ Binary arithmetic
◼ Boolean algebra
◼ Simplification of Boolean functions using K-maps
◼ Logic gates
◼ Design of basic combinational circuits:
◼ Adders (Half adder & Full adder)
◼ Multiplexers & De-multiplexers

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 2
 5.5 Logic Gates
❖ Basic building blocks for forming digital electronic circuitry
❖ It has one output terminal and one or more input terminals

❖ Its output would be HIGH (1) or Low (0) depending on the

digital level (s) at the input terminal (s)
❖ The logic gates can be used to design digital systems that
will evaluate digital input levels and produce a specific
output response based on that particular logic circuit
design
Logic gates:
❖ (1) INVERTER (or NOT gate) (2) AND gate (3) OR gate (4)
NAND gate (5) NOR gate (6) Exclusive-OR gate (7)
Exclusive- NOR gate
❖ NAND and NOR are universal gates
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 3
Logic Gates
❖ The INVERTER, AND and OR gates are considered to be
the basic logic gates in the field of digital electronics
❖ The NAND, NOR, Exclusive-OR and Exclusive- NOR gates
are constructed using the basic logic gates

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 4
Inverter (NOT)
❖ The INVERTER is also known as a NOT gate
❖ It is a logic gate that performs inversion (also called
complementation) operation
❖ It changes one logic level to the opposite logic level, i.e.,
from HIGH to LOW level or from LOW to HIGH level
❖ In terms of bits, it changes a 1 to 0 and a 0 to 1

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 5
AND
❖ The AND gate is one of the basic gates from which all logic
functions are constructed
❖ It is composed of 2 or more inputs and a single output
❖ Note that inputs are shown on the left (labeled as A and B)
and the output is on the right (labeled as X)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 6
OR
❖ Like AND gate, the OR gate, is another basic logic gate
from which all logic functions are constructed
❖ It is composed of two or more inputs and a single output
❖ Notice that the inputs are shown on the left labelled as A
and B and the output is on the right (labelled as X)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 7
NAND
❖ The term NAND is a contraction of NOT-AND
❖ It implies an AND function with a complemented (or
inverted) output
❖ Notice that this symbol is the same as AND gate symbol
except for a small circle (or a bubble) on its output
❖ This small circle denotes the inversion operation

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 8
NOR
❖ The term NOR is a contraction of NOT-OR
❖ It implies an OR function with a complemented (or
inverted) output
❖ Notice that this symbol is the same as OR gate symbol
except for a small circle (or a bubble) on its output
❖ This small circle denotes the inversion operation

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 9
Ex-OR
❖ The exclusive –OR (abbreviated as XOR) gate has only
two-inputs
❖ Unlike the other logic gates we have discussed earlier, the
exclusive-OR gate has never more than two inputs
❖ The output is HIGH(1) only when the two inputs are at
opposite logic levels while the output is LOW(0) when the
two inputs are at same logic levels

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 10
Ex-NOR
❖ The bubble on the output of the XNOR gate symbol
indicates that its output is opposite to the output of the
XOR gate
❖ The output of an XNOR gate is HIGH(1) only when the two
inputs are at the same logic level
❖ The output is LOW(0) when the two inputs are at opposite
logic levels

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 11
 Exercise-1
Write the Boolean expression for output X of the logic circuit
shown below.

SOLUTION:
?

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 12
Exercise-1 (Contd.)
SOLUTION:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 13
 Exercise-2
Write the Boolean expression for output X of the logic circuit
shown below.

SOLUTION:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 14
Exercise-2 (Contd..)
SOLUTION:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 15
 Exercise-3
ഥ B
Sketch the logic circuit for the expression:(A+ ഥ).C
SOLUTION:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 16
Implementation of AND using NAND

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 17
Implementation of AND using NOR

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 18
Implementation of OR using NAND

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 19
Implementation of OR using NOR

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 20
Implementation of NOT using NAND

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 21
Implementation of NOT using NOR

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 22
Implementation of XNOR using NAND

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 23
Implementation of XNOR using NOR

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 24
Implementation of NOR using NAND

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 25
Implementation of NAND using NOR

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 26
Exercise-4
Sketch the logic circuit using universal gate for the
expression: F=((C'.B.A)'(D'.C.A)'(C.B'.A)')'
SOLUTION:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 27
Exercise-5
Sketch the logic circuit using universal gate for the
expression: F=(((C.B'.A)+(D.C'.A)+(C.B'.A))')'
SOLUTION:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 28
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 29
BEEE102L BASIC ELECTRICAL
AND ELECTRONICS
ENGINEERING

Dr.S.ALBERT ALEXANDER
SCHOOL OF ELECTRICAL ENGINEERING
[email protected]

Dr.S.ALBERT ALEXANDER-
SELECT-VIT 1
Module 5
◼ Number base conversion
◼ Binary arithmetic
◼ Boolean algebra
◼ Simplification of Boolean functions using K-maps
◼ Logic gates
◼ Design of basic combinational circuits: Adders (Half
adder & Full adder)
◼ Multiplexers & De-multiplexers

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 2
5.6 Combinational Circuits
❖ Combinational logic (sometimes also referred to as time-
independent logic) is a type of digital logic which is
implemented by Boolean circuits, where the output is a
pure function of the present input only

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 3
Combinational Circuits
❖ A combinational circuit is one where the output at any time
depends only on the present combination of inputs at that
point of time with total disregard to the past state of the
inputs
❖ The logic gate is the most basic building block of
combinational logic
❖ The logical function performed by a combinational circuit is
fully defined by a set of Boolean expressions
❖ The other category of logic circuits, called sequential logic
circuits, comprises both logic gates and memory elements
such as flip-flops

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 4
Combinational Circuits
❖ Half adder – to perform two bit binary addition
❖ Full adder – to perform three bit binary addition
❖ Multiplexer – binary information from one of many input
lines and directs it to a single output line [2n:1]
❖ Demultiplexer - Several output lines, one input line [1:2n]

❖ Encoder – similar to MUX, many input lines and n output

lines [2n:n]
❖ Decoder – similar to DeMUX, n input lines and many
output lines [n:2n]

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 5
5.7 Adders
❖ Combinational logic building blocks can be used to perform
addition and subtraction operations on binary numbers
❖ Addition and subtraction are the two most commonly used
arithmetic operations, as the other two, namely
multiplication and division, are respectively the processes
of repeated addition and repeated subtraction
❖ Half adder – to perform two bit binary addition
❖ Full adder – to perform three bit binary addition

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 6
Half Adder
❖ A half-adder is an arithmetic circuit block that can be used
to add two bits
❖ Such a circuit thus has two inputs that represent the two
bits to be added and two outputs, with one producing the
SUM output and the other producing the CARRY
❖ The Boolean expressions for the SUM and CARRY outputs
are given by:
❖ SUM S = AB+ ഥ AB
ഥ and CARRY C = AB

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 7
Half Adder
❖ SUM output is that of an EX-OR gate
❖ CARRY output is that of an AND gate
❖ However, these two expressions can certainly be
represented in different forms using various laws and
theorems of Boolean algebra to illustrate the flexibility that
the designer has in hardware-implementing as simple a
combinational function as that of a half-adder

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 8
Half Adder
❖ Half-adder implementation with only NAND gates as given
below
❖ One part of the circuit implements a two-input EX-OR gate
with two-input NAND gates
❖ The AND gate required to generate CARRY output is
implemented by complementing an already available
NAND output of the input variables

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 9
Full Adder
❖ A full adder circuit is an arithmetic circuit block that can be
used to add three bits to produce a SUM and a CARRY
output
❖ Such a building block becomes a necessity when it comes
to adding binary numbers with a large number of bits
❖ The full adder circuit overcomes the limitation of the half-
adder, which can be used to add two bits only

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 10
Full Adder
❖ The Boolean expressions for the SUM and CARRY outputs
are given by:
ഥ BC
❖ SUM S = A ഥ in+ ABC
ഥ in +ABC
ഥ in +ABCin
❖ ഥ in+ABC
CARRY Cout = ABC ഥ in+ABCin +ABCin

ഥ
Cout = AB+Cin(AB+ABഥ)

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 11
Full Adder
❖ ഥ BC
SUM S = A ഥ in+ ABC
ഥ in +ABC ഥ in +ABCin
❖ ഥ
SUM S = Cin (AB+A ഥ
B)+C ഥഥ
in (AB+AB)
❖ ഥ
SUM S = Cin (AB+A ഥ
B)+C ഥഥ
in (AB+AB)
❖ SUM S = Cin AB

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 12
Full Adder
❖ ഥ in+ABC
CARRY Cout = ABC ഥ in+ABCin +ABCin
❖ ഥ
CARRY Cout = AB+ Cin(AB+A ഥ)
B
❖ CARRY Cout = AB+ABCഥ in+ ABC
ഥ in
❖ CARRY Cout = AB(Cin+1)+ABCഥ in+ ABC
ഥ in
❖ CARRY Cout = ABCin+AB+ABC ഥ in+ ABC
ഥ in
❖ ഥ ABC
CARRY Cout = AB+ACin(B+B)+ ഥ in
❖ ഥ in
CARRY Cout = AB+ACin+ABC
❖ ഥ in
CARRY Cout = AB(Cin+1)+ACin+ABC
❖ CARRY Cout = ABCin+AB+ACin+ABcഥ in
❖ ഥ
CARRY Cout = BCin(A+A)+AB+AC in
❖ CARRY Cout = BCin+AB+ACin
Cin+1=1
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 13
Dr.S.ALBERT ALEXANDER-SELECT-
VIT 14
BEEE102L BASIC ELECTRICAL
AND ELECTRONICS
ENGINEERING

Dr.S.ALBERT ALEXANDER
SCHOOL OF ELECTRICAL ENGINEERING
[email protected]

Dr.S.ALBERT ALEXANDER-
SELECT-VIT 1
Module 5
◼ Number base conversion
◼ Binary arithmetic
◼ Boolean algebra
◼ Simplification of Boolean functions using K-maps
◼ Logic gates
◼ Design of basic combinational circuits:
◼ Adders (Half adder & Full adder)
◼ Multiplexers & De-multiplexers

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 2
5.8 Combinational Circuits
❖ Combinational logic (sometimes also referred to as time-
independent logic) is a type of digital logic which is
implemented by Boolean circuits, where the output is a
pure function of the present input only

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 3
Combinational Circuits
❖ Half adder – to perform two bit binary addition
❖ Full adder – to perform three bit binary addition
❖ Multiplexer – binary information from one of many input
lines and directs it to a single output line [2n:1]
❖ Demultiplexer - Several output lines, one input line [1:2n]

❖ Encoder – similar to MUX, many input lines and n output

lines [2n:n]
❖ Decoder – similar to DeMUX, n input lines and many
output lines [n:2n]

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 4
Multiplexer
❖ A multiplexer or MUX, also called a data selector, is a
combinational circuit with more than one input line, one
output line and more than one selection line
❖ Multiplexers in IC form almost invariably have an ENABLE
or STROBE input, which needs to be active for the
multiplexer to be able to perform its intended function
❖ A multiplexer selects binary information present on any one
of the input lines, depending upon the logic status of the
selection inputs, and routes it to the output line

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 5
Multiplexer
❖ If there are n selection lines, then the number of maximum
possible input lines is 2n and the multiplexer is referred to
as a 2n-to-1 multiplexer or 2n ×1 multiplexer
❖ 4-to-1 multiplexer:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 6
Multiplexer
❖ 8-to-1 multiplexers:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 7
Multiplexer
❖ 16-to-1 multiplexers:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 8
2:1 Multiplexer

Y = S' I0 + S I1

❖ For S = 0, the Boolean expression for the output becomes

Y = I0
❖ For S = 1, the Boolean expression for the output becomes
Y = I1
❖ Thus, inputs I0 and I1 are respectively switched to the
output for S = 0 and S = 1

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 9
4:1 Multiplexer
❖ The input combinations 00, 01, 10 and 11 on the select
lines respectively switch I0, I1, I2 and I3 to the output

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 10
 Typical Application of a MUX
Multiple Sources Selector Single
Destination

MP3 Player
Docking Station

Laptop
D0
Sound Card

MUX
D1
Y
D2

D3

Surround Sound System

Digital
Satellite
B A Selected Source
0 0 MP3
0 1 Laptop
Digital
Cable TV 1 0 Satellite
1 1 Cable TV

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De-Multiplexer
❖ A demultiplexer is a combinational logic circuit with an
input line, 2n output lines and n select lines
❖ It routes the information present on the input line to any of
the output lines
❖ The output line that gets the information present on the
input line is decided by the bit status of the selection lines
❖ 1-to-4 demultiplexer: truth table when the input line is held
HIGH

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 12
1:2 De-Multiplexer

S D Y1 Y0
0 0 0 0
0 1 0 1
1 0 0 0
1 1 1 0

Assume S is the Select Input, D is the Data Input and Y0 and Y1 are the
outputs of the 1-to-2 Demultiplexer.

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 13
1:2 De-Multiplexer
❖ The output Y0 is active when the combination of select line
and input line are active low and high respectively, i.e., SD
=01
❖ ഥ
Therefore, the expression for output Y0 is: Y0 = SD
❖ The output Y1 is active when the combination of select line
and input line are active high, i.e., S D = 1 1
❖ Therefore, the expression for output Y0 is: Y1 = S D
❖ The logic diagram can be designed using two AND gates
and one NOT gate as:

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 14
1:4 De-Multiplexer

S1 S0 D Y3 Y2 Y1 Y0
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 0 0
0 1 1 0 0 1 0
1 0 0 0 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 0 0
1 1 1 1 0 0 0
Dr.S.ALBERT ALEXANDER-SELECT-
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1:4 De-Multiplexer
❖ Y0 = S1 S0 D
❖ Y1 = S1 S0 D
❖ Y2 = S1 S0 D
❖ Y3 = S1 S0 D

Dr.S.ALBERT ALEXANDER-SELECT-
VIT 16
Typical Application of a DEMUX
Multiple
Single Source Selector Destinations
B/W Laser
Printer

Fax
D0

DEMUX
Machine
X D1

D2

D3
Color Inkjet
Printer

B A Selected Destination
0 0 B/W Laser Printer
0 1 Fax Machine Pen
Plotter
1 0 Color Inkjet Printer
1 1 Pen Plotter

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Dr.S.ALBERT ALEXANDER-SELECT-
VIT 18