Verilog HDL (18EC44)

Academic Year 2022-23

Digital System Design Using

Verilog
22ECU302
Dr. Girija.S
Asst. Professor
Dept. of ECE
Dr.AIT
1
Girija.S Dept. of ECE, Dr.Ambedkar Institute of Technology
 Verilog HDL (18EC44)

UNIT -5

Behavioral Modelling

2
Girija.S Dept. of ECE, Dr.Ambedkar Institute of Technology
 Verilog HDL

Behavioral modelling
The behavioral model describes the system by showing how the
output behaves according to the changes in the inputs.
The design is specified at algorithmic level.
Behavioral modeling uses two main blocks:
initial block
always block

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 Verilog HDL

Structured Procedures
1. always
2. initial
▪ Basic statements in behavioral modeling
▪ Other statements can appear only inside these
blocks
▪ always and initial represent separate activity
flow
▪ Both blocks begins at 0 simulation time
▪ Initial and always blocks cannot be nested
▪ Each initial and always block must form its own
block
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 Verilog HDL

initial
► Starts at zero simulation time
► executes only once during a simulation
► All initial blocks executed concurrently at
time 0
► begin-end is used to build initial blocks
(similar to {-} in C)
► Used mainly for initialization, monitoring
of waveforms and other processes that
must be executed only once during the
entire simulation run.
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 Verilog HDL

initial
The syntax is as follows:
initial [timing_control] procedural_statement

The procedural statement could be any of the following:

Selection_statement
Case_statement
Loop_statement

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 Verilog HDL
module stimulus;
reg x,y, a,b, m;
initial
m = 1'b0; // single statement need not be grouped

initial
begin
#5 a = 1’b1; // multiple statement need to be grouped
#25 b = 1’b0;
end

initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end

initial
#50 $finish;
endmodule

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 Verilog HDL
module stimulus;
Four initial blocks execute
reg x,y, a,b, m;
initial
in parallel at time 0
m = 1'b0;
If a delay #<delay> is
initial seen before a statement,
begin the statement is executed
#5 a = 1’b1; <delay> time units after
#25 b = 1’b0; the current simulation
end time.

initial Results
begin
#10 x = 1'b0; time statement executed
#25 y = 1'b1; 0 m = 1’b0;
end 5 a = 1’b1;
10 x = 1’b0;
initial 30 b =1’b0;
#50 $finish; 35 y = 1’b1;
#50 $finish; 50 $finish;
endmodule
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 Verilog HDL

always
➢ The always statement starts at simulation
time 0 and repeatedly executes the
statements within it in a loop fashion during
simulation
➢ The syntax is as below:
➢ always[timing_control]procedural_statement
➢ An always block is used to model a block
of activities that are continuously
repeated in a digital circuit

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 Verilog HDL

always

► Starts at zero simulation time

► executes continuously in a looping
fashion
► begin-end is used to build initial blocks
(similar to {-} in C)
► Models a block of activity that is repeated
continuously in a digital circuit

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 Verilog HDL
//always block
module clock_gen;

reg clock;

//Initialize clock at time zero

iinitial
clock = 1'b0;

//Toggle clock every half cycle (time period = 20)

always
#10 clock = ~clock;

initial
#1000 $finish;

endmodule

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 Verilog HDL

Procedural Assignment
► Update values of reg, integer, real or time variables
<lvalue> = <expression>

► Theleft-hand side of a procedural assignment

<lvalue> can be one of the following:
▪ A reg, integer, real or time register variable or a memory
element
▪ bit select of these variables (e.g., addr[0])
▪ A part select of these variables (e.g., addr[31:16])
▪ A concatenation of any of the above (e.g., {a, b[3:0]})

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 Verilog HDL

Blocking Assignment
► Executed in the order they are specified in a
sequential block

► Will not block execution of statements that follow

in a parallel block

► The “ = “ operator is used to specify

blocking assignments

► Use blocking statements to build combinational

logic block
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 Verilog HDL
Example : Blocking Statements
module dummy;

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;

//All behavioral statements must be inside an initial or always block

initial
begin
x = 0; y = 1; z = 1; //Scalar assignments (@ time 0)
count = 0; //Assignment to integer variables (@ time 0)
reg_a = 16'b0; reg_b = reg_a; //initialize vectors (@ time 0)
#15 reg_a[2] = 1’b1; //Bit select assignment with delay (@ time 15)
#10 reg_b[15:13] = {x, y, z}; //Assign result of concatenation to
//part select of a vector (@ time 25)
count = count + 1; //Assignment to an integer increment (@ time 25)
end
initial
$monitor($time, " x = %b, y = %b, z = %b, count = %0d, reg_a = %x, reg_b = %x",
x, y, z, count, reg_a, reg_b);

endmodule

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 Verilog HDL

Non-blocking Assignment
► Allows scheduling of assignments without
blocking execution of the statements that
follow in a sequential block
► A “ <= “ operator is used to specify non-
blocking assignments
► Executed last in the time step in which they are
scheduled, that is, after all the blocking
assignments in that time step are executed
► Usenon-blocking statements to build
Sequential logic block

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 Verilog HDL
Non-blocking Statements

module dummy;

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;

//All behavioral statements must be inside an initial or always block

//Don’t mix blocking and non-blocking statements in one block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments (@ time 0)
count = 0; //Assignment to integer variables (@ time 0)
reg_a = 16'b0; reg_b = reg_a; //initialize vectors (@ time 0)
#15 reg_a[2] <= 1’b1; //Bit select assignment with delay (@ time 15)
#10 reg_b[15:13] <= {x, y, z}; //Assign result of concatenation to
//part select of a vector (@ time 10)
count <= count + 1; //Assignment to an integer increment (@ time 0)
end
initial
$monitor($time, " x = %b, y = %b, z = %b, count = %0d, reg_a = %x, reg_b = %x",
x, y, z, count, reg_a, reg_b);
endmodule

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 Verilog HDL

Applications of Non Blocking Assignments

► They are used as a method to model several

concurrent data transfers that take place
after a common event

►Disadvantage:Degradation in the simulator

performance and increase in memory usage

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 Verilog HDL
Applications of Non Blocking Assignments
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1; //The old value of reg1
end

► At each positive edge of clock following sequence takes place for the
non-blocking assignments.
1. Read operation is performed on each right-hand-side variable (in1, in2,
in3 and reg1), at the positive edge of clock and expressions are
evaluated
2. Write operations to the left-hand-side variables are based on the intra-
assignment delay in each assignment
3. Write operations are executed at the scheduled time steps.

► The order in which the write operations are executed is not known
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 Verilog HDL
Non-blocking statements to eliminate race conditions

//Illustration 1: Two concurrent always blocks with blocking statements

always @(posedge clock)

a = b;

always @(posedge clock)

b = a;

//Illustration 2: Two concurrent always blocks with nonblocking

statements

always @(posedge clock)

a <= b;

always @(posedge clock)

b <= a;

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 Verilog HDL

Processing of non-blocking assignment

always @(posedge clock)

begin
//Read operation
//store values of right-hand-side expressions in temporary variable
temp_a = a;
temp_b = b;

//Write operation
//Assign values of temporary variables to left-hand-side variables
a = temp_b;
b = temp_a;
end
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 Verilog HDL

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 Verilog HDL

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 Verilog HDL

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 Verilog HDL

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 Verilog HDL

Conditional Statements
► if statement
▪ if (<expression>)
true_statement;
▪ if (<expression>)
true_statement;
else
false_statement;
▪ if (<expression>)
true_statement1;
else if (<expression>)
true_statement2;
:
else (<expression>)
default;

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 Verilog HDL
Conditional statement example

//Type 1 Statements
if (!lock) buffer = data;
if (enable) out = in;

//Type 2 statements
if (number_queued < MAX_Q_DEPTH)
begin
data_queue = data;
number_queued = number_queued + 1;
end
else
$display (“Queue Full. Try again”);

//Type 3 statements
//Execute statements based on ALU control signal.
if (alu_control == 0)
y = x + z;
else if ( alu_control == 1)
y = x – z;
else
$

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 Verilog HDL

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 Verilog HDL

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 Verilog HDL

Case Statements
► case statement
▪ case (<expression>)
alternative1 : statement1; //block or statement
alternative2 : statement2;
:
default : default_statement; //optional
endcase
▪ case statement compares 0, 1, x and z values
in the expression and the alternative bit for bit.
If unequal bit width, they are filled with zero to
match the widest width.
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 Verilog HDL

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 Verilog HDL
Example : multiplexer with case statement

module mux4_to_1 (out, i0,i1, i2, i3, s1, s0);

//Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

Case ({s1, s0}) //Switch based on concatenation of control signals
2’d0 : out = i0;
2’d1 : out = i1;
2’d2 : out = i2;
2’d3 : out = i3;
default: $display (“Invalid control signals”);
endcase

endmodule

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 Verilog HDL

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 Verilog HDL
Example : case statement with x and z

module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);

// Port declarations from the I/O diagram

output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;

always @(s1 or s0 or in)

case ({s1, s0}) //Switch based on control signals
2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end
2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end

//Account for unknown signals on select. If any select signal is x then outputs are x. If any select signal is
//z, outputs are z. If one is x and the other is z, x gets higher priority.

2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx :

begin
out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx;
end
2'bz0, 2'bz1, 2'b, 2'b0z, 2'b1z :
begin
out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz;
end
default: $display("Unspecified control signals");
endcase
endmodule

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 Verilog HDL
Example : case statement with x and z continue…..

module stimulus;

wire OUT0, OUT1, OUT2, OUT3;

reg IN, S1, S0;

//instantiate the decoder

demultiplexer1_to_4 dm0( OUT0, OUT1, OUT2, OUT3, IN, S1, S0);
initial
$monitor($time,"OUT0 = %b,OUT1= %b,OUT2= %b,OUT3= %b,IN= %b,S1= %b,S0= %b“,
OUT0, OUT1, OUT2, OUT3, IN, S1, S0);
initial
begin
#5 IN = 1; S1 = 0; S0 = 0;
#5 IN = 1; S1 = 0; S0 = 1;
#5 IN = 1; S1 = 1; S0 = 0;
#5 IN = 1; S1 = 1; S0 = 1;
#5 IN = 1; S1 = 1'bx; S0 = 0;
#5 IN = 1; S1 = 0; S0 = 1'bx;
#5 IN = 1; S1 = 1'bz; S0 = 0;
#5 IN = 1; S1 = 0; S0 = 1'bz;
#5 IN = 1; S1 = 1'bx; S0 = 1'bz;
end
endmodule
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 Verilog HDL
casez : treats all z values in the case
casex use alternatives as the case expression as
don’t care

reg [3:0] encoding; casex : treats all z & x values as don’t

care
integer state;
casex (encoding) //logic value x represents a don”t care bit.
4’b1xxx : next_state = 3;
4’bx1xx : next_state = 2;
4’bxx1x : next_state = 1;
4’bxxx1 : next_state = 0;
default : next_state = 0;
endcase

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 Verilog HDL

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 Verilog HDL

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 Verilog HDL

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 Verilog HDL

LOOPS
► while(<expression>) //any logical expression

module count_mod;

//Illustration 1: Increment count from 0 to 127.

//Exit at count 128. Display the count variable.

integer count; initial

begin

count = 0;
while (count < 128) //Execute loop till count is 127.
//exit at count 128
begin
$display("Count = %d", count);
count = count + 1;
end
end
endmodule

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 Verilog HDL

LOOPS
► For (initial_condition; condition; change of value)

▪ Example

module counter;

integer count;

initial
for ( count=0; count < 128; count = count + 1)
$display("Count = %d", count);
endmodule

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 Verilog HDL

► repeat
▪ Executes the loop a fixed number of times
▪ Must contain a number (constant, variable, signal value)
▪ Variable or signal value evaluated only when the loop starts

▪ Example

module counter;
//Illustration 1 : increment and display count from 0 to 127

integer count;

initial
begin
count = 0;
repeat(128)
begin
$play("Count = %d", count);
count = count + 1;
end
end
endmodule
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42
 Verilog HDL
► forever
▪ No expression
▪ Executes forever until $finish is encountered
▪ Can also be exited using disable
▪ Without a timing constrain this statement is executed indefinitely
▪ Useful to generate a clock in test bench

▪ Example 7.20

module clock_gen;
//Example 1: Clock generation
//Use forever loop instead of always block

reg clock;

initial
begin
clock = 1'b0;
forever #10 clock = ~clock; //Clock with period of 20 units
initial
#100000 $finish;

endmodule

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 Verilog HDL

GATE LEVEL MODELLING

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 Verilog HDL

Gate level modeling

Gate types:
Verilog supports basic gates as predefined
primitives. These primitives are instantiated like
modules, except that they are predefined in
Verilog and do not need a module definition.
There are two classes of basic gates:
And/or gates
Buf/not gates

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 Verilog HDL

AND/ OR GATES
Have one scalar output & multiple scalar inputs.
The o/p of a gate is evaluated as soon as one of
the i/p changes

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 Verilog HDL

AND/ OR GATES

Example gate instantiation of and/or gates

Wire OUT,IN1,IN2;
and a1(OUT,IN1,IN2);
nand na1(OUT,IN1,IN2);
or or1(OUT,IN1,IN2);

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 Verilog HDL

AND/ OR GATES

Example gate instantiation of and/or gates

//more than 2 inputs; 3 inputs
nand na2(OUT,IN1,IN2,IN3);

//gate instantiation without instance name

and (OUT,IN1,IN2) //legal(Anonymous)

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 Verilog HDL

AND/ NAND GATE Truth Table

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 Verilog HDL

OR/ NOR GATE Truth Table

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 Verilog HDL

XOR/ XNOR GATE Truth Table

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 Verilog HDL

BUF / Not gates

They have one scalar input &one or more scalar outputs.
The last terminal in the port list is connected to the
input. Other terminal is connected to the outputs.

Eg: buf b1(out1,in);

not n1(out1,in);

buf b1_2(out1,ou12,in); // more than 2 o/p’s

not (out1,in); //legal gate - without instance name

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 Verilog HDL

BUF/ NOT GATE Truth Table

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 Verilog HDL

BUFif/ NOTif GATE Truth Table

Gates with an additional control signal to buffer & not

gates are also available

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 Verilog HDL

bufif1 GATE Truth Table

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 Verilog HDL

notif1 GATE Truth Table

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 Verilog HDL

bufif0 GATE Truth Table

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 Verilog HDL

notif0 GATE Truth Table

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 Verilog HDL

These gates are used when multiple drivers, drive the

signal and only when the control signal is asserted.
bufif1 b1(out)
bufif0 b0(out)

// instantiation
notif1 n1(out)
notif0 n0(out)

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 Verilog HDL

Array Instantiation
For repetitive instances representation, differ from each
other only by index of vector to which they are connected.
wire [7:0] out,in1,in2;
//basic gate instantiations
nand n-gate[7:0] (out,in1,in2);
//equivalent to following
nand n-gate0(out[0], in1[0], in2[0]);
nand n-gate1(out[1], in1[1], in2[1]);
nand n-gate2(out[2], in1[2], in2[2]);
nand n-gate3(out[3], in1[3], in2[3]);
nand n-gate4(out[4], in1[4], in2[4]);
nand n-gate5(out[5], in1[5], in2[5]);
nand n-gate6(out[6], in1[6], in2[6]);
nand n-gate7(out[7], in1[7], in2[7]);
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 Verilog HDL

Gate level Multiplexer

4:1 mux with 2 select signals, used to connect 2 or more
sources to a single destination, also used to implement
Boolean function.
S1 S0 out

0 0 I0

0 1 I1

1 0 I2

1 1 I3

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 Verilog HDL

Logic Diagram Multiplexer

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 Verilog HDL

Code for Multiplexer

module mux_4to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0,i1,i2,i3; and(y1,i1,s1n,s0);
input s1,s0; and(y2,i2,s1,s0n);
wire s1n,s0n; and(y3,i3,s1,s0);
wire y0,y1,y2,y3; // 4 input or gates
// gate instantiation or(out,y0,y1,y2,y3);
not (s1n,s1); //~(s1) endmodule
not (s0n,s0);
// 3 i/p and gates
and(y0,i0,s1n,s0n);

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 Verilog HDL

Stimulus Code for Multiplexer

// define module
module stimulus;
reg in0,in1,in2,in3;
reg s1,s0; //declare output wire
wire output; //instantiate mux
mux_4to1 mymux(output,in0,in1,in2,in3,s1,s0);
initial
begin
in0=1; in1=0; in2=1; in3=0; //set i/p lines
#1 $display (“in0=%b, in1=%b, in2=%b, in3=%b\n”
,in0,in1,in2,in3);
//choose in0

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 Verilog HDL

Stimulus Code for Multiplexer

s1=0; s0=0;
#1 $display(“s1=%b, s0=%b, output=%b\n”, s1, s0, output);
//choose in1
s1=0; s0=1;
#1 $display(“s1=%b, s0=%b, output=%b\n”, s1, s0, output);
//choose in2
s1=1; s0=0;
#1 $display(“s1=%b, s0=%b, output=%b\n”, s1, s0, output);
//choose in3
s1=1; s0=1;
#1 $display(“s1=%b, s0=%b, output=%b\n”, s1, s0, output);
end
endmodule

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 Verilog HDL

Stimulus Code for Multiplexer

The o/p of simulation:

in0=1, in1=0, in2=1, in3=0

s1=0, s0=0, output=1
s1=0, s0=1, output=0
s1=1, s0=0, output=1
s1=1, s0=1, output=0

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 Verilog HDL

4-bit Ripple carry adder

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 Verilog HDL

4-bit Ripple carry adder

Sum= a xor b xor cin

Cout= a.b+cin(a xor b)

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 Verilog HDL

1-bit Adder

Sum= a xor b xor cin

Cout= a.b+cin(a xor b)

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 Verilog HDL

1-bit Adder Truth Table

X Y cin S cout Xi yi ci co
0 1 1 1
0 0 0 0 0
1 0 1 1
0 0 1 1 0
1 1 0 1
0 1 0 1 0
1 1 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Verilog HDL

Verilog Code for 1-bit Full Adder

module fulladd(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
wire s1,c1,c2; //internal nets
//instantiate logic gate primitive
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,cin);
and (c2,s1,cin);
xor ( cout,c2,c1);
endmodule

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 Verilog HDL

Verilog Code for 4-bit RCA

module fulladder4(sum,cout,a,b,cin);
output [3:0]sum;
output cout;
input [3:0]a,b;
input cin;
wire c1,c2,c3; //internal nets
fulladd fa0(sum[0], c1, a[0], b[0], cin);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], cout, a[3], b[3], c3);
endmodule
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 Verilog HDL

Verilog Code for 4-bit RCA

module fulladder4(sum,cout,a,b,cin);
output [3:0]sum;
output cout;
input [3:0]a,b;
input cin;
wire c1,c2,c3; //internal nets
fulladd fa0(sum[0], c1, a[0], b[0], cin);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], cout, a[3], b[3], c3);
endmodule
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 Verilog HDL

Stimulus Code for 4-bit RCA

Stimulus for 4 bit ripple carry fa:

//define the stimulus

module stimulus;
//set up variables
reg[3:0]A,B;
reg CIN;
wire [3:0] SUM;
wire COUT;
//instantiate 4-bit fa
fulladd4 FA_4(SUM, COUT, A, B, CIN);
//set up monitoring signal

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 Verilog HDL

Stimulus Code for 4-bit RCA

Stimulus for 4 bit ripple carry fa:

//define the stimulus

module stimulus;
//set up variables
reg[3:0]A,B;
reg CIN;
wire [3:0] SUM;
wire COUT;
//instantiate 4-bit fa
fulladd4 FA_4(SUM, COUT, A, B, CIN);
//set up monitoring signal

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 Verilog HDL

Stimulus Code for 4-bit RCA

initial
begin
$monitor ($time, “A=%b, B=%b, CIN=%b, ------ COUT=%b, SUM=%b\n”, A, B, CIN,
COUT, SUM);
end
initial
begin
A=4’d0; B=4’d0; cin=1’b0;
#5 A=4’d3; B=4’d4;
#5 A=4’d2; B=4’d5;
#5 A=4’d9; B=4’d9;
#5 A=4’d10; B=4’d15;
#5 A=4’d0; B=4’d5; CIN=1’b1;
end
endmodule
Girija S ECE Dr.AIT
 Verilog HDL

Output for 4-bit RCA

output of simulation :

0 A=0000, B=0000, CIN=0, ------ COUT=0, SUM=0000

5 A=0011, B=0100, CIN=0, ------ COUT=0, SUM=0111
10 A=0010, B=0101, CIN=0, ------ COUT=0, SUM=0111
15 A=1001, B=1001, CIN=0, ------ COUT=1, SUM=0010
20 A=1010, B=1111, CIN=0, ------ COUT=1, SUM=1001
25 A=1010, B=0101, CIN=1, ------ COUT=1, SUM=0000

Girija S ECE Dr.AIT