lOMoARcPSD|49882446

MPMC UNIT-1

Electrical & Electronics (V.K.R, V.N.B & A.G.K College Of Engineering)

Scan to open on Studocu

Studocu is not sponsored or endorsed by any college or university

Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

UNIT -I
PART-1 8085 MICROPROCESSOR

Introduction
Microcomputer: The term microcomputer is generally synonymous with
personal computer, or a computer that depends on a microprocessor.
 Microcomputers are designed to be used by individuals, whether in
the form of PCs, workstations or notebook computers.
 A microcomputer contains a CPU on a microchip (the
microprocessor), a memory system (typically ROM and RAM), a bus
system and I/O ports, typically housed in a motherboard.
Microprocessor: A silicon chip that contains a CPU. In the world of personal
computers, the terms microprocessor and CPU are used interchangeably.
 A microprocessor (sometimes abbreviated µP) is a digital electronic
component with miniaturized transistors on a single semiconductor
integrated circuit (IC).
 One or more microprocessors typically serve as a central processing
unit (CPU) in a computer system or handheld device.
 Microprocessors made possible the advent of the microcomputer.
 At the heart of all personal computers and most working stations
sits a microprocessor.
 Microprocessors also control the logic of almost all digital devices,
from clock radios to fuel-injection systems for automobiles.
 Three basic characteristics differentiate microprocessors:
 Instruction set: The set of instructions that the microprocessor can
execute.
 Bandwidth: The number of bits processed in a single instruction.
 Clock speed: Given in megahertz (MHz), the clock speed determines
how many instructions per second the processor can execute.
 In both cases, the higher the value, the more powerful the CPU. For
example, a 32-bit microprocessor that runs at 50MHz is more
powerful than a 16-bit microprocessor that runs at 25MHz.

Downloaded by TEJASWINI VEERAVALLI ([email protected])

 lOMoARcPSD|49882446

 In addition to bandwidth and clock speed, microprocessors are

classified as being either RISC (reduced instruction set computer) or
CISC (complex instruction set computer)

8085 Microprocessor
The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It
was binary compatible with the more-famous Intel 8080 but required less
supporting hardware, thus allowing simpler and less expensive microcomputer
systems to be built. The "5" in the model number came from the fact that the
8085 requires only a +5-Volt (V) power supply rather than the +5 V, −5 V and
+12 V supplies the 8080 needed. The main features of 8085 μP are:
 It is an 8-bit microprocessor.
 It is manufactured with N-MOS technology.
 It has 16-bit address bus and hence can address up to 216= 65536
bytes (64KB) memory locations through A0–A15.
 The first 8 lines of address bus and 8 lines of data bus are
multiplexed AD0–AD7
 Data bus is a group of 8 lines D0–D7.
 It supports external interrupt request.
 A 16-bit program counter (PC)
 A 16-bit stack pointer (SP)
 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3.2 MHZ
single phase clock.
 It is enclosed with 40 pins DIP (Dual in line package).

8085 Architecture
8085 consists of various units as shown in Fig. 1 and each unit performs its
own functions. The various units of a microprocessor are listed below
 Accumulator
 Arithmetic and logic Unit
 General purpose register
 Program counter
 Stack pointer
 Temporary register
 Flags
 Instruction register and Decoder

2
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

 Timing and Control unit

 Interrupt control
 Address buffer and Address-Data buffer
 Address bus and Data bus

Accumulator
Accumulator is nothing but a register which can hold 8-bit data. Accumulator
aids in storing two quantities. The data to be processed by arithmetic and logic
unit is stored in accumulator. It also stores the result of the operation carried out
by the Arithmetic and Logic unit. The accumulator is also called an 8-bit register.
The accumulator is connected to Internal Data bus and ALU (arithmetic and logic
unit). The accumulator can be used to send or receivedata from the Internal Data
bus.

Arithmetic and Logic Unit

There is always a need to perform arithmetic operations like +, -, *, / and to
perform logical operations like AND, OR, NOT etc. So, there is a necessity for
creating a separate unit which can perform such types of operations. These
operations are performed by the Arithmetic and Logic Unit (ALU). ALU performs
these operations on 8-bit data. But these operations cannot be performed unless
we have an input (or) data on which the desired operation is to be performed.
So, from where do these inputs reach the ALU? For this purpose, accumulator is
used. ALU gets its Input from accumulator and temporary register. After
processing the necessary operations, the result isstored back in accumulator.

General Purpose Registers

Apart from accumulator 8085 consists of six special types of registers called
General Purpose Registers. These general-purpose registers are used to hold
data like any other registers. The general-purpose registers in 8085 processors
are B, C, D, E, H and L. Each register can hold 8-bit data. Apart from the above
function these registers can also be used to work in pairs to hold 16-bit data.
They can work in pairs such as B-C, D-E and H-L to store 16-bit data. The H-L pair
works as a memory pointer. A memory pointer holds the address of a particular
memory location. They can store 16-bit address as they work in pair.

3
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Fig. 8085 Architecture

Program Counter and Stack Pointer

Program counter is a special purpose register.
Consider that an instruction is being executed by processor. As soon as the
ALU finished executing the instruction, the processor looks for the next
instruction to be executed. So, there is a necessity for holding the address of the
next instruction to be executed in order to save time. This is taken care by the
program counter. A program counter stores the address of the next instruction
to be executed. In other words, the program counter keeps track of the memory
address of the instructions that are being executed by the microprocessor and
the memory address of the next instruction that is going to be executed.
Microprocessor increments the program whenever an instruction is being
executed, so that the program counter points to the memory address of the next
instruction that is going to be executed. Program counter is a 16-bit register.
Stack pointer is also a 16-bit register which is used as a memory pointer. A
stack is nothing but the portion of RAM (Random access memory).
So, does that mean the stack pointer points to portion of RAM?

4
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Yes. Stack pointer maintains the address of the last byte that is entered into
stack.
Each time when the data is loaded into stack, Stack pointer gets
decremented. Conversely it is incremented when data is retrieved from stack.

Temporary Register
As the name suggests this register acts as a temporary memory during the
arithmetic and logical operations. Unlike other registers, this temporary register
can only be accessed by the microprocessor and it is completely inaccessible to
programmers. Temporary register is an 8-bit register.

Flags
Flags are nothing but a group of individual Flip-flops. The flags are mainly
associated with arithmetic and logic operations. The flags will show either a
logical (0 or 1) (i.e.) a set or reset depending on the data conditions in
accumulator or various other registers. A flag is actually a latch which can hold
some bits of information. It alerts the processor that some event has taken place.
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Fig. Flag Register
Intel processors have a set of 5 flags.
1. Carry flag
2. Parity flag
3. Auxiliary carry flag
4. Zero flag
5. Sign flag
Consider two binary numbers.
For example
1100 0000
1000 0000
When we add the above two numbers, a carry is generated in the most
significant bit. The number in the extreme right is least significant bit, while the
number in extreme left is most significant bit. So, a ninth bit is generated due to
the carry. So how to accommodate 9th bit in an 8-bit register?
For this purpose, the Carry flag is used. The carry flag is set whenever a carry
is generated and reset whenever there is no carry. But there is an

5
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

auxiliary carry flag? What is the difference between the carry flag and auxiliary
carry flag?
Let’s discuss with an example. Consider the two numbers given below
0000 1100
0000 1001
When we add both the numbers a carry is generated in the fourth bit from
the least significant bit. This sets the auxiliary carry flag. When there is no carry,
the auxiliary carry flag is reset. So, whenever there is a carry in the most
significant bit Carry flag is set. While an auxiliary carry flag is set only when a
carry is generated in bits other than the most significant bit.
Parity checks whether it’s even or add parity. This flag returns a 0 if it is
odd parity and returns a 1 if it is an even parity. Sometimes they are also called
as parity bit which is used to check errors while data transmission is carried out.
Zero flag shows whether the output of the operation is 0 or not. If the value
of Zero flag is 0 then the result of operation is not zero. If it is zero the flag returns
value 1.
Sign flag shows whether the output of operation has positive sign or negative
sign. A value 0 is returned for positive sign and 1 is returned for negative sign.

Instruction Register and Decoder

Instruction register is 8-bit register just like every other register of
microprocessor. Consider an instruction. The instruction may be anything like
adding two data's, moving a data, copying a data etc. When such an instruction is
fetched from memory, it is directed to Instruction register. So, the instruction
registers are specifically to store the instructions that are fetched from memory.
There is an Instruction decoder which decodes the information present in the
Instruction register for further processing.

Timing and Control Unit

Timing and control unit is a very important unit as it synchronizes the
registers and flow of data through various registers and other units. This unit
consists of an oscillator and controller sequencer which sends control signals
needed for internal and external control of data and other units. The oscillator
generates two-phase clock signals which aids in synchronizing all the registers
of 8085 microprocessor.
Signals that are associated with Timing and control unit are:

6
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Control Signals: RD’, WR’, ALE

 ALE is used for provide control signal to synchronize the components
of microprocessor and timing for instruction to perform the
operation.
 RD (Active low) and WR (Active low) are used to indicate whether
the operation is reading the data from memory or writing the data
into memory respectively.

Status Signals: S0, S1, IO/M’

 IO/M (Active low) is used to indicate whether the operation belongs
to the memory or peripherals.

Table 1.1 Status signals and the status of data bus

IO/M’ (Active Low) S1 S2 Data Bus Status (Output)
0 0 0 Halt
0 0 1 Memory WRITE
0 1 0 Memory READ
1 0 1 IO WRITE
1 1 0 IO READ
0 1 1 Op code fetch
1 1 1 Interrupt acknowledge

DMA Signals: HOLD, HLDA, READY

 HOLD: Indicates that another master is requesting the use of the
address and data buses. The CPU, upon receiving the hold request,
will relinquish the use of the bus as soon as the completion of the
current bus transfer. Internal processing can continue. The processor
can regain the bus only after the HOLD is removed. When the HOLD
is acknowledged, the Address, Data RD, WR and IO/M’ lines are tri-
stated.
 HLDA: Hold Acknowledge: Indicates that the CPU has received the
HOLD request and that it will relinquish the bus in the next clock
cycle HLDA goes low after the Hold request is removed. The CPU
takes the bus one half-clock cycle after HLDA goes low.
 READY: This signal synchronizes the fast CPU and the slow memory,
peripherals. If READY is high during a read or write cycle, it indicates
that the memory or peripheral is ready to send or receive

7
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

data. If READY is low, the CPU will wait an integral number of clock
cycle for READY to go high before completing the read or write cycle.
READY must conform to specified setup and hold times.

Reset Signals: Reset in, Reset Out

RESET IN: A low on this pin;
 Sets the program counter to zero (0000H)
 Resets the interrupt enables and HLDA flip-flops.
 Tri-states the data bus, address bus and control bus.
 Affects the content of processors internal registers randomly.
On Reset, The Program counter sets to 0000h which causes the 8085 to
execute; the first instruction from address 0000H.
 RESET OUT: This active high signal indicates that the processor; is
being reset. This signal is synchronized to the processor clock and it
can be used to reset other devices connected in the system.

Interrupt control
As the name suggests this control interrupts a process. Consider that a
microprocessor is executing the main program. Now whenever the interrupt
signal is enabled or requested the microprocessor shifts the control from main
program to process the incoming request and after the completion of request,
the control goes back to the main program. For example, an Input/output device
may send an interrupt signal to notify that the data is ready for input. The
microprocessor temporarily stops the execution of main program and transfers
control to I/O device. After collecting the input data, the control is transferred
back to main program. Interrupt signals present in 8085 are:
 INTR
 RST 7.5
 RST 6.5
 RST 5.5
 TRAP
INTR is maskable 8080A compatible interrupt. When the interrupt occurs
the processor fetches from the bus one instruction, usually one of these
instructions: One of the 8 RST instructions (RST0 - RST7). The processor saves
current program counter into stack and branches to memory location N * 8
(where N is a 3 - bit number from 0 to 7 supplied with the RST instruction).

8
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

CALL instruction (3-byte instruction). The processor calls the subroutine,

address of which is specified in the second and third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 2CH
(hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 34H
(hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 3CH
(hexadecimal) address.
TRAP is a non-maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches to 24H
(hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI
instructions. RST5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled
individually using SIM instruction.

Serial Input/output control

The input and output of serial data can be carried out using 2 instructions
in 8085.
 SID-Serial Input Data
 SOD-Serial Output Data
Two more instructions are used to perform serial-parallel conversion
needed for serial I/O devices.
 SIM
 RIM

Address buffer and Address-Data buffer

The contents of the stack pointer and program counter are loaded into the
address buffer and address-data buffer. These buffers are then used to drive the
external address bus and address-data bus. As the memory and I/O chips are
connected to these buses, the CPU can exchange desired data to the memory and
I/O chips.
The address-data buffer is not only connected to the external data bus but
also to the internal data bus which consists of 8-bits. The address data buffer can
both send and receive data from internal data bus.

9
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Address bus and Data bus

We know that 8085 is an 8-bit microprocessor. So, the data bus present in
the microprocessor is also 8-bits wide. So, 8-bits of data can be transmitted
from or to the microprocessor. But 8085 processor requires 16-bit address bus
as the memory addresses are 16-bit wide. The 8 most significant bits of the
address are transmitted with the help of address bus and the 8 least significant
bits are transmitted with the help of multiplexed address/data bus. The eight- bit
data bus is multiplexed with the eight least significant bits of address bus. The
address/data bus is time multiplexed. This means for few microseconds, the 8
least significant bits of address are generated, while for next few seconds the
same pin generates the data. This is called Time multiplexing. But there are
situations where there is a need to transmit both data and address
simultaneously. For this purpose, a signal called ALE (address latch enables) is
used. ALE signal holds the obtained address in its latch for a long time until the
data is obtained and so when the microprocessor sends the data next time the
address is also available at the output latch. This technique is called
Address/Data demultiplexing.

Pin Diagram of 8085

The signals can be grouped as follows
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

10
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Fig. 1.3 Pin diagram of 8085

Power supply and Clock frequency signals

 Vcc + 5-volt power supply
 Vss Ground
 X1, X2: Crystal or R/C network or LC network connections to set the
frequency of internal clock generator. The frequency is internally
divided by two. Since the basic operating timing frequency is 3 MHz,
a 6 MHz crystal is connected externally.
 CLK (output) – Clock Output is used as the system clock for
peripheral and devices interfaced with the microprocessor.

Data Bus and Address Bus

AD0-AD7:-These are multiplexed address and data bus. So, it can be used to
carry the lower order 8-bit address as well as the data. Generally, these lines are
demultiplexed using the Latch. During the opcode fetch operation, in the first
clock cycle the lines deliver the lower order address bus A0-A7. In the
subsequent IO/M read or write it is used as data bus D0-D7. CPU can read or
write data through these lines. A8-A15:- These are address bus used to address
the memory location.

11
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Timing Diagrams
Timing diagram is the display of initiation of read/write and transfer of data
operations under the control of 3-status signals IO/M’, S1 and S0. Each machine
cycle is composed of many clock cycles. Since, the data and instructions, both are
stored in the memory, the µP performs fetch operation to read the instruction or
data and then execute the instruction. The 3-statussignals: IO / M’, S1 and S0 are
generated at the beginning of each machine cycle. The unique combination of
these 3-status signals identifies read or write operation and remain valid for the
duration of the cycle. Thus, time taken byany µP to execute one instruction is
calculated in terms of the clock period. The execution of instruction always
requires read and writes operations to transfer data to or from the µP and
memory or I/O devices. Each read/ write operation constitutes one machine
cycle. Each machine cycle consists of many clock periods/ cycles, called T-states.

Fig. 1.6 Machine cycle showing clock periods

Each and every operation inside the microprocessor is under the control of
the clock cycle. The clock signal determines the time taken by the microprocessor
to execute any instruction. State is defined as the time interval between 2-trailing
or leading edges of the clock. Machine cycle is the timerequired to transfer data
to or from memory or I/O devices.

The 8085 microprocessor has 5 basic machine cycles. They are

 Opcode fetch cycle (4T)
 Memory read cycle (3 T)
 Memory write cycle (3 T)
 I/O read cycle (3 T)
 I/O write cycle (3 T)
Processor Cycle
The function of the microprocessor is divided into fetch and execute cycle of
any instruction of a program. The program is nothing but number ofinstructions
stored in the memory in sequence. In the normal process of

12
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

operation, the microprocessor fetches (receives or reads) and executes one

instruction at a time in the sequence until it executes the halt (HLT) instruction.
Thus, an instruction cycle is defined as the time required to fetch and execute
an instruction. For executing any program, basically 2-steps are followed
sequentially with the help of clocks
 Fetch, and
 Execute.
The time taken by the µP in performing the fetch and execute operations
are called fetch and execute cycle. Thus, sum of the fetch and execute cycle is
called the instruction cycle as indicated in Fig.
Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)

Fig. 1.7 Processor cycle

The 1st machine cycle of any instruction is always an Opcode fetch cycle in
which the processor decides the nature of instruction. It is of at least 4-states. It
may go up to 6-states.
In the opcode fetch cycle, the processor comes to know the nature of the
instruction to be executed. The processor during (M1 cycle) puts the program
counter contents on the address bus and reads the opcode of the instruction
through read process. The T1, T2, and T3 clock cycles are used for the basic
memory read operation and the T4 clock and beyond are used for its
interpretation of the opcode. Based on these interpretations, the µP comes to
know the type of additional information/data needed for the execution of the
instruction and accordingly proceeds further for 1 or 2-machine cycle of memory
read and writes.
Instruction Fetch (FC)⇒An instruction of 1 or 2 or 3-bytes is extracted from
the memory locations during the fetch and stored in the µP’s instruction register.
Instruction Execute (EC)⇒The instruction is decoded and translated into
specific activities during the execution phase.

Opcode Fetch
The 1st step in communicating between the microprocessor and memory is
reading from the memory. This reading process is called opcode fetch. The

13
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

process of opcode fetch operation requires minimum 4-clock cycles T1, T2, T3,
and T4and is the 1st machine cycle (M1) of every instruction. In order to
differentiate between the data byte pertaining to an opcode or an address, the
machine cycle takes help of the status signal IO/ M, S1, and S0. The IO/ M= 0
indicates memory operation and S1 = S0 = 1 indicates Opcode fetch operation.
The opcode fetch machine cycle M1 consists of 4-states (T1, T2, T3, and T4).
The 1st 3-states are used for fetching (transferring) the byte from the memory
and the 4th-state is used to decode it.

Fig. Opcode Fetch

 During T4 the opcode is sent for decoding and decoded in T4.

 The execution is also completed in T4if the instruction is single
byte.
 More machine cycles are essential for 2- or 3-byte instructions.
The 1st machine cycleM1is meant for fetching the opcode. The
machine cycles M2and M3are required either to read/ writedata
or address from the memory or I/O devices.

14
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Interfacing I/O Devices

 Using I/O devices data can be transferred between the
microprocessor and the outside world.
 This can be done in groups of 8 bits using the entire data bus. This is
called parallel I/O.
 The other method is serial I/O where one bit is transferred at a time
using the SID and SOD pins on the Microprocessor.
 There are two ways to interface 8085 with I/O devices in parallel
data transfer mode:
 Memory Mapped IO
 IO Mapped IO

Memory mapped I/O

I/O devices are interfaced using address from memory space. That means
IO device address are part of addresses given to memory locations.8085 uses 16-
bit address to memory interfacing. So, any address between 0000H-FFFFH can
be given to each peripheral. But the addresses given to peripheral can’t be used
for memory. Memory control signals are used as read and write control signals
for peripherals. And all the operations that can be performed on memory can
also be performed on peripherals. No need of using IO instructionssuch as IN,
OUT.

IO mapped I/O
In this method separate address space is given to IO devices. Each IO device
is given an 8-bit address. Hence maximum 256 devices can be interfaced to the
processor. The address range for the IO devices is 00H-FFH. IO control signals
are used to perform read, write operations. For reading data from IO device or
writing data to IO device IN, OUT instructions needs to be used. Arithmetic and
logical operations can’t be performed directly on IO devices as in memory
mapped IO. IO devices can be interfaced, by using buffers for simple IO i.e. by
using address decoding circuit to enable buffer. For handshake IO or to interface
more peripherals ICs like 8255 peripheral programmable interface (PPI) can be
used.

15
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

The interfacing of output devices

Output devices are usually slow.
 Also, the output is usually expected to continue appearing on the
output device for a long period of time.
 Given that the data will only be present on the data lines for a very
short period (microseconds), it has to be latched externally.

 To do this the external latch should be enabled when the port’s

address is present on the address bus, the IO/M signal is set high and
WR is set low.
 The resulting signal would be active when the output device is being
accessed by the microprocessor.
 Decoding the address bus (for memory-mapped devices) follows the
same techniques discussed in interfacing memory.

Interfacing of Input Devices

 The basic concepts are similar to interfacing of output devices.
 The address lines are decoded to generate a signal that is active
when the particular port is being accessed.
 An IORD signal is generated by combining the IO/M and the RD
signals from the microprocessor.
 A tri-state buffer is used to connect the input device to the data bus.
 The control (Enable) for these buffers is connected to the result of
combining the address signal and the signal IORD.

16
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Applications of Microprocessor in General Life

There are a lot of applications of Microprocessor in general life. Some of the
applications are given below
 Mobile Phones
 Digital Watches
 Washing Machine
 Computer
 Lighting Control
 Traffic Control
 LAPTOP
 Modems
 Power Stations
 Television
 CD Player
 Multimeter
 CRO
 Wave generator
 More applications in medical

17
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

PART-2
8086 MICROPROCESSOR

Introduction
The 8086 is a 16-bit microprocessor intended to be used as the CPU in a
microcomputer. The term “16-bit” means that its arithmetic logic unit, internal
registers, and most of its instructions are designed to work 16-bit binary words.
It has 16-bit data bus and 20-bit address bus.
Words will be stored in two consecutive memory locations. If the first byte of
a word is at an even address, the 8086 can read the entire word in one operation.
If the first byte of the word is at an odd address, the 8086 will read the first byte
in one operation, and the second byte in another operation.

Features
 8086 is a 40 pin IC.
 It is a 16-bit processor.
 Its operating voltage is 5 volts.
 Its operating frequency is 5 MHz
 The total memory addressing capacity is 1MB (external).
 It has 16-bit data bus and 20-bit address bus.
 It has fourteen 16-bit registers.
 It has around 20000 transistors in its circuitry and it is made in
HMOS technology.
 Pipelining improves the performance of the processor so that
operation is faster.8086 uses two stage of pipelining.
 First is Fetch Stage and the second is Execute Stage.
 Fetch stage that prefetch upto 6 bytes of instructions stores them in
the queue.
 Execute stage that executes these instructions.
 Operates in two modes: 8086 operates in two modes:

Minimum Mode: A system with only one microprocessor.

Maximum Mode: A system with multiprocessor.

18
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

 8086 uses memory banks:The 8086 uses a memory banking system. It

means entire data is not stored sequentially in a single memory of 1 MB
but memory is divided into two banks of 512KB.
 Interrupts:8086 has 256 vectored interrupts.
 Multiplication and Division:8086 has a powerful instruction set. So
that it supports Multiply and Divide operation.

Pin Diagram
The 8086 signals can be categorized in three groups. The first are the signals
having common functions in minimum as well as maximum mode, the second are
the signals which have special functions in minimum mode and third are the
signals having special functions for maximum mode
The following signal description are common for both the minimum and
maximum modes.

AD15-AD0
These are the time multiplexed memory I/O address and data lines. Address
remains on the lines during T1 state, while the data is available on the data bus
during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock states of a
machine cycle. TW is a wait state. These lines are active high and float to a
tristate during interrupt acknowledge and local bus hold acknowledgecycles.

Fig. 3.1Pin Diagram

19
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address
and status lines. During T1, these are the most significant address lines or
memory operations. During I/O operations, these lines are low. During memory
or I/O operations, status information is available on those lines for T2, T3, TW
and T4.The status of the interrupt enable flag bit(displayed on S5) is updated at
the beginning of each clock cycle. The S4 and S3 combined, indicate which
segment register is presently being used for memory accesses as shown in the
following table.These lines float to tri-state off during the local bus hold
acknowledge. The status line S6 is always low(logical). The address bits are
separated from the status bits using latches controlled by the ALE signal.

Table 3.1 Segment Register Indication

S4 S3 Indication
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 Data

BHE/S7-Bus High Enable/Status: The bus high enable signal is used to

indicate the transfer of data over the higher order (D15-D8) data bus as shown
in the following table. It goes low for the data transfers over D15-D8 and is used
to derive chip selects of odd address memory bank or peripherals. BHE is low
during T1 for read, write and interrupt acknowledge cycles, when- ever a byte
is to be transferred on the higher byte of the data bus. The status information is
available during T2, T3 and T4. The signal is active low and is high-impedance
state during 'hold'. It is low during T1 for the first pulse of the interrupt
acknowledge cycle.

Table 3.2 Bus High Enable Indication

BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Upper byte from or to even address
1 1 None

RD-Read: Read signal, when low, indicates the peripherals that the
processor is performing a memory or I/O read operation. RD is active low and

20
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

shows the state for T2, T3, TW of any read cycle. The signal remains in high-
impedance during the 'hold acknowledge'.

Ready: This is the acknowledgement from the slow devices or memory that
they have completed the data transfer. The signal made available by the devices
is synchronized by the 8284A clock generator to provide ready input to the 8086.
The signal is active high.

INTR-lnterrupt Request: This is a level triggered input. This is sampled

during the last clock cycle of each instruction to determine the availability ofthe
request. If any interrupt request is pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked by resetting the interrupt
enable flag. This signal is active high and internally synchronized.

TEST: This input is examined by a 'WAIT' instruction. If the TEST input

goes low, execution will continue, else, the processor remains in an idle state. The
input is synchronized internally during each clock cycle on leading edge of clock.

NMI-Non-maskable Interrupt: This is an edge-triggered input which

causes a Type2 interrupt. The NMI is not maskable internally by software. A
transition from low to high initiates the interrupt response at the end of the
current instruction. This input is internally synchronized.

Reset: This input causes the processor to terminate the current activity and
start execution from FFFF0H. The signal is active high and must be active for at
least four clock cycles. It restarts execution when the RESET returns low. RESET
is also internally synchronized.

CLK-Clock Input: The clock input provides the basic timing for processor
operation and bus control activity. It’s an asymmetric square wave with 33%
duty cycle. The range of frequency for different 8086 versions is from 5MHz to
10MHz.

VCC : +5V power supply for the operation of the internal circuit. GND ground
for the internal circuit.

21
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

MN/MX: The logic level at this pin decides whether the processor is to
operate in either minimum (single processor) or maximum (multiprocessor)
mode.
The following pin functions are for the minimum mode operation of 8086.

M/IO -Memory/IO: This is a status line logically equivalent to S2 in

maximum mode. When it is low, it indicates the CPU is having an I/O operation,
and when it is high, it indicates that the CPU is having a memory operation. This
line becomes active in the previous T4 and remains active till final T4 of the
current cycle. It is in high-impedance state during local bus "hold acknowledge".

INTA -Interrupt Acknowledge: This signal is used as a read strobe for

interrupt acknowledge cycles. In other words, when it goes low, it means that the
processor has accepted the interrupt. It is active low during T2, T3 and TW of
each interrupt acknowledge cycle.

ALE-Address latch Enable: This output signal indicates the availability of

the valid address on the address/data lines, and is connected to latch enable
input of latches. This signal is active high and is never in high-impedance state.

DT /R -Data Transmit/Receive: This output is used to decide the direction

of data flow through the transceivers (bidirectional buffers). When the
processor sends out data, this signal is high and when the processor is receiving
data, this signal is low. Logically, this is equivalent to S1 in maximum mode. Its
timing is the same as M/I/O.

DEN-Data Enable This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transceivers (bidirectional buffers) to
separate the data from the multiplexed address/data signal. It is active from the
middle of T2 until the middle of T4 DEN is in high-impedance state during 'hold
acknowledge' cycle.

HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it

indicates to the processor that another master is requesting the bus access. The
processor, after receiving the HOLD request, issues the hold acknowledge signal
on HLDA pin, in the middle of the next clock cycle after completing the current
bus (instruction) cycle. At the same time, the processor floats the local bus and

22
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

control lines. When the processor detects the HOLD line low, it lowers the HLDA
signal. HOLD is an asynchronous input, and it should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle,
it will release the local bus during T 4 provided:
1. The request occurs on or before T 2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word (or
operating on an odd address).
3. The current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A Lock instruction is not being executed.
The following pin functions are applicable for maximum mode operation of
8086.

S2, S1, S0 -Status Lines: These are the status lines which reflect the type of
operation, being carried out by the processor. These become active during T4 of
the previous cycle and remain active during T1 and T2 of the current bus cycle.
The status lines return to passive state during T3 of the current bus cycle so that
they may again become active for the next bus cycle during T4. Any change in
these lines during T3 indicates the starting of a new cycle, and return to passive
state indicates end of the bus cycle. These status lines are encoded in the
following table.
Table 3.3 Status Lines Indication
S2 S1 S0 Indication
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive

Lock
This output pin indicates that other system bus masters will be prevented
from gaining the system bus, while the LOCK signal is low. The LOCK signal is
activated by the 'LOCK' prefix instruction and remains active until the
completion of the next instruction. This floats to tri-state off during "hold

23
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

acknowledge". When the CPU is executing a critical instruction, which requires

the system bus, the LOCK prefix instruction ensures that other processors
connected in the system will not gain the control of the bus. The 8086, while
executing the prefixed instruction, asserts the bus lock signal output, which may
be connected to an external bus controller.

QS1, QS0-Queue Status

These lines give information about the status of the code prefetch queue.
These are active during the CLK cycle after which the queue operation is
performed. These are encoded as shown in the following table.

Table 3.4 Queue Status Indication

Qs1 Qs0 Indication
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue

RQ/GT0, RQ/GT1-ReQuest/Grant: These pins are used by other local bus

masters, in maximum mode, to force the processor to release the local bus at
the end of the processor's current bus cycle. Each of the pins is bidirectional with
RQ/GT0 having higher priority than RQ/ GT1, RQ/GT pins have internal pull-up
resistors and may be left unconnected. The request! grant sequence is as
follows:
1. A pulse one clock wide from another bus master requests the bus
access to 8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide
from 8086 to the requesting master, indicates that the 8086 has
allowed the local bus to float and that it will enter the "hold
acknowledge" state at next clock cycle. The CPU's bus interface unit
is likely to be disconnected from the local bus of the system.
3. A one clock wide pulse from another master indicates to 8086 that
the 'hold' request is about to end and the 8086 may regain control of
the local bus at the next clock cycle. Thus, each master to master
exchange of the local bus is a sequence of 3 pulses. There must be at
least one dead clock cycle after each bus exchange. The request and
grant pulses are active low. For the bus requests those are received

24
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

while 8086 is performing memory or I/O cycle, the granting of the

bus is governed by the rules of HOLD, and HLDA in minimum mode.

Internal Block Diagram:

The 8086 CPU is divided into two independent functional parts, the bus
interface unit or BIU, and the execution unit or EU.

The Bus Interface Unit

The BIU handles all data and addresses on the buses for the execution unit
such as it sends out addresses, fetches instructions from memory, reads data
from ports and memory as well as writes data to ports and memory. In BIU there
are so many functional groups or parts these are as follows.

Instruction Queue
To increase the execution speed, BIU fetches as many as six instruction bytes
ahead to time from memory. The prefetched instruction bytes are held for the EU
in a first in first out group of registers called an instruction queue. When the EU
is ready for its next instruction, it simply reads the instruction from this
instruction queue. This is much faster than sending out an address to the system
memory and to send back the next instruction byte. Fetching the next instruction
while the current instruction executes is called pipelining.

Fig. Block Diagram

25
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Segment Registers
The BIU contains four 16-bit segment registers. They are: the extra segment
(ES) register, the code segment (CS) registers, the data segment (DS) registers,
and the stack segment (SS) registers. These segment registers are used to hold
the upper 16 bits of the starting address for each of the segments. The part of a
segment starting address stored in a segment register is often called the segment
base.
1. Code Segment (CS): The CS register is used for addressing a memory
location in the Code Segment of the memory, where the executable
program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data
are accessed in the
Data Segment by an offset address or the content of other register that
holds the offset address.
3. Stack Segment (SS): SS defined a section of memory to store addresses
and data while a subprogram executes.
4. Extra Segment (ES): ES is additional data segment that is used by some
of the string to hold the extra destination data.

Fig . Segment Register

Instruction Pointer (IP)
In the BIU, the next register, below the segment register is instruction
pointer. The instruction pointer (IP) holds the 16-bit address of the next code
byte within this code segment.

26
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

The Execution Unit

The execution unit (EU) tells the BIU where to fetch instructions or data from,
decodes instructions, and executes instructions. The functional parts of the
execution unit are control circuitry or system, instruction decoder, and
Arithmetic logic unit (ALU).Control circuitry to perform various internal
operations. A decoder in the EU translates instructions fetched from memory to
generate different internal or external control signals that required performing
the operation. The EU has a 16-bit ALU, which can perform arithmetic operations
such as add, subtract etc. and logical operations such as AND, OR, XOR, increment,
decrement etc.

Flag Register
A 16-bit flag register is a flip-flop which indicates some condition produced
by the execution of an instruction or controls certain operations of the EU. They
are modified automatically by CPU after mathematical operations. It has 9 flags
and they are divided into two categories:
1. Conditional Flags
2. Control Flags

Conditional Flags
Conditional flags represent result of last arithmetic or logical instructions.
 Carry Flag (CF): This flag will be set to one if the arithmetic
operation produces the carry in MSB position. It is also used in
multiple-precision arithmetic.
 Auxiliary Flag (AF): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4
– D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This
is not a general-purpose flag; it is used internally by the processor to
perform Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If
lower order 8-bits of the result contains even number of 1’s, the
Parity Flag is set to one and for odd number of 1’s, the Parity Flag is
reset i.e. zero.
 Zero Flag (ZF): It is set to one; if the result of arithmetic or logical
operation is zero else it is reset.
 Sign Flag (SF): In sign magnitude format the sign of number is
indicated by MSB bit. If the result of operation is negative, sign flag
is set to one.

27
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

 Overflow Flag (OF): It occurs when signed numbers are added or

subtracted. An OF indicates that the result has exceeded the capacity
of machine.

Control Flags
Control flags are intentionally set or reset to control certain operations of the
processor with specific instructions put in the program from the user. Control
flags are as follows:
1. Trap Flag (TF): It is used for single step control. It allows user to
execute one instruction of a program at a time for debugging. When
trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used
to allow/prohibit the interruption of a program. If it is set, the
maskable interrupt is enabled and if it is reset, the interrupt is
disabled.
3. Direction Flag (DF): It is used in string operation. If it is set, string
bytes are accessed from higher memory address to lower memory
address. When it is reset, the string bytes are accessed from lower
memory address to higher memory address.

Fig . Flag Register

General Purpose Registers

The EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL,
DH, and DL. These registers can be used individually for temporary storage of
8-bit data. The AL register is also called the accumulator. Certain pairs of these
general-purpose registers can be used together to store 16-bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL and DH and DL. These register
pairs are referred to the AX, BX, CX, and DX resp.

28
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Microprocessor and Microcontroller

1. AX Register: For 16-bit operations, AX is called the accumulator

register that stores operands for arithmetic operations.
2. BX Register: This register is mainly used as a base register. It holds
the starting base location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop
instruction to store loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O
instruction.

Stack Pointer Register

The stack pointer (SP) register contains the 16-bit offset from the start of the
segment to the memory location where a word was most recently stored on the
stack. The memory location where a word was most recently stored is called the
top of stack.

Other Pointer and Index Registers

The EU also contains a 16-bit source index (SI) register, base pointer (BP)
registers, and Destination Index (DI) registers. These three registers can be
mainly used for temporary storage of 16-bit data just like a general-purpose
register.

Min/Max Mode of Operation:

The microprocessors 8086 and 8088 can be configured to work in two
modes: The Minimum mode and the Maximum mode.
The Minimum mode is used for single processor system, where 8086/8088
directly generates all the necessary control signals.
The Maximum mode is designed for multiprocessor systems, where an
additional “Bus-controller” IC is required to generate the control signals. The
processors control the Bus controller using status-codes.

29
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Fig a. Minimum mode signals Fig b. Maximum mode signals

Interrupts
An interrupt is the method of processing the microprocessor by peripheral
device. An interrupt is used to cause a temporary halt in the execution of
program. Microprocessor responds to the interrupt with an interrupt service
routine, which is short program or subroutine that instructs the microprocessor
on how to handle the interrupt.
There are two basic type of interrupt, maskable and non-maskable, non-
maskable interrupt requires an immediate response by microprocessor, it
usually used for serious circumstances like power failure. A maskable interrupt
is an interrupt that the microprocessor can ignore depending upon some
predetermined upon some predetermined condition defined by status register.

Interrupt can divide to five groups:

1. Hardware interrupt
2. Non-maskable interrupt
3. Maskable interrupt
4. Software interrupt
5. Reset
Hardware, software and internal interrupt are service on priority basis. each
interrupt is given a different priority level by assign it a type number. Type 0
identifies the highest-priority and type 255 identifies the lowest- priority
interrupt.
The 8086 chips allow up to 256 vectored interrupts. This means that you can
have up to 256 different sources for an interrupt and the 80x86 will directly call
the service routine for that interrupt without any software processing. This is in
contrast to non-vectored interrupts that transfer control directly to a single
interrupt service routine, regardless of the interrupt source.
30
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

The 8086 provides a 256-entry interrupt vector table beginning at address

0:0 in memory. This is a 1K table containing 256 4-byte entries. Each entry in this
table contains a segmented address that points at the interrupt service routine
in memory. The lowest five types are dedicated to specific interrupts such as the
divide by zero interrupt and the non-maskable interrupt. The next
27 interrupt types, from 5 to 31 are reserved by Intel for use in future
microprocessors. The upper 224 interrupt types, from32 to 255, are available to
use for hardware and software interrupts.

Hardware Interrupt
The primary sources of interrupts, however, are the PCs timer chip,
keyboard, serial ports, parallel ports, disk drives, CMOS real-time clock, 4 mouse,
sound cards, and other peripheral devices. These devices connect to an Intel
8259A programmable interrupt controller (PIC) that prioritizes the interrupts
and interfaces with the 80x86 CPU. The 8259A chip adds considerable
complexity to the software that processes interrupts.

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt pin (NMI) which has
higher priority than the maskable interrupt request pin (INTR). A typical use
would be to activate a power failure routine. The NMI is edge-triggered on aLOW-
to-HIGH transition. The activation of this pin causes a type 2 interrupt. NMI is
required to have a duration in the HIGH state of greater than two CLK cycles, but
is not required to be synchronized to the clock. Any high-goingtransition of NMI
is latched on-chip and will be serviced at the end of thecurrent instruction or
between whole moves of a block-type instruction. Worst case response to NMI
would be for multiply, divide, and variable shift instructions. There is no
specification on the occurrence of the low-going edge; it may occur before,
during, or after the servicing of NMI. Another high-going edge triggers another
response if it occurs after the start of the NMI procedure. The signal must be free
of logical spikes in general and be free of bounces on the low-going edge to avoid
triggering extraneous responses.

Maskable Interrupt
Whenever an external signal activates the INTR pin, the microprocessor will
be interrupted only if interrupts are enabled using set interrupt Flag instruction.
If the interrupts are disabled using clear interrupt Flag instruction, the
microprocessor will not get interrupted even if INTR is activated. That is,

31
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

INTR can be masked. INTR is a non-vectored interrupt, which means, the 8086
does not know where to branch to service the interrupt. The 8086 has to be told
by an external device like a Programmable Interrupt controller regarding the
branch. Whenever the INTR pin is activated by an I/O port, if Interrupts are
enabled and NMI is not active at that time, the microprocessor finishes the
current instruction that is being executed and gives out a ‘0’ on INTA pin twice.
When INTA pin goes low for the first time, it asks the external device to get ready.
In response to the second INTA the microprocessor receives the 8 bits, say N,
from a programmable Interrupt controller. The action taken is as follows.
1. Complete the current instruction.
2. Activates INTA output, and receives type Number, say N
3. Flag register value, CS value of the return address & IP value of their
turn address are pushed on to the stack.
4. IP value is loaded from contents of word location N x 4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to 0.

At the end of the ISS, there will be an IRET instruction. This performspopping
off from the stack top to IP, CS and Flag registers. Finally, the register values
which are also saved on the stack at the start of ISS, are restored fromthe stack
and a return to the interrupted program takes place using the IRET instruction.

Software Interrupt
There are instructions in 8086 which cause an interrupt. They are
 INT instructions with type number specified.
 INT 3, Break Point Interrupt instruction.
 INTO, Interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these
instructions is executed a branch to an ISS takes place. Because their execution
results in a branch to an ISS, they are called interrupts. Software Interrupt
instructions can be used to test the working of the various Interrupt handlers-
For example, we can execute INTO instruction to execute type 0 ISS, without
really having to divide a number by 0. Similarly, we can execute INT 2 instruction
to test NMI ISS.

32
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

INT-Interrupt Instruction with Type number Specified

The mnemonic for this is INT. It is a 2-byte instruction. The first byte
provides the op-code and the second byte the Interrupt type number. Op-code
for this instruction is CDH. The execution of an INT instruction, say INTN, when N
is the value in the range 00H to FFH, results in the following:
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address
are pushedon to the stack.
3. IP is loaded from the contents of the word location N x 4.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus, a branch to the ISS take place. During the ISS, interrupt is disabled
because the Interrupt flag is reset to 0. At the end of the ISS, there will be an IRET
instruction. Thus, a return back to the interrupted program takes place with Flag
registers unchanged.

INT 3-Break Point Interrupt Instruction

When a break point is inserted, the system executes the instructions up to
the breakpoint, and then goes to the break point procedure. Unlike the single-
Step feature which stops execution after each instruction, the breakpoint feature
executes all the instructions up to the inserted breakpoint and then stops
execution. The mnemonic for the instruction is INT3. It is a 1-byte instruction
Op-code for this is CCH.

The execution of INT3 instruction results in the following.

1. Flag register value is pushed on to the Stack.
2. CS value of the return address and IP value of the return address are
pushed onto the Stack.
3. IP is loaded from the contents of the word location 3x4 = 0000CH.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus, a branch to the ISS takes place. During the ISS, interrupts are disabled
because Interrupt flag is reset to 0. At the end of the ISS, there will be an IRET
instruction to return back to the interrupted program. A break point interrupt
service procedure usually saves all the register contents on the Stack.Depending
upon the system, it may then send the register contents to the CRTdisplay and
wait for the next command from the user.

33
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

INTO - Interrupt on overflow instruction

The overflow flag, OF, will be set if the signed result of an arithmetic
operation on two signed numbers is too large to be represented in the
destination register or memory location. For example, if we add the 8-bit signed
number 01101100 and the 8- bit signed number 01010001, the signed result will
be 10111101. This is correct if we add unsigned binary numbers, but it is not the
correct signed result. There are two ways to detect and respond to an overflow
error in a program. One way is to put the jump if overflow instruction, JO,
immediately after the arithmetic instruction. If the overflow flag is Set, execution
will jump to the address specified in the JO instruction. At this address an error
routine may be put which respond to the overflow. The secondway is to put them
INTO instruction immediately after the arithmetic Instruction in the program.
The mnemonic for the instruction is INTO. It is a 1- byte instruction. The op-code
for this is CEH. It is a conditional interrupt instruction. Only if the overflow flag
is Set, a branch takes place to an interrupt handler whose interrupt type number
is 4. If the overflow flag is reset, the execution continues with the next instruction.
The execution of INTO results in the following.
1. Flag register values are pushed on to the Stack.
2. CS value of the return address and IP value of the return address
and IP value of the return address are pushed on to the stack.
3. IP is loaded from the contents of word location 4x4 = 00010H.
4. CS is loaded from the contents of next word location.
5. Interrupt flag and Trap flag are reset to 0.
Thus, a branch to ISS takes place. During the ISS, interrupts are disabled. At
the end of ISS, there will be an IRET instruction, returning back to the interrupted
program. Instructions in the ISS procedure performs the desired response to the
error condition.

Reset
Processor initialization or start up is accomplished with activation (HIGH)
of the RESET pin. The 8086 RESET is required to be HIGH for greater than 4
CLK cycles. The 8086 will terminate operations on the high-going edge of RESET
and will remain dormant as long as RESET is HIGH. The low-going transition of
RESET triggers an internal reset sequence for approximately 10 CLK cycles. After
this interval the 8086 operates normally beginning with the instruction in
absolute location FFFF0H.

34
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

Memory Read and Write Bus Cycles

During period T1,
 The 8086 outputs the 20-bit address of the memory location to be
accessed on its multiplexed address/data bus. BHE is also output
along with the address during T1.
 At the same time a pulse is also produced at ALE. The trailing edge or
the high level of this pulse is used to latch the address in external
circuitry.
 Signal M/IO is set to logic 1 and signal DT/R is set to the 0-logic level
and both are maintained throughout all four periods of the buscycle.
 Beginning with period T2,
 Status bits S3 through S6 are output on the upper four address bus
lines. This status information is maintained through periods T3 and
T4. On the other hand, address/data bus lines AD0 through AD7 are
put in the high-Z state during T2.
 Late in period T2, RD is switched to logic 0. This indicates to the
memory subsystem that a read cycle is in progress. DEN is switched
to logic 0 to enable external circuitry to allow the data to move from
memory onto the microprocessor's data bus.
During period T3,
 The memory must provide valid data during T3 and maintain it until
after the processor terminates the read operation. The data read by
the 8086 microprocessor can be carried over all 16 data bus lines 8.
During T4,
 The 8086 switches RD to the inactive 1 logic level to terminate the
read operation. DEN returns to its inactive logic level late during T4
to disable the external circuitry.
During period T1,
 The address along with BHE are output and latched with the ALE
pulse.
 M/IO is set to logic 1 to indicate a memory cycle.
 However, this time DT/R is switched to logic 1. This signals external
circuits that the 8086 is going to transmit data over the bus.
Beginning with period T2,

35
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

 WR is switched to logic 0 telling the memory subsystem that

a writeoperation is to follow.
 The 8086 puts the data on the bus late in T2 and maintains
the datavalid through T4. Data will be carried over all 16
data bus lines.
 DEN enables the external circuitry to provide a path for
data fromthe processor to the memory.

Fig: Min mode memory read bus cycle

Fig: Min mode memory write bus cycle

36
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

37
Downloaded by TEJASWINI VEERAVALLI ([email protected])
 lOMoARcPSD|49882446

38
Downloaded by TEJASWINI VEERAVALLI ([email protected])