The Fundamentals of LDO Design

and Application
A low dropout regulator (LDO) consists of a voltage reference, called the dropout voltage. For example, in a battery-powered
an error amplifier, a feedback voltage divider, and a series pass design using a lithium-ion cell connected to a 2.8 V LDO, the
element, usually a bipolar or CMOS transistor (see Figure 1). battery voltage can drop from 4.2 V (fully charged) to 3.0 V
Output current is controlled by the PMOS transistor, which (battery empty) and provide a constant 2.8 V output provided
in turn is controlled by the error amplifier. This amplifier the LDO’s dropout voltage is below 200 mV. In some systems
compares the reference voltage with the feedback voltage LDOs are used for postregulation. The LDO connects to the
from the output and amplifies the difference. If the feedback output of a high-efficiency switching regulator and provides
voltage is lower than the reference voltage, the gate of the noise filtering, as well as a constant and stable output voltage.
PMOS device is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage REVERSE POLARITY
ADP1740 PROTECTION
is higher than the reference voltage, the gate of the PMOS
device is pulled higher, allowing less current to pass and VIN VOUT
decreasing the output voltage. This is a closed-loop system
UVLO
based around two main poles, the internal pole of the error
amplifier/pass transistor and the external pole of the output
GND
capacitor’s equivalent series resistance (ESR). SHORT-CIRCUIT
AND THERMAL
PROTECTION SENSE
Analog Devices LDOs are designed to be stable over the
R1
specified operating temperature and voltage ranges when
PG 0.5V
the recommended capacitors are used. The ESR of the REF R2
output capacitor affects the stability of the LDO control PG
DETECT
loop. A minimum ESR of 1 Ω or less is recommended to 0.9𝛍A
ensure stability. The LDOs response to rapid changes in load SS
EN SHUTDOWN
current, i.e. the transient response, is also affected by output
capacitance. Using a larger value of output capacitor improves
the transient response of the LDO; however, it can increase Figure 2. ADP1740 internal block diagram.
the start-up time.
VBIAS Common Questions About LDOs

VIN VOUT
What are some key selection criteria used for selecting
PMOS
PASS TRANSISTOR an LDO?
Depending on your particular design your selection criteria
AMP may differ. However, as a general rule you should use the list
below in the order that they appear.

REFERENCE
• Input voltage range
• Output voltage, fixed or adjustable
Figure 1. An LDO provides the required output voltage regulation • Output accuracy over line, load, and temperature
from an input voltage with a low dropout (i.e. small difference
between VIN and VOUT ). • Load current requirement
• Dropout voltage
LDO regulators are used to derive lower output voltages from
a main supply or battery. The output voltage is ideally stable • Power supply rejection ratio (PSRR)
with line and load variations, immune to changes in ambient • Output noise
temperature, and stable over time. LDOs should have as low a • Quiescent current and shutdown current
difference between the input and output voltage as possible,

analog.com/power
Does the output bypass capacitor value affect LDO What causes an LDO’s output noise and how can it be
performance? reduced?
An LDO’s design is usually optimized for a specific value of An LDO’s internal voltage reference is the primary source
load bypass capacitor. Increasing the load capacitance above for output noise. It is usually specified in microvolts rms
the recommended value can improve load transient response. over a specific bandwidth, such as 25 μV rms from 1 kHz
However, when a larger output capacitor is chosen, the input to 100 kHz. This low level noise is much lower than the
bypass capacitor should be increased to match it. Note: the switching transients and harmonics from a switch mode
input and output capacitors should be placed as close as dc-to-dc converter. Some LDOs feature a bypass pin to filter
possible to the LDO. reference voltage noise with a capacitor to ground. Following
the data sheet specified input, output, and bypass capacitors
What types of capacitors should be used for input/output usually results in a unproblematic noise level.
bypass? Analog Devices, Inc.
Worldwide Headquarters
Any good quality ceramic capacitors can be used, as long as Do LDOs have a minimum load current requirement? Analog Devices, Inc.
they meet the minimum capacitance and maximum effective None of Analog Devices LDOs need a minimum load current. One Technology Way
series resistance (ESR) specifications listed on the LDO data However, there are many competitive LDOs on the market that do P.O. Box 9106
Norwood, MA 02062-9106
sheet. Ceramic capacitors using X5R or X7R dielectrics are require a minimum load, some needing as much as several mA.
U.S.A.
highly recommended as these have good temperature stability
What are some useful features to look for in selecting Tel: 781.329.4700
and a low voltage coefficient. (800.262.5643,
an LDO?
U.S.A. only)
Does LDO ground current vary with load current? • An enable input to control LDO turn-on and turn-off for Fax: 781.461.3113
Designs using a bipolar transistor for the pass element exhibit system power savings
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a large increase in ground current as output load increases, • Programmable soft-start to limit inrush current, control Europe Headquarters
reaching ~5% of load current. MOSFET based LDOs are more output voltage rise-time during startup, and enable voltage Analog Devices, Inc.
energy efficient as the ground current increase with load sequencing Wilhelm-Wagenfeld-Str. 6
is minimal. The ground current for MOSFET based LDOs is 80807 Munich
• Tracking feature, which allows the LDO output to follow an Germany
typically below 0.1% of full load.
external voltage rail or reference Tel: 49.89.76903.0
What is power supply rejection ratio (PSRR)? Fax: 49.89.76903.157
• A bypass pin that allows an external capacitor to reduce
Power supply rejection ratio specifies the ability of an LDO to output voltage noise and improve power supply rejection Analog Devices, Inc.
Japan Headquarters
prevent output voltage fluctuations when there are variations in • A power-good output that indicates when the output is in
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input voltage. PSRR is usually specified at a specific frequency, regulation New Pier Takeshiba
for example 60 dB rejection at 120 Hz. Battery-based systems • Thermal shutdown that turns the LDO off if its temperature South Tower Building
should employ LDOs that maintain high PSRR at low battery exceeds the specified level 1-16-1 Kaigan, Minato-ku,
voltages, i.e. with a low input-output voltage differential. Tokyo, 105-6891
• Current limit function to control the LDO’s output current and Japan
If the LDO is driven from a switching power supply, will the power dissipation Tel: 813.5402.8200
HF switching noise be rejected? Fax: 813.5402.1064

LDOs will reject input noise up to tens, even hundreds of kHz. Analog Devices, Inc.
High frequency (1 MHz and up) switching noise rejection is Southeast Asia
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primarily a function of the output bypass capacitor network; the
Analog Devices
LDO’s loop bandwidth is too low above 1 MHz to provide any 22/F One Corporate Avenue
noise reduction. The LDO forms an impedance divider with the 222 Hu Bin Road
pass element and the output capacitor network and load; this Shanghai, 200021
provides noise rejection at high frequency. China
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Fax: 86.21.2320.8222

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