E0007E

2024-08-29

Written Exam

Course name: Course code:

Allowed aids:
Graphing calculator, BETA, Physics Handbook, Fysika, Sedra Smith—
Microelectronic Circuits. Notes are allowed in the course literature. Four
single-page A4 of hand-written notes are also allowed as well as any number of
printed pages from the digital parts of Sedra Smith.

On-duty teacher:
Joakim Nilsson, 070-36 36 957

Number of copies: Number of pages: Project number:

Grade scale: No. of tasks: Total score:

Other information:
Tasks 1–7 may be answered on the same page. The remaining tasks should be
answered on separate pages. Use only one side per sheet of paper. Submit the
tasks in order. Do not submit the exam sheets. Do not use a red pen. Make
sure your handwriting is readable.

Page 1 / 10
 E0007E
2024-08-29

Part I
This part consists of 7 tasks. These tasks may be answered on the same page.
Each task gives a choice of several answers. Choose only one of the answers
for each task. No motivation for your choice is required.

Task 1 (2 credits)
Consider the circuit in the figure below. The diodes can be considered to
have forward voltage drop of 0.7 V. What is the voltage vout ?
10 V
1.0 V
100 mV

vout

10 kΩ

A. −600 mV

B. 0 V

C. 300 mV

D. 9.3 V

Page 2 / 10
 E0007E
2024-08-29

Task 2 (2 credits)
Consider the circuit in the figure below. The Zener diode has a Zener voltage
of 15 V. What is the voltage vout ?
22 V

4.0 kΩ

vout

3.0 kΩ

A. 0 V
B. 3.0 V
C. 7.0 V
D. 9.4 V
E. 15 V
F. 18 V
G. 22 V

Task 3 (2 credits)
Coupling capacitors connected between amplifier stages are used in order
to...
A. Coupling capacitors are not used for amplifiers.
B. Keep the variation of the supply voltage to a minimum.
C. Make it possible to set the DC levels of different amplifier stages
independent of each other.
D. Filter out high frequencies in the signal fed to the amplifier.

Page 3 / 10
 E0007E
2024-08-29

Task 4 (2 credits)
Consider the circuit in the figure below. Which of the following contributes
significantly to the high cutoff frequency fH for the gain |Gv | = |Vout /Vsig |?

Rout
Rin
Cout
Cin Vout

Vsig CS

A. Both capacitors Cin and Cout .

B. The capacitor CS .

C. The output resistance Rout seen at the amplifier output.

D. Internal paracitic capacitances of the transistor.

Page 4 / 10
 E0007E
2024-08-29

Task 5 (2 credits)
Consider the four amplifiers in the figures below. Assume the transistors
are biased in active mode with collector currents of IC = 1 mA. All resistors
have resistances of 10 kΩ, all transistors have betas of around 100, and all
capacitors are large. Which amplifier has the lowest output resistance, Rout ?

Rout
Rout Rin
Rin
Vout
Vout

Vsig Vsig
1) 2)

Rout

Rin
Iout
Rin
Rout
Isig
Vout
Vsig
3) 4)

A. No. 1

B. No. 2

C. No. 3

D. No. 4

Page 5 / 10
 E0007E
2024-08-29

Task 6 (2 credits)
Which of the conditions 1–5 are requirements for making the assumption of a
virtual short between the positive input (V + ) and the negative input (V − ) of
an op amp circuit?

1. The op amp is connected in a negative feedback circuit.

2. The op amp is connected in a positive feedback circuit.

3. The op amp is not connected in a feedback circuit.

4. The op amp is saturated.

5. The op amp is not saturated.

Select one of answers A–F.

A. 1 and 4

B. 1 and 5

C. 2 and 4

D. 2 and 5

E. 3 and 4

F. 3 and 5

Page 6 / 10
 E0007E
2024-08-29

Task 7 (2 credits)
A 1 V sinusoid is fed into the input of an operational amplifier in the non-
inverting configuration with a gain of 10 V/V. The input and output voltages
are shown in the plot below. As can be seen from the plot, the output voltage
is not what was desired. What modification to the circuit could be made to
remedy this problem?

10 vin
vout
5
Voltage [V]

−5

−10
0 5 10 15 20
Time [µs]

A. Replace the op amp with another op amp that has a higher bandwidth

B. Add big decoupling capacitors

C. Increase the gain of the circuit by adjusting the resistor values

D. Increase the supply voltage (assuming the op amp is rated for a higher
supply voltage)

E. Replace the op amp with another op amp that has a higher slew rate

F. AC-couple the input signal

Page 7 / 10
 E0007E
2024-08-29

Part II
This part consists of 3 tasks. For each of these, a full and clear solution is
required. Motivate approximations and assumptions that you make and make
sure to verify said assumptions.
When solving a subtask, if you do not manage to calculate all numerical
values required for a later subtask, assume reasonable values of your choice
for the quantities in question, and clearly state that you are doing so.
In order for this part to yield any credits, at least 8 credits must have
been awarded for Part I.

Task 8 (3 credits)
Using only NMOS and PMOS transistors, design a logic cicuit that realizes
the following logic function:

Y = A or B.

The function is also tabulated in the table below for all possible input values.
A and B are input signal voltages, while Y is the output signal voltage. In
the table, 0 represents the logic low voltage level, while 1 represents the logic
high voltage level. You are allowed to place several gates in cascade. The
circuit should work for a supply voltage of 0.9 V and a threshold voltage for
both transistor types of 0.5 V.

AB Y
00 0
01 1
10 1
11 1

Page 8 / 10
 E0007E
2024-08-29

Task 9 (7 credits)
Consider the amplifier below. The transistor has current gain β = 50 and
Early voltage VA = 120 V.

a). Calculate values for the bias voltages VB , VE , and VC as well as the bias
currents IB , IE , and IC . (2 credits)

b). Draw the full small-signal schematic, including ro . Use this to calculate
values for the midband gain Gv = vout /vsig , the amplifier input resistance
Rin , and the amplifier output resistance Rout . (2 credits)

c). Explain what the purpose of the 3.3 kΩ resistor RE is. Given that the
values of the three remaining biasing resistors can be changed, does any
problem arise if RE were to be set to 0 Ω? (1 credit)

10 V 10 V
Rout
Rin
33 kΩ 1.0 kΩ
∞
∞ vout
1.0 kΩ

vsig 22 kΩ 3.3 kΩ ∞ 10 kΩ

Page 9 / 10
 E0007E
2024-08-29

Task 10 (6 credits)
Consider the amplifier below. The transistor’s transconductance parameter is
given as kn = 60 mA/V2 , and its threshold voltage as Vt = 2.0 V. You may
ignore the transistor output resistance ro for this task.
You are given exactly one large capacitor which you are allowed to attach
between any two nodes in the circuit below. Utilize this capacitor and select
values for RG1 , RG2 , RS and RD in order to achieve bias current ID of around
3.0 mA and a midband gain |Gv | = |Vout /Vsig | of at least 40 V/V.

12 V

Rout
Rin RD
∞
∞ Vout
1.5 kΩ

Vsig 200 kΩ 50 kΩ
RS

−12 V

Page 10 / 10