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Enhancing Wireless Communication using Software-Defined Radio

Architecture

Article · October 2012

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International Journal of Research and Reviews in Computer Science (IJRRCS) 1841
Vol. 3, No. 5, October 2012, ISSN: 2079-2557
© Science Academy Publisher, United Kingdom
www.sciacademypublisher.com/journals/index.php/IJRRCS

Enhancing Wireless Communication using Software-Defined

Radio Architecture

James Agajo1, Idigo Victor Eze2, and Nosiri Onyebuchi3

1
Federal Polytechnic Auchi Department of Electrical/ Electronics, Edo State Nigeria
2
Nnamdi Azikiwe University Awka Department of Electronics and Computer Engineering, Anambra State, Nigeria
3
Federal University of Technology Owerri Department of Electrical/ Electronics, Nigeria
Email: [email protected] [email protected], [email protected]

Abstract – Software-Defined Radio (SDR) is a rapidly evolving technology that is receiving enormous recognition and
generating widespread interest in the telecommunication industry. It facilitates implementation of the physical and link layer
protocols-in effect entire wireless system,-in software. A side effect of the rapid growth of wireless system technology in the
recent past is an excess of wireless system standards. Therefore the SDR concept is emerging as a pragmatic solution. It aims
to build flexible radio systems which are multiple-Defined Radio architectures as a prototyping, tool for wireless baseband
signal processor implementations is explored. Signal processing implementations is explored. Signal processing architectures
and algorithms for the physical layer of IEEE 802.11g- the latest release from the popular IEEE family of wireless standards-is
developed and simulated in Matlab and Simulink. The integrity of the developed model is verified by measurement of the
constellation versus signal to noise ratio (SNR) and Bit error Rate (BER) versus SNR graph, which are reported. The IEEE
802.11g PHY model is then translated to software (C++) with the aid of Real-Time workshop software tool. The generated
codes can then be targeted on a Digital Signal Processor (DSP) or other programmable hardware modules.
Keywords – SDR, OFDM, DSP, Modulation

1. Introduction device which has the ability to run different wireless

standards. This in turn poses no mean challenges at the
1.1. Background different layers of the network, right from the wireless
The astronomical growth of wireless communication in interface (radio) to the application level. The devices would
the last two decades has brought with it new challenges. As have to monitor the different RF signals on different wireless
researchers and vendors seek for higher-rate data support in interfaces and switch to standards appropriately. Also, the
wireless infrastructure, several innovations for implementing size of the devices would have to be as limited as possible.
modulation/demodulation Approaching the above challenges by the present way of
implementation where separate hardware resources are
allocated for each of the standards would make the “universal
access devices” bulky and inefficient. Moreover,
upgradeability when new standards emerge would be
impossible. Software-defined radio (SDR) is emerging as a
pragmatic solution to this. SDR is simply a technology where
all the seven layers of a wireless network (from Open System
Interconnection - OSI - model point of view) are
implemented in software.In the traditional radio system, the
upper layers - Application, Presentation, and Session - are
and encoding/decoding emerge and these ultimately result in almost always implemented in software; lower layers are a
a proliferation of air interface standards (AIS). This poses combination of hardware and software, except the physical
great challenges to all stakeholders: equipment (PHY) layer which is mostly hardware [1]. But in software-
manufacturers, regulators, service providers, users, etc. defined radio, layers 7 down to 1 are all implemented in
Responses to the above challenges and market pressures software.
are forcing the convergence of wireless standards in one Programmable processing devices, like: Digital Signal
access device. This convergence would produce a seamless, Processors (DSPs), Field Programmable Gate Arrays
ubiquitous wireless network with voice, video, multimedia (FPGAs), General Purpose Processors (GPPs),
and broadband data services traveling across multiple Programmable system on chip (SOC) or other application-
wireless interfaces providing anytime, anywhere specific processors [2] [3], are used to run the embedded
communications to its users. Such technology would enable software. The use of these technologies allows new wireless
users to always be connected to a network through a single features and capabilities to be added to existing radio systems
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1842

without requiring new hardware. In addition, multiple using Direct Sequence (DS) and Frequency Hopped (FH)
wireless standards can be implemented on the same device. spread spectrum (SS) techniques. The third PHY facilitates
communication over infrared links. As the demand for data
2. IEEE 802.11 Physical layer rates continued to increase, several new PHY layer
The physical (PHY) layer is the lowest layer (ISO layer 1) specifications have been added. These PHY extensions to the
specification of the IEEE 802.11 standard. It is the logical original standard are designated by a letter following the
layer in charge of defining the physical details of the 802.11 name, such as 802.11a, 802.11b, 802.11g or 802.11n.
network, such as electrical power transmitted, modulation The letter suffix represents the task group that defines the
scheme, etc [22]. The original 802.11 standard specifies three extension to the standard [23]. Table 2.1 briefly summarizes
PHY layers. Two of the PHYs facilitate communications in 802.11 PHY extensions [12][1][13].
the 2.4GHz Industrial Scientific and Medical (ISM) band

Table 2.1. IEEE 802.11 PHY specifications

IEEE Release Technique Band Modulation Max Rate Range Range
(Mbps) (inside) (Outside)
(M) (M)
802.11 1997 FHSS 2.4GHz FSK 2 ≈20 ≈100
DSSS 2.4GHz PSK 2 ≈20 ≈100
Infrared PPM 2
802.11a 1999 OFDM 5.7GHz PSK or QAM 54 ≈35 ≈120
802.11b 1999 DSSS 2.4GHz PSK 11 ≈38 ≈140
802.11g 2003 DSSS, OFDM 2.4GHz PSK,QAM 54 ≈38 ≈140
802.11n Expected MIMO 2.4, 5.7GHz 248 ≈70 ≈250
2009

Figure 1. Relationship between physical and data link layers.

is as presented in figure 2 [10]. Chipsets for implementing

2.1. Basics of IEEE 802.11g standard
this have been available. Coming chapters will be dedicated
The IEEE 802.11g WLAN standard can be thought of as to reducing the hardware implementation to software
an intersection between the 802.11b and 802.11a standards. implementation using DSP, FPGA or other suitable
Like 802.11b, it operates in the same 2.4GHz portion of the reprogrammable platforms.
radio frequency spectrum that allows for license-free
operation on a nearly worldwide basis. 802.11g also 2.2. Review of Software Defined Radio Architecture.
implements DSSS PHY and is also limited to the same three Software defined radio architectures have continuously
non-overlapping channels as 802.11b. An important evolved since the inception of flexible radio concept. New
mandatory requirement of 802.11g is full backward advances in digital components proceed to modify even the
compatibility with 802.11b, which both provides investment latest designs. An ideal software defined radio (SDR) is
protection for the installed base of 802.11b clients and entirely implemented digitally, so that it can be completely
extracts a substantial performance penalty when operating in reconfigurable via software. This section explains the generic
this mode [1]. Like 802.11a, 802.11g uses Orthogonal SDR architecture that would permit implementation of IEEE
Frequency Division Multiplexing (OFDM). When coupled 802.11g and other WLAN protocols on a single design.
with various modulation types, 802.11g (like 802.11a) is As shown in fig. 1, a digital radio system consists of three
capable of supporting much higher data rates than 802.11b. main functional blocks: RF section, IF section and baseband
802.11g supports a large set of data rates, in fact all the rates section. The RF section consists of essentially analogue
supported by both 802.11a and 802.11b, as shown in table 2.2 hardware modules while IF and baseband sections contain
below [5]. digital hardware in a conventional digital hardware radio
Implementation block diagram of IEEE 802.11g baseband system.
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1843

Table 2.2. 802.11g data rates, transmission types and modulation schemes. Implementation block
Data Rate (Mbps) Transmission type Modulation scheme
54 OFDM 64QAM
48 OFDM 64QAM
36 OFDM 16QAM
24 OFDM 16QAM
18 OFDM QPSK
12 OFDM QPSK
11 DSSS CCK
9 OFDM BPSK
6 OFDM BPSK
5.5 DSSS QPSK, DQPSK
2 DSSS QPSK
1 DSSS BPSK

Antenna
Rx ADC DDC

RF Front‐ Base band

end
Processing
Tx DAC DUC

Figure 2. Block diagram of a generic digital transceiver [18][29].

As shown in figure. 2 , a digital radio system consists of systems, depending on the speed gap between the ADC/DAC
three main functional blocks: RF section, IF section and and DSP.
baseband section. The RF section consists of essentially
analogue hardware modules while IF and baseband sections 2.5. Simulation and Prototyping.
contain digital hardware in a conventional digital hardware The purpose of simulation and prototyping is to develop
radio system. and refine new ideas. The simulation environment offers the
designer a flexible and powerful environment on the
2.3. Analogue/Digital Conversion. computer. In simulation, communication system parameters
ADC and DAC are critical blocks as they are the interface like signal to noise ratio (SNR), modulation types and other
between the analogue and digital domains. They are largely modeling parameters can be clearly specified and easily
responsible for MODEM (modulation/demodulation) changed. The designer has more freedom in exploring the
performance and are subject to many constraints. Signal to design space as the simulation environment allows design of
noise ratio (SNR) is linked to converter resolution by the algorithms without the constraints of real-time execution. In
following equation [18]: contrast, the prototyping environment connects the design to
the real world. Test data is presented to the system from an
SNRAD = 1.76 + 6.02b + 10log (2BW/Fsampling) 2.1
uncontrolled environment using hardware interfaces such as
where b is the resolution in bits, Fsampling is the sampling analog to digital converters which present data of fixed
frequency and BW the bandwidth of interest. The width. The designer is restricted with limited hardware
performance of ADC/DAC is very critical to realization of resources and the timing and power consumption
any software defined radio. The higher the bandwidth it can requirements. These two are rarely used together in the
handle, the closer it can be placed to the antenna and the design and development process. Instead the design is
more ideal the SDR becomes. An ideal SDR has the developed as a two-step process. As a first step, new
ADC/DAC immediately following the antenna, thus algorithms are developed based on simulation results. The
eliminating the RF front-end. description of the algorithm is used to develop a prototype in
the second step.
2.4. Digital Down/Up Conversion.
Digital Down/Up Conversion (DDC/DUC) is a 2.6. Simulation and prototyping environments.
fundamental part of the communication system. Digital radio Simulation and prototyping of WLAN systems involves
have fast A/D,D/A converters delivering vast amount of data, development and integration of several computationally
but in many cases, the signal of interest is a small portion of intensive algorithms to enable different features required by
that bandwidth.DDC acts as a buffer bridging the speed gap these systems. The designer is faced with two important
between the ADC and Digital signal processor on the receive problems. First, simulation of communication systems
side while DUC does same on the transmit side. It must be involves block diagrams and mathematical equations while
understood that DDC/DUC may not be necessary in some prototyping hardware is programmed in C, C++, assembly or
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1844

HDL. Second, simulations often run on a host computer, this is left for future work.
while prototypes run on hardware and the powerful features
of simulation cannot be combined with the real-time 2.7. Use of Constellation Diagram in System Performance
constraints of the prototype hardware. Analysis
Each algorithm used in the simulation has to be tested Some properties of a modulation scheme can be inferred
independently before being integrated into a communication from its constellation diagram. The bandwidth occupied by
system. Interconnection of different algorithm blocks must be the modulation signals decreases as the number of signal
tested to ensure proper operation with neighboring blocks. points/dimension increases. Hence if a modulation scheme
The resulting block diagram must be translated into a has a constellation that is densely packed, it is more
program suitable to execute on the prototype hardware. bandwidth-efficient than the modulation scheme with a
Mathematical equations are used in algorithm creation. A sparsely packed constellation. The probability of bit error is
digital signal processor is typically used in prototyping proportional to the distance between the closest points in the
communication systems which require assembly language or constellation. The effects of signal corruption on
C programming language to generate an executable routine. constellation diagram are as summarized below.
Both simulation and prototyping are inherent in a) Gaussian noise shows as fuzzy constellation points;
communication system design, with initial design entry done b) Non-coherent single frequency interference shows as
on the host and final testing done on the prototyping circular constellation points;
hardware. c) Phase noise shows as rotationally spreading
In a block based system level design, each block is constellation points;
represented by an equation, which specifies the algorithm d) Amplitude compression causes the corner points to
implemented by that block. The proper operation of move towards the center.
individual blocks and the entire system is verified by In this simulation, an instrument called Discrete Time
simulation. The system is then translated into C or HDL and Scatter Plot scope is employed to relay the constellation
compiled to run on DSP or FPGA. The main simulation diagram of the transmitted and received signals.
environments employed in this thesis are Matlab and
Simulink. The add-on tool, Real Time Workshop, was then
employed for automatic code generation. The prototyping
will involve DSP and other hardware and software tools, but

Figure 3. Use of Constellation Diagram in System Performance Analysis.

J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1845

Figure 3. 64QAM Modulated Signal Constellation on Discrete Time Scatter Plot Scope.

3. System Design
2.8. Automatic code generation with Real-Time Workshop.
Real-Time workshop generates and executes stand-alone 3.1. IEEE 802.11g Physical layer services
C code for developing and testing algorithms modeled in IEEE 802.11g PHY offers information transfer services to
Simulink and embedded Matlab code. The resulting code can the Data link control (DLC). For this purpose, it provides for
be used for many real-time and non-real-time applications, functions to map different DLC Protocol Data Unit (PDU)
including simulation acceleration, rapid prototyping and trains into framing formats, called PHY bursts, appropriate
hardware-in-the loop testing. The generated code can be for transmitting and receiving management. IEEE 802.11g
tuned and monitored using simulink blocks and built-in PHY layer was conceived to offer link-adaptive data rates of
analysis capabilities, or run and interact with the code outside up to 54Mbps using Orthogonal Frequency Division
the Matlab and simulink environment. Multiplexing (OFDM) in the 2.4GHz ISM band. For
Key features of Real-Time workshop include: backward compatibility with the very popular IEEE 802.11b
• Generates ANSI C and C++ code and executables for (Wi-Fi), it also incorporates High Rate Direct Sequence
discrete, continuous or hybrid simulink models; Spread Spectrum (HR-DSSS) technique for rates up to
• Uses model blocks to incrementally generate and 11Mbps . Therefore PHY layer design of IEEE 802.11g
build code for large applications; involves a parallel design of both OFDM and DSSS
• Supports simulink data dictionary features for integer, transmitters and receivers and their appropriate management
floating point and fixed point data; logic.
• Generates code for single-rate, multirate and IEEE 802.11g PHY Consist of two functions:
asynchronous models; • Physical layer convergence function; Supported by
Supports single-tasking and multitasking operating Physical Layer Convergence Procedure (PLCP) that
systems and bare-board (no operating system) environments; defines method of mapping MAC sub layer Protocol
• Performs code optimizations that improve code Data Units (MPDU) into frame suitable for sending
execution speed; and receiving user data and management information.
• Provides capabilities for code customization and Also it enables MAC to operate at minimum
legacy code generation; dependence on Physical media by simplifying PHY
• The generated code can be tuned and monitored service interface to MAC services.
within or outside Simulink. • Physical Media Dependent (PMD) function that
produces methods for transmitting and receiving data
through the wireless medium.
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1846

3.2. DSSS Subsystem Design b) Generate the SIGNAL field bits, coding and
IEEE 802.11g PHY DSSS subsystem is the same as IEEE interleaving SIGNAL field bits, and map them into
802.11b PHY. It is based on the principle of using codes to frequency domain, insert pilots and transform into
spread a baseband signal over a wider bandwidth, similar to time domain;
what is obtainable in Code Division Multiple Access c) Prepend the SERVICE field, and add pad bits to the
(CDMA) systems. It supports four data rates: 1Mbps and octet stream and form the DATA;
2Mbps (Low-Rate DSSS); 5.5Mbps and 11Mbps (High-Rate d) Scramble and encode the DATA using convolutional
DSSS). It consists of two major functions: spreading and encoding and puncture to get higher rates and map
modulation. Other (ancillary) functions in the subsystem, like them into complex BPSK, QPSK, 16-QAM or 64-
Data Scrambling/Descrambling, Filtering, etc., have to do QAM symbols followed by pilot insertion;
with error management for better received data integrity. The e) Transform from frequency domain to time domain and
receiver performs the reverse of the functions of the add a cyclic prefix and concatenate the OFDM
transmitter. symbols into a single time-domain signal.
Thus, an OFDM transmitter block diagram is as in
3.3. OFDM Subsystem Design figure.3.1 below [26] [18]
The IEEE 802.11g also specifies an OFDM PHY that The tasks of the physical layer blocks on the transmitter
splits an information signal across 52 separate Sub-carriers to side (fig. 4.6) will be discussed in detail in the following
provide transmission of data at rates of 6, 9, 12, 18, 24, 36, sections. We will see by “reverse engineering” why certain
48 or 54Mbps. In this mode, a pseudo binary sequence is sent choices are made in the physical layer of IEEE 802.11g
through the pilot sub- channels to prevent the generation of system. This gives useful insight in the system for designing
spectral lines. The remaining 48 Subcarriers provide separate an IEEE 802.11g receiver.
wireless pathways for sending the information in a parallel
fashion [26]. 3.6. Forward Error Correction (FEC) Coding
Forward error Coding, or Channel Coding, is a method of
3.4. OFDM Signal Representation adding redundancy to the sent information so that it can be
In an OFDM System, data is carried on multiple sub- transmitted over a noisy channel, and subsequently be
carriers. The modulation of sub-carriers is done directly in checked and corrected for errors that occurred in the
the frequency domain using complex multiplication; the transmission. In IEEE 802.11g, convolution coding is used.
resulting data are transformed into the time domain using the As earlier stated in Chapter 2, IEEE 802.11g operates a link-
IFFT at the transmitter and transformed back to frequency adaptive rate up to 54Mbps. In the same way, the code rate
domain using the FFT at the receiver. The number of points also varies. The code rate is defined as [17]
of the IFFT/FFT used in a system depends on the number of Input bit rate
sub-carriers used [18]. In 802.11g system, the number of sub- RC = 3.3
Output bit rate
carriers used is 52, which translates to using a 64-point
IFFT/FFT. The transmitter and receiver decide per transmission burst
The discrete-time representation of the signal using N what bit rate is actually used, depending on the link (channel)
sub-carriers is given by the equation [18]: characteristics. Table 4.4 [26] summarizes these.
Table 3.1. IEEE 802.11g Coding
N / 2 −1
X (n) = 1 / N ∑ X ( k )e ej2ðK/Nn
Data
Rate
Modulation Coding
Rate
Coded
Bits per
Coded
bits per
Data
bits per
K =N / 2
3.1
(Mbps) (Rc) Subcarrier OFDM OFDM
where X (k) is the complex modulation vector and n Є [-N/2, Symbol Symbol
6 BPSK ½ 1 48 24
N/2]. 9 BPSK ¾ 1 48 36
At the receiver side, the data is recovered by performing 12 QPSK ½ 2 96 48
an FFT on the received signal, i.e. 18 QPSK ¾ 2 96 72
24 16-QAM ½ 4 192 96
N / 2 −1 36 16-QAM ¾ 4 192 144
X (n) = 1 / N ∑ X ( k )e ej2ðK/Nn
48 16-QAM 2/3 6 288 192
K =N / 2
3.2 54 64-QAM ¾ 6 288 216

where kЄ [-N/2, N/2]. Convolutional Codes are commonly specified by three

parameters: n, k and m, where n is the number of output bits,
k is the number of input bits and m is the number of memory
registers [37].

Figure 4. OFDM Transmitter block diagram.

3.5. OFDM Transmitter Design.

The encoding of data into OFDM signals is as follows
[18]:
a) Generate the short training sequence and long training Figure 4. Convolutional Encoder [17].
sequence;
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1847

3.7. Puncturing Convolution Codes

Puncturing is a very useful technique to generate 4. System Implementation
additional rates from a single convolutional code. The basic Having explored the design details of IEEE 802.11g PHY
idea behind puncturing is not to transmit some of the output layer in the last chapter, this chapter presents the
bits from the convolutional encoder, thus increasing the rate implementation of these functional entities for the SDR
of the codes. This increase in the rate decreases the free project. In this work, a three-step implementation approach is
distance of the code, but usually the resulting free distance is employed, which includes:
very close to the optimum one that is achieved by specifically • Creating a graphical model of the system using
designing a convolutional code for the punctured rate. The essentially Digital Signal Processing (DSP) and
receiver inserts dummy bits to replace the punctured bits in communication Blocksets in Matlab with the aid of
the receiver, hence only one encoder/decoder pair is needed Simulink model editor;
to generate several different code rates. The encoder for a • Performance evaluation of the simulated model;
punctured code can be fabricated using the original low-rate • Generation of the software codes.
convolutional encoder followed by a bit selector which As earlier stated, IEEE 802.11g PHY consists of OFDM
deletes specific code bits according to a given rule. and DSSS subsystems. OFDM is the major one, while DSSS
The puncture pattern is specified by the puncture vector mode is only switched when the system is in any
parameter in the mask. The puncture vector is a binary environment that has IEEE 802.11b node or access point.
column vector. A 1 indicates that the bit in the corresponding Since the major decision regarding the mode that the PHY
position of the input vector is sent to the output vector, while operates is taken at the data link layer, which is outside the
a 0 indicates that the bit is removed. scope of this project, the two subsystems are implemented
To create a rate ¾ code from the rate ½, constraint length separately.
7 convolutional code, the optimal puncture vector is [1 1 0 1
1 0] ` (where the “` “after the vector indicates the transpose). 4.1. Modeling of IEEE 802.11g OFDM PHY
Bits in positions 3 and 6 are removed. Now for every 3 bits of The model depicts the time-independent mathematical
input, the punctured code generates 4 bits of output (as relationships between the system’s inputs, state and outputs
opposed to the 6 bits produced before puncturing). This of various systems physical layer functional entities.
makes the rate ¾. Simulink model editor offers a good environment for
achieving this. The different functional entities (blocks) are
3.8. Data Interleaving
sourced from their respective blocksets. Those that cannot be
Interleaving aims to distribute transmitted bits in time or sourced are created by defining the inputs, outputs and
frequency or both to achieve desirable bit error distribution appropriate mathematical relationships. The set parameters
after demodulation. The interleaver decorrelates the data and for all the functional blocks are as generated at the design
spreads adjacent data over many subcarriers. All encoded bits stage in section 4. Table 4.1 below provides a summary of
are interleaved by a block interleaver with a block size the general parameters for the OFDM.
corresponding to the number of bits in a single OFDM For the purpose of simulation, use is made of a Bernouli
symbol, NCBPS (288) [38]. The interleaver is defined by a Binary Generator. This block generates random binary
two-step permutation: numbers using Bernouli distribution. 216 samples per time
• Let k be the index of bits at the input, let i be the bit are used based on the standard, at 54Mbps (Table 4.2 refers).
index after this permutation and let NBPSC be the
number of bits mapped per OFDM subcarrier. The Table 4.1. Global Parameters.
first permutation is given by [17] Parameters Value
Nsd: number of data subcarriers 48
i = NBPSC (k mod 16) /16 + floor (k/1 (3.4)
Nsp: number of pilot subcarriers 4
With k = 0, 1 … NBPSC-1 Nfft: number of FFT subcarriers 64
Ncyclic: cyclic prefix 16
• Let i be the bit index after the first permutation and let Viterbi Depth: Tradeback depth in the 34
j be the index after this permutation. The second viterbi decoder
permutation is given by OFDMSymbolDuration: Duration of 4e-006
one OFDM symbol
j = S floor(s/i) + [I + NBPSC – floor (16i/NBPSC) mod S](3.5) Puncture Vector [110110]

With i = 0, 1 … NBPSC-1 and S = max (NBPSC/2, 1).

General
Convolutional Matrix OFDM
Bernoulli Puncture Block Rectangular Normalize 1
Encoder Interleaver Transmitter
Binary Interleaver QAM Tx Signal 1
Bernoulli Binary Puncture Rectangular QAM
Convolutional Matrix General Block
Generator Interleaver Interleaver Modulator
Encoder
Baseband

Figure 5. OFDM transmitter Model.

J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1848

Figure 6. OFDM Transmitter block details.

4.2. OFDM Transmitter

OFDM transmitter functional Model is as presented in
figure 5 below. The scrambler is conspicuously missing in
the model because the data source for this simulation makes
that unnecessary. However, this is only for the purpose of
simulation. Actual transmitter incorporates this
Figure 9. OFDM Receiver block details.

4.4. Transmission Channel Model Implementation

Since no system transmits data perfectly, in this modeling
Bernoulli
process of IEEE 802.11g OFDM PHY, the effect of
Binary imperfections of the transmission channel is taken care of by
using the Additive White Gaussian Noise (AWGN) channel
Bernoulli Binary block. When the input signal is real, this block adds a real
Generator
Gaussian noise and produces a real output signal, likewise, it
Figure 7. Bernouli Binary Generator. The complete model (IEEE 802.11g OFDM PHY) is then
generated by combining as block.
4.3. OFDM Receiver
This block is very important in assessing the performance
The functional Model of OFDM receiver is as presented of the system under various noise levels and other
in figure 6. The receiver functions to reverse the processes imperfections.
that the signals undergo during transmission so as to retrieve
the original baseband signals (MPDU) for service to the data 4.5. Performance Evaluation of the OFDM System
link layer. Having concluded the implementation of IEEE 802.11g
OFDM PHY model, it is time to perform some analysis in
Rectangular QAM
order to assess the performance of the system. The approach
Unipolar to
Demodulator General Block Matrix Bipolar
Baseband Deinterleaver Deinterleaver Viterbi Decoder
employed has to do with visual assessment of the
Converter Insert Zero
General Unipolar to
Matrix
OFDM
Denormalize Rectangular
QAM
Block
Deinterleaver
Deinterleaver
Bipolar
Converter
Insert Zero
Viterbi Decoder constellation diagrams of the received signals before
Receiver
pilots demodulation at different SNR (10dB, 15dB, 20dB, 25dB
and 50dB). This is then compared to a plot of Bit error rate
Figure 8. IEEE 802.11g OFDM PHY.
(BER) versus SNR already presented in figure 11 Random
Source block to generate the noise. The initial seed parameter
in this block initializes the noise generator.
performed on a similar OFDM system at the same data rate in
[12].
1 AWGN 1 The constellation diagram of the transmitted signal after
modulation is as presented in fig. 12,13,14,15,16 and 17 adds
In Out
a complex Gaussian noise and produces a complex output
Figure 4.4. OFDM Receiver functional model. signal for a complex input. It inherits its sample time from
the input signal. It uses the signal processing blockset
A detail of OFDM Receiver block is presented in fig. 4.5.
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1849

Figure 11. IEEE 802.11g OFDM PHY.

Figure 12. Transmitted signal constellation.

Figure 14. The received 64 QAM signal constellation diagram at SNR =
15db.

Figure 13. The received 64 QAM signal constellation at SNR = 10db.

Figure 15. The received 64 QAM signal constellation diagram at SNR =
20db.
J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1850

Figure 17. BER/SNR plot.

4.6. Modeling of IEEE 802.11g DSSS PHY

The same steps followed in the modeling of the OFDM
subsystem was also followed for DSSS modeling. The DSSS
Figure 16. The received 64 QAM signal constellation diagram at SNR =
25db. PHY model is as presented in figure. 18 that follows.

Figure 18. IEEE 802.11g DSSS PHY model.

Figure 19. Real-Time Workshop Configuration Panel Window.

J. Agajo et al. / IJRRCS, Vol. 3, No. 5, pp. 1841-1851, October 2012 1851

4.7. Generation of the prototype software for the system [3] Official IEEE 802.11 working group project timelines". 2007
http://grouper.ieee.org/groups/802/11/Reports/802.11_Timelines.htm.
Having designed, modeled, simulated and verified the Retrieved on 2007-11-18.
IEEE 802.11g PHY systems, the next stage is the generation [4] "How to: Migrate to 802.11n in the Enterprise".
of the prototype software codes which, when implemented nets.com/resources/tutorials/migrate_80211n.html. Retrieved on 2008-
10-08.
with the other layers on a DSP or other general platforms will [5] http://www.wirevolution.com/2007/09/07/how-does-80211n-get-to-
fully implement the standard in software. As already 600mbps/
mentioned in Methodology, the software tool employed for [6] "Cuadro nacional de Atribución de Frecuencias CNAF". Secretaría
eEstadottp://www.mityc.es/Telecomunicaciones/Secciones/Espectro/c
this is Real-Time workshop, from Mathworks incorporated. naf. Retrieved on 2008-03-05.
There are several options available in Real-Time workshop [7] Evolution du régime d’autorisation pour les RLAN". French
on code generation depending on the availability of support Telecommunications Regulation Authority (ART).
http://www.arcep.fr/uploads/tx_gspublication/evol-rlan-250703.pdf.
tools and software. Retrieved on 2008-10-26.
It can: [8] Channel Deployment Issues for 2.4 GHz 802.11 WLANs". Cisco
• Generate a generic C or C++ code which can then be Systems,Inc. Channel.html. Retrieved on 2007-02-07.
[9] Garcia Villegas, E.; et. al. (2007), "Effect of adjacent-channel
targeted on any chosen platform. It neither builds the interference in IEEE 802.11 WLANs", CrownCom 2007., ICST &
executable code nor target it to any particular IEEE
platform; [10] 802.11 Technical Section". http://wifi.cs.st-
andrews.ac.uk/wififrame.html. Retrieved on 2008-12-15.
• Generate the C or C++ codes and builds the [11] Understanding 802.11 Frame Types". http://www.wi-
executable files but does not target it to any particular fiplanet.com/tutorials/article.php/1447501. Retrieved on 2008-12-14.
platform. Availability of support software like Code
Composer Studio (CCS) can be of help in this regard.
• Generate the codes and builds the executable file
based on the chosen target but does not download the
file to the target; and
• Creates the codes, builds the executable based on a
chosen selected target. This of course needs support
hardware and software.
Due to uneasy access to the required hardware and
support software, this project is limited to generation of C
codes that when compiled and executed on any general
platform, will fully perform the functions of the physical
layer of IEEE 802.11g WLAN standard.

4.8. Software Generation Process

After modeling and simulation, with the model open and
in the current window, on the simulation menu,
‘configuration Parameters’ is clicked to bring out the panel in
the Real-Time Workshop Configuration Panel Window.
It is on this panel that all parameters and options are set
for the code generation process. After the configuration, the
‘Generate Code’ button is clicked and the software is
generated. The generated software is as presented in
appendices.

5. Conclusion
This thesis presented important issues for the design of
SDR-based wireless systems and exploration of this concept
by implementing the physical layer of IEEE 802.11g
standard. SDR is a promising technology that facilitates
development of multi-band, multi-service, multi-standard,
multi-feature handsets and future-proof network
infrastructure equipment. It is a revolutionary force of change
that will further push towards a wire-free society.

References
[1] Looking for 802.11g Wireless Internet Access information, definitions
and technology descriptions?
[2] List of WLAN Channels ^ "ARRLWeb: Part 97 - Amateur Radio
Service". American Radio Relay League.
http://www.arrl.org/FandES/field/regulations/news/part9 IEEE. ISBN
0-7381-5656-9.

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