SN74LVC4245A

OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER

WITH 3-STATE OUTPUTS
www.ti.com SCAS375H – MARCH 1994 – REVISED MARCH 2005

FEATURES DB, DW, OR PW PACKAGE

• Bidirectional Voltage Translator (TOP VIEW)
• 5.5 V on A Port and 2.7 V to 3.6 V on B Port
(5 V) VCCA 1 24 VCCB (3.3 V)
• Control Inputs VIH/VIL Levels Are Referenced 2 23
DIR VCCB (3.3 V)
to VCCA Voltage 3 22
A1 OE
• Latch-Up Performance Exceeds 250 mA Per A2 4 21 B1
JESD 17 A3 5 20 B2
• ESD Protection Exceeds JESD 22 A4 6 19 B3
– 2000-V Human-Body Model (A114-A) A5 7 18 B4
A6 8 17 B5
– 200-V Machine Model (A115-A)
A7 9 16 B6
– 1000-V Charged-Device Model (C101)
A8 10 15 B7
GND 11 14 B8
DESCRIPTION/ORDERING INFORMATION 12 13
GND GND
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
<br/>

The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 device
without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to
align with the conventional '245 pinout.

ORDERING INFORMATION
TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 25 SN74LVC4245ADW
SOIC – DW LVC4245A
Reel of 2000 SN74LVC4245ADWR
SSOP – DB Reel of 2000 SN74LVC4245ADBR LJ245A
–40°C to 85°C
Tube of 60 SN74LVC4245APW
TSSOP – PW Reel of 2000 SN74LVC4245APWR LJ245A
Reel of 250 SN74LVC4245APWT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

FUNCTION TABLE
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1994–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS www.ti.com
SCAS375H – MARCH 1994 – REVISED MARCH 2005

LOGIC DIAGRAM (POSITIVE LOGIC)

2
DIR

22
OE

3
A1

21
B1

To Seven Other Channels

Absolute Maximum Ratings (1)

over operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted)
MIN MAX UNIT
VCCA Supply voltage range –0.5 6.5 V
A port (2) –0.5 VCCA + 0.5
VI Input voltage range V
Control inputs –0.5 6
VO Output voltage range A port (2) –0.5 VCCA + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through each VCCA or GND ±100 mA
DB package 63
θJA Package thermal impedance (3) DW package 46 °C/W
PW package 88
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 6 V maximum.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.

2
 SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
www.ti.com
WITH 3-STATE OUTPUTS
SCAS375H – MARCH 1994 – REVISED MARCH 2005
(1)
Absolute Maximum Ratings
over operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted)
MIN MAX UNIT
VCCB Supply voltage range –0.5 4.6 V
VI Input voltage range B port (2) –0.5 VCCB + 0.5 V
VO Output voltage range B port (2) –0.5 VCCB + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCCB or GND ±100 mA
DB package 63
θJA Package thermal impedance (3) DW package 46 °C/W
PW package 88
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions (1)

for VCCA = 4.5 V to 5.5 V
MIN MAX UNIT
VCCA Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIA Input voltage 0 VCCA V
VOA Output voltage 0 VCCA V
IOH High-level output current –24 mA
IOL Low-level output current 24 mA
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Recommended Operating Conditions (1)

for VCCB = 2.7 V to 3.6 V
MIN MAX UNIT
VCCB Supply voltage 2.7 3.6 V
VIH High-level input voltage VCCB = 2.7 V to 3.6 V 2 V
VIL Low-level input voltage VCCB = 2.7 V to 3.6 V 0.8 V
VIB Input voltage 0 VCCB V
VOB Output voltage 0 VCCB V
VCCB = 2.7 V –12
IOH High-level output current mA
VCCB = 3 V –24
VCCB = 2.7 V 12
IOL Low-level output current mA
VCCB = 3 V 24
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

3
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS www.ti.com
SCAS375H – MARCH 1994 – REVISED MARCH 2005

Electrical Characteristics (1)

over recommended operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS VCCA MIN TYP (2) MAX UNIT
4.5 V 4.3
IOH = –100 µA
5.5 V 5.3
VOH V
4.5 V 3.7
IOH = –24 mA
5.5 V 4.7
4.5 V 0.2
IOL = 100 µA
5.5 V 0.2
VOL V
4.5 V 0.55
IOL = 24 mA
5.5 V 0.55
II Control inputs VI = VCCA or GND 5.5 V ±1 µA
IOZ (3) A port VO = VCCA or GND 5.5 V ±5 µA
ICCA VI = VCCA or GND, IO = 0 5.5 V 80 µA
∆ICCA (4) One input at 3.4 V, Other inputs at VCCA or GND 5.5 V 1.5 mA
Ci Control inputs VI = VCCA or GND Open 5 pF
Cio A port VO = VCCA or GND 5V 11 pF

(1) VCCB = 2.7 V to 3.6 V

(2) All typical values are measured at VCC = 5 V, TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.

Electrical Characteristics (1)

over recommended operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS VCCB MIN TYP (2) MAX UNIT
IOH = –100 µA 2.7 V to 3.6 V VCC – 0.2
2.7 V 2.2
VOH IOH = –12 mA V
3V 2.4
IOH = –24 mA 3V 2
IOL = 100 µA 2.7 V to 3.6 V 0.2
VOL IOL = 12 mA 2.7 V 0.4 V
IOL = 24 mA 3V 0.55
IOZ (3) B port VO = VCCB or GND 3.6 V ±5 µA
ICCB VI = VCCB or GND, IO = 0 3.6 V 50 µA
∆ICCB (4) One input at VCCB – 0.6 V, Other inputs at VCCB or GND 2.7 V to 3.6 V 0.5 mA
Cio B port VO = VCCB or GND 3.3 V 11 pF

(1) VCCA = 5 V ± 0.5 V

(2) All typical values are measured at VCC = 3.3 V, TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.

4
 SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
www.ti.com
WITH 3-STATE OUTPUTS
SCAS375H – MARCH 1994 – REVISED MARCH 2005

Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1 and Figure 2)
VCCA = 5 V ± 0.5 V,
FROM TO VCCB = 2.7 V to 3.6 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX
tPHL 1 6.3
A B ns
tPLH 1 6.7
tPHL 1 6.1
B A ns
tPLH 1 5
tPZL 1 9
OE A ns
tPZH 1 8.1
tPZL 1 8.8
OE B ns
tPZH 1 9.8
tPLZ 1 7
OE A ns
tPHZ 1 5.8
tPLZ 1 7.7
OE B ns
tPHZ 1 7.8

Operating Characteristics
VCCA = 4.5 V to 5.5 V, VCCB = 2.7 V to 3.6 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Outputs enabled 39.5
Cpd Power dissipation capacitance per transceiver CL = 0, f = 10 MHz pF
Outputs disabled 5

Power-Up Considerations (1)

TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up
problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.

5
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS www.ti.com
SCAS375H – MARCH 1994 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

A PORT
2 × VCC

From Output 500 Ω S1 Open

TEST S1
Under Test GND
tPLH/tPHL Open
CL = 50 pF tPLZ/tPZL 2 × VCC
(see Note A) 500 Ω
tPHZ/tPZH GND

LOAD CIRCUIT

tw

VCC
Input 1.5 V 1.5 V
3V
0V Output 1.5 V 1.5 V
VOLTAGE WAVEFORMS Control
0V
PULSE DURATION
tPZL tPLZ
Output VCC
VCC Waveform 1 50% VCC
Input 1.5 V 1.5 V S1 at 2 × VCC VOL + 0.3 V
VOL
0V (see Note B)
tPZH tPHZ
tPLH tPHL Output
VOH Waveform 2 VOH
VOH - 0.3 V
Output 50% VCC 50% VCC S1 at GND 50% VCC
VOL (see Note B) ≈0 V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6
 SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
www.ti.com
WITH 3-STATE OUTPUTS
SCAS375H – MARCH 1994 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

B PORT
7V

From Output 500 Ω S1 Open

TEST S1
Under Test GND
tPLH/tPHL Open
CL = 50 pF tPLZ/tPZL 7V
(see Note A) 500 Ω
tPHZ/tPZH GND

LOAD CIRCUIT

tw

3V
Input 1.5 V 1.5 V
0V 3V
Output 1.5 V 1.5 V
VOLTAGE WAVEFORMS Control
0V
PULSE DURATION
tPZL tPLZ
Output 3.5 V
3V Waveform 1 1.5 V
1.5 V 1.5 V S1 at 7 V VOL + 0.3 V
Input VOL
0V (see Note B)
tPZH tPHZ
tPLH tPHL
VOH Output VOH
VOH - 0.3 V
Output 1.5 V 1.5 V Waveform 2 1.5 V
VOL S1 at GND ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

7
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2012

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
SN74LVC4245ADBR ACTIVE SSOP DB 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADW ACTIVE SOIC DW 24 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADWR ACTIVE SOIC DW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APW ACTIVE TSSOP PW 24 60 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWR ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWT ACTIVE TSSOP PW 24 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
SN74LVC4245APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2012

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
SN74LVC4245APWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC4245A :

• Enhanced Product: SN74LVC4245A-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC4245ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVC4245APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC4245ADBR SSOP DB 24 2000 367.0 367.0 38.0
SN74LVC4245ADWR SOIC DW 24 2000 367.0 367.0 45.0
SN74LVC4245APWR TSSOP PW 24 2000 367.0 367.0 38.0
SN74LVC4245APWT TSSOP PW 24 250 367.0 367.0 38.0

Pack Materials-Page 2
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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