UNIT 4 COMBINATIONAL LOGIC

Combinational circuit is a circuit in which we combine the different gates in the circuit,
for example encoder, decoder, multiplexer and demultiplexer. Some of the
characteristics of combinational circuits are following -

 The output of combinational circuit at any instant of time depends only on the
levels present at input terminals.
 The combinational circuit does not use any memory. The previous state of input
does not have any effect on the present state of the circuit.
 A combinational circuit can have an ‘n’ number of inputs and ‘m’ number of
outputs.

A Combinational Y0
B Y1
C Circuit Y2
……….. …………..
.………. …….…….
n Ym

Figure: Block diagram of Combinational Circuit

Binary Addition Circuits

Addition and Subtraction are two basic Arithmetic Operations that must be performed
by any Digital Computer. If both these operations can be properly implemented, then
Multiplication and Division tasks become easy (as multiplication is repeated addition
and division is repeated subtraction).
Consider the operation of adding two binary numbers, which is one of the fundamental
tasks performed by a digital computer. The four basic addition operations two single bit
binary numbers are:

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In the first three operations, each binary addition gives sum as one bit , i.e., either 0 or 1.
But for the fourth addition operation (where the inputs are 1 and 1), the result consists
of two binary digits. Here, the lower significant bit is called as the ‘Sum Bit’, while the
higher significant bit is called as the ‘Carry Bit’.

For single bit additions, there may not be an issue. The problem may arise when we try
to add binary numbers with more than one bit.

The logic circuits which are designed to perform the addition of two binary numbers
are called as Binary Adder Circuits. Depending on how they handle the output of the
‘1+1’ addition, they are divided into:

 Half Adder

 Full Adder

Let us take a look at the binary addition performed by various adder circuits.

Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs. The half
adder circuit is designed to add two single bit binary numbers A and B. It is the basic
building block for addition of two single bit numbers. This circuit has two outputs carry
out and sum.
Combinational
A Sum (∑)
Circuit

B Carry Out (C0)

Figure: Half Adder

Truth Table of Half Adder and Logic diagram

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From truth table it is clear that sum is taken from X-OR gate and Carry Out is taken
from AND gate. Inputs are labeled as A and B. The ‘Sum’ output is labeled as
summation symbol (∑) and the Carry output is labeled with CO.

Half adder is mainly used for addition of augend and addend of first order binary
numbers i.e., 1-bit binary numbers. We cannot add binary numbers with more than one
bit as the Half Adder cannot include the ‘Carry’ information from the previous sum.

Due to this limitation, Half Adder is practically not used in many applications,
especially in multi-digit addition. In such applications, carry of the previous digit
addition must be added along with two bits; hence it is a three bit addition.

Full Adder

A Full Adder is a combinational logic circuit which performs addition on three bits and
produces two outputs: a Sum and a Carry. As we have seen that the Half Adder cannot
respond to three inputs and hence the full adder is used to add three digits at a time.

It consists of three inputs, of which two are input variables representing the two
significant bits to be added, whereas the third input terminal is the carry from the
previous addition. The two outputs are a Sum and Carry outputs.

The following image shows a block diagram of a Full Adder where the inputs are
labeled as A, B and CIN, while the outputs are labeled as ∑ and COUT.

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 Outputs
Inputs

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

From the above truth table, we can obtain the Boolean Expressions for both the Sum
and Carry Outputs. Using those expressions, we can build the logic circuits for Full
Adder. But by simplifying the equations further, we can derive at a point that a Full
Adder can be easily implemented using two Half Adders and an OR Gate.

The following image shows a Full Adder Circuit implemented using two Half Adders
and an OR Gate. Here, A and B are the main input bits, CIN is the carry input, ∑ and
COUT are the Sum and Carry Outputs respectively.

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Parallel Binary Adders

As we discussed, a single Full Adder performs the addition of two one bit numbers and
also the carry input. For performing the addition of binary numbers with more than one
bit, more than one full adder is required and the number of Full Adders depends on the
number bits. Thus, a Parallel Adder is a combination of Multiple Full Adders and is
used for adding all bits of the two numbers simultaneously.

By connecting ‘n’ number of full adders in parallel, an n-bit Parallel Adder can be
constructed. From the below figure, it is to be noted that there is no carry at the least
significant position, hence we can use either a half adder or make the carry input of full
adder as zero at this position.

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The following figure shows a Parallel 4-bit Binary Adder, which has three full adders
and one half adder. The two binary numbers to be added are ‘A3 A2 A1 A0’ and
‘B3 B2 B1 B0‘, which are applied to the corresponding inputs of the Full Adders. This
parallel adder produces their result as ‘C4 S3 S2 S1 S0‘ , where C4 is the final carry.

In the 4 bit adder, first block is a half-adder that has two inputs as A0 B0 and produces a
sum S0 and a carry bit C1. The first block can also be a full adder and if so, then the input
Carry C0 must be 0.

Next three blocks should be full adders, as there are three inputs applied to them (two
main binary bits and a Carry bit from the previous stage).

Hence, the second block full adder produces a sum S1 and a carry C2. This will be
followed by other two full adders and thus the final result is C4 S3 S2 S1 S0.

Commonly, the Full Adders are designed in dual in-line package integrated circuits.
74LS283 is a popular 4-bit full adder IC. Arithmetic and Logic Unit or ALU of a
computer consist of these parallel adders to perform the addition of binary numbers.

Binary Subtraction Circuits

Another basic arithmetic operation to be performed by Digital Computers is the

Subtraction. Subtraction is a mathematical operation in which one integer number is
deducted from another to obtain the equivalent quantity. The number from which other
number is to be deducted is called as ‘Minuend’ and the number subtracted from the
minuend is called ‘Subtrahend’.

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Similar to the binary addition, binary subtraction is also has four possible basic
operations. They are:

 0–0=0

 0 – 1 = 1 (Borrow 1)

 1–0=1

 1–1=0

Similar to the adder circuits, basic subtraction circuits are also of two types:

 Half Subtractor

 Full Subtractor

Half Subtractor

A Half Subtractor is a multiple output Combinational Logic Circuit that does the
subtraction of two 1-bit binary numbers. It has two inputs and two outputs. The two
inputs correspond to the two 1-bit binary numbers and the two outputs correspond to
the Difference bit and Borrow bit (in contrast to Sum and Carry in Half Adder).

Following table shows the truth table of a Half Subtractor.

This circuit is similar to that of the Half Adder with only difference being the minuend
input i.e., A is complemented before applied at the AND gate to implement the borrow
output.

In case of multi-digit subtraction, subtraction between the two digits must be performed
along with borrow of the previous digit subtraction, and hence a subtractor needs to

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have three inputs, which is not possible with a Half Subtractor. Therefore, a half
subtractor has limited set of applications and strictly speaking, it is not used in practice.

Full Subtractor

A Full Subtractor is a combinational logic circuit which performs a subtraction between

the two 1-bit binary numbers and it also considers the borrow of the previous bit i.e.,
whether 1 has been borrowed by the previous minuend bit.

So, a Full Subtractor has three inputs, in which two inputs corresponding to the two bits
to be subtracted (minuend A and subtrahend B), and a borrow bit, usually represented
as BIN, corresponding to the borrow operation. There are two outputs, one corresponds
to the difference D output and the other Borrow output BO.

By deriving the Boolean expression for the full subtractor from above truth table, we get
the expression that tells that a full
subtractor can be implemented with half
subtractors with OR gate as shown in figure
below.

Inputs Outputs (A-B-Bin)

A B Bin Difference, Bout

D
Therefore, it is possible to convert the full
0 0 0 0 0
adder circuit into full subtractor by simply
0 0 1 1 1 complementing the input A before it is
applied to the gates to produce the final
0 1 0 1 1
borrow bit output Bo.
0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

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Parallel Binary Subtractors

To perform the subtraction of binary numbers with more than one bit, we have to use
the Parallel Subtractors. This parallel subtractor can be designed in several ways,
including combination of half and full subtractors, all full subtractors, all full adders
with subtrahend complement input, etc.

The below figure shows a 4 bit Parallel Binary Subtractor formed by connecting one half
subtractor and three full subtractors.

In this subtractor, 4 bit minuend ‘A3 A2 A1 A0‘ is subtracted by 4 bit

subtrahend ‘B3 B2 B1 B0‘ and the result is the difference output ‘D3 D2 D1 D0‘ . The
borrow output of each subtractor is connected as the borrow input to the next
subtractor.

It is also possible to design a 4 bit parallel subtractor using 4 full adders as shown in the
below figure. This circuit performs the subtraction operation by considering the
principle that the addition of minuend and the complement of the subtrahend is
equivalent to the subtraction process.

We know that the subtraction of A by B is obtained by taking 2’s complement of B and

adding it to A. The 2’s complement of B is obtained by taking 1’s complement and
adding 1 to the least significant pair of bits.

Hence, in this circuit 1’s complement of B is obtained with the inverters (NOT gate) and
a 1 can be added to the sum through the input carry.

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Parallel Adder / Subtractor

The operations of both addition and subtraction can be performed by a one common
binary adder. Such binary circuit can be designed by adding an Ex-OR gate with each
full adder as shown in below figure. The figure below shows the 4 bit parallel binary
adder/subtractor which has two 4 bit inputs as ‘A3 A2 A1 A0‘ and ‘B3 B2 B1 B0‘.

The mode input control line M is connected with carry input of the least significant bit
of the full adder. This control line decides the type of operation, whether addition or
subtraction.

When M= 1, the circuit is a subtractor

and when M=0, the circuit becomes
adder. The Ex-OR gate consists of two
inputs to which one is connected to
the B and other to input M. When M =
0, B Ex-OR of 0 produce B. Then, full
adders add the B with A with carry
input zero and hence an addition operation is performed.

When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence, the
complemented B inputs are added to A and 1 is added through the input carry, nothing
but a 2’s complement operation. Therefore, the subtraction operation is performed.

Multiplexer
Multiplexer means many into one. A multiplexer is a circuit used to select and route
any one of the several input signals to a single output. A simple example of a non-
electronic circuit of a multiplexer is a single pole multi-position switch.

Multi-position switches are widely used in many electronics circuit. However, circuits
that operate at high speed require the multiplexer to be automatically selected. A
mechanical switch cannot perform this task efficiently. Therefore, multiplexer is used to
perform high speed switching are constructed of electronic components.

Multiplexers can handle two type of data i.e., analog and digital. For analog application,
multiplexer are built using relays and transistor switches. For digital application, they
are built from standard logic gates.

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The multiplexer used for digital applications, also called digital multiplexer, is a circuit
with many input but only one output. By applying control signals (also known as Select
Signals), we can steer any input to the output. Some of the common types of
multiplexer are 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexer.

Understanding 4-to-1 Multiplexer

The 4-to-1 multiplexer has 4 input bits, 2 control or select bits, and 1 output bit. The
select input determines which of the input data bit is transmitted to the output. One of
these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

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1 1 I3
From Truth table, we can directly write the Boolean function for output, Y as

Y=S1′S0′I0 + S1'S0I1 + S1S0′I2 + S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR gate.
The circuit diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the

above circuit. Similarly, you can implement
8x1 Multiplexer and 16x1 multiplexer by
following the same procedure.

 An example of 4-to-1 multiplexer is IC

74153 in which the output is same as the input.

 Another example of 4-to-1 multiplexer is 45352 in which the output is the

compliment of the input.

 Example of 16-to-1 line multiplexer is IC 74150.

Applications of Multiplexer

Multiplexer are used in various fields where multiple data need to be transmitted using
a single line. Following are some of the applications of multiplexers –

1. Communication System – Communication system is a set of system that enables

communication like transmission system, relay and tributary station, and
communication network. The efficiency of communication system can be
increased considerably using multiplexer. Multiplexer allow the process of
transmitting different type of data such as audio, video at the same time using a
single transmission line.

2. Telephone Network – In telephone network, multiple audio signals are

integrated on a single line for transmission with the help of multiplexers. In this
way, multiple audio signals can be isolated and eventually, the desire audio
signals reach the intended recipients.

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 3. Computer Memory – Multiplexers are used to implement huge amount of
memory into the computer, at the same time reduces the number of copper lines
required to connect the memory to other parts of the computer circuit.

4. Transmission from the Computer System of a Satellite – Multiplexer can be

used for the transmission of data signals from the computer system of a satellite
or spacecraft to the ground system using the GPS (Global Positioning System)
satellites.

Q. Design an 8-to-1 line multiplexer using lower order multiplexers and explain
it.

Soln:

The same selection lines, S1 & S0 are applied to both 4x1 Multiplexers. The data inputs of
upper 4x1 Multiplexer are I0 to I3 and the data inputs of lower 4x1 Multiplexer are I4 to
I7. Therefore, each 4x1 Multiplexer produces an output based on the values of selection
lines, S1 & S0.

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that
is present in second stage. The other selection line, S2 is applied to 2x1 Multiplexer.

If S2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 0 to I3 based
on the values of selection lines S1 & S0.

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If S2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 4 to I7 based
on the values of selection lines S1 & S0. Therefore, the overall combination of two 4x1
Multiplexers and one 2x1 Multiplexer performs as one 8x1 Multiplexer.

Q. Implement the Boolean function (𝑨,,) = ∑(𝟏,𝟑,𝟓,𝟔) with multiplexer.

Soln:

The multiplexer can be implemented with 4 to 1 multiplexer. It is possible to generate n+1

variables with 2n to 1 multiplexer.

Now, truth table for the given function is:

Now the implementation table is

If the minterms in a column are not circled, then apply 0 to the corresponding
multiplexer unit.

If the 2 minterms are circled, then apply 1 to the corresponding multiplexer unit.

If the bottom minterm is circled, and top is not circled then apply 𝐴 to the
corresponding multiplexer unit.

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If the top minterm is circled, and bottom is not circled then apply 𝐴′ to the
corresponding multiplexer unit.

Multiplexer implementation:

Q. Implement the Boolean function 𝑭(𝑨,𝑩,𝑪,𝑫)=∑(𝟎,𝟏,𝟑,𝟒,𝟖,𝟗,𝟏𝟓) by

multiplexer.

Soln: This function can be implemented with 8 to 1 MUX. The truth table for
the function is:-

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Now the implementation table and multiplexer implementation are given below:

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Demultiplexer
Demultiplexer means one to many. A demultiplexer is a circuit with one input and
many outputs. DEMUX or De-Multiplexer is a data distributor combinational circuit. It
works in a reverse way of the Multiplexer. By applying control signal, we can steer any
input to the output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16
demultiplexer. Following figure illustrate the general idea of a demultiplexer with 1
input

signal, m control signals, and n output signals.

1-to-4 Demultiplexer

The 1-to-4 demultiplexer has 1 input bit, 2 control or select bits, and 4 output bits. An
example of 1-to-4 demultiplexer is IC 74155. The 1-to-4 demultiplexer is shown in figure
below-

The input bit is labeled as Data D. This data bit is transmitted to the selected output
lines, which depends on the values of A and B, the
control or Select Inputs.

When A B = 0 1 , the second AND gate from the top is

enabled while other AND gates are disabled. Therefore,
data bit D is transmitted to the output Y1, giving Y1 =
Data.

If D is LOW, Y1 is LOW. If D is HIGH, Y1 is HIGH.

The value of Y1 depends upon the value of D. All other
outputs are in low state.

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Truth table of the 1x4 DEMUX as mentioned below.

Selection Inputs Outputs

B A Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
If the control input is changed to A B = 1 0, all the gates are disabled except the third
AND gate from the top. Then, D is transmitted only to the Y2 output, and Y2 = Data.

1x8 De-Multiplexer

The 1x8 DEMUX was designed by using two DEMUX. They are the two 1x4 DEMUX
and one 1x2 DEMUX. The 1x8 DEMUX contains two input lines with four outputs. Let
us see the block diagram of the 1x8 DEMUX as mentioned below.

Selection Inputs Outputs

S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 I
0 0 1 0 0 0 0 0 0 I 0
0 1 0 0 0 0 0 0 I 0 0
0 1 1 0 0 0 0 I 0 0 0
1 0 0 0 0 0 I 0 0 0 0
1 0 1 0 0 I 0 0 0 0 0
1 1 0 0 I 0 0 0 0 0 0
1 1 1 I 0 0 0 0 0 0 0

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Here, the 1x8 DEMUX truth table is as mentioned above.

1x16 De-Multiplexer

SELECTION INPUTS OUTPUTS

S3 S2 S1 S0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0

0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0

0 1 0 1 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0

0 1 1 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0

0 1 1 1 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 0 0

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SELECTION INPUTS OUTPUTS

1 0 1 1 0 0 0 0 A 0 0 0 0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0

1 1 0 1 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The 1x16 DEMUX was designed by using the two 1x8 DEMUX and one 1x2 DEMUX.
The 1x16 DEMUX have two input lines. It has eight outputs. Let us see the block
diagram of the 1x16 DEMUX as mentioned below.

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Example of 1-to-16 demultiplexer is IC 74154. It has 1 input bit, 4 control / select bits and
16 output bit.

Applications of Demultiplexer

1. Demultiplexer is used to connect a single source to multiple destinations. The

main application area of demultiplexer is communication system, where
multiplexers are used. Most of the communication system are bidirectional i.e.,
they function in both ways (transmitting and receiving signals). Hence, for most
of the applications, the multiplexer and demultiplexer work in sync.
Demultiplexer is also used for reconstruction of parallel data and ALU circuits.

2. Communication System – Communication system use multiplexer to carry

multiple data like audio, video and other form of data using a single line for
transmission. This process makes the transmission easier. The demultiplexer
receives the output signals of the multiplexer and converts them back to the
original form of the data at the receiving end. The multiplexer and demultiplexer
work together to carry out the process of transmission and reception of data in
communication system.

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 3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be
stored in multiple registers or storage units with the help of demultiplexer. The
output of ALU is fed as the data input to the demultiplexer. Each output of
demultiplexer is connected to multiple register which can be stored in the
registers.

4. Serial to Parallel Converter – A serial to parallel converter is used for

reconstructing parallel data from incoming serial data stream. In this technique,
serial data from the incoming serial data stream is given as data input to the
demultiplexer at the regular intervals. A counter is attach to the control input of
the demultiplexer. This counter directs the data signal to the output of the
demultiplexer where these data signals are stored. When all data signals have
been stored, the output of the demultiplexer can be retrieved and read out in
parallel.

Encoders
An encoder is a combinational circuit that converts binary information in the form of a
2N input lines into N output lines, which represent N bit code for the input. For simple
encoders, it is assumed that only one input line is active at a time.

As an example, let’s consider Octal to Binary encoder. As shown in the following figure,
an octal-to-binary encoder takes 8 input lines and generates 3 output lines.

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Truth Table –

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active;
010 when D2 is active and so on.

Implementation –

From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7.
Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5,
6 or 7. Hence, the Boolean functions would be:

X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7

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Hence, the encoder can be realized with OR gates as follows:

One limitation of this encoder is that only one input can be active at any given time. If
more than one input is active, then the output is undefined. For example, if D6 and D3
are both active, then, our output would be 111 which is the output for D7. To overcome
this, we use Priority Encoders.

Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000 which
actually is the output for D0 active. In order to avoid this, an extra bit can be added to
the output, called the valid bit which is 0 when all inputs are 0 and 1 otherwise.

Priority Encoder

A priority encoder is an encoder circuit in which inputs are given priorities. When more
than one inputs are active at the same time, the input with higher priority takes
precedence and the output corresponding to that is generated.

In case of an ordinary encoder, one and only one decimal input can be activated at any
given time. But in the case of some practical digital systems, two or more decimal
inputs can unintentionally become active at the same time that might cause confusion.
For example, on a keyboard, a user presses key 4 before releasing another key 2. In such
a situation, the output will be corresponding to (6)10, instead of being (4)10 or (2)10.
This kind of problems can be solved with the help of priority encoder. According to the
priority system, the decimal input having largest magnitude among all the
simultaneous inputs is encoded. Hence, as per this priority encoding system, the
priority encoder would encode 4 if both 4 and 2 are active at the same time.

Several types of priority encoders are there. Some most important types of priority
encoders are listed and explained below.

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• 4 Input Priority Encoder

• Decimal to BCD Priority Encoder

• Octal to Binary Priority Encoder

Let us consider the 4 to 2 priority encoder as an example. From the truth table, It has
three outputs designated by A, B, and V. Where, A and B are the ordinary outputs and
V is the output that acts as a valid bit indicator. This third output V is set to 1 when one
or more inputs are equal to 1. In the case, when all the inputs to the encoder are equal to
0, there is no any valid input, and thus the output V is set to 0. The other two outputs,
i.e. A and B of the encoder are not determined when V is equal to 0. Therefore, when, V
is equal to 0, the outputs A and B are specified as "don’t care conditions". Here, D3 has
highest priority, therefore, whatever are the other inputs, when D3 is high, and output
has to be 11. And D0 has the lowest priority, therefore the output would be 00 only
when D0 is high and the other input lines are low. Similarly, D2 has higher priority over
D1 and D0 but lower than D3 therefore the output would be 10 only when D2 is high
and D3 are low (D0 & D1 are don’t care).

Truth Table
D3 D2 D1 D0 X Y V

0 0 0 0 X x 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

It can clearly be seen that the condition for valid bit to be 1 is that at least any one of the
inputs should be high. Hence,

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V = D0 + D1 + D2 + D3

For X:

=> X = D2 + D3

For Y:

=> Y = D1 D2’ + D3

Hence, the priority 4-to-2 encoder can be realized as follows:

Decimal to BCD Priority Encoder

This type of priority encoder performs the function of encoding the decimal digits into
4-bit BCD (Binary Coded Decimal) outputs. As it is a decimal to BCD priority encoder,

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therefore, it produces a BCD corresponding to the decimal digit of highest priority
among all the inputs and ignores all others.

The truth table of the decimal to BCD priority encoder is given below.

Decimal Inputs (× = Don’t care) BCD Outputs

I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0

1 1 1 1 1 1 1 1 1 1 1 1 1

× × × × × × × × 0 0 1 1 0

× × × × × × × 0 1 0 1 1 1

× × × × × × 0 1 1 1 0 0 0

× × × × × 0 1 1 1 1 0 0 1

× × × × 0 1 1 1 1 1 0 1 0

× × × 0 1 1 1 1 1 1 0 1 1

× × 0 1 1 1 1 1 1 1 1 0 0

× 0 1 1 1 1 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1 1 1 1 1 0

The truth table of the decimal to BCD priority encoder clearly shows that the
magnitudes of the decimal inputs determine their priorities. If any decimal input is
HIGH, it will be encoded if all other higher value inputs are LOW regardless of the state
of all lower value inputs.

Octal to Binary Priority Encoder

This type of priority encoder is used to perform encoding of octal code into binary code.
Hence, this type priority encoder has eight inputs and three outputs that produce
corresponding binary code as given in the truth table below.

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 Inputs Outputs

I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 V

0 0 0 0 0 0 0 0 × × × 0

1 0 0 0 0 0 0 0 0 0 0 1

× 1 0 0 0 0 0 0 0 0 1 1

× × 1 0 0 0 0 0 0 1 0 1

× × × 1 0 0 0 0 0 1 1 1

× × × × 1 0 0 0 1 0 0 1

× × × × × 1 0 0 1 0 1 1

× × × × × × 1 0 1 1 0 1

× × × × × × × 1 1 1 1 1

Decoder
The conversion of binary to decimal can be done using a device namely a decoder. This
device is one kind of combinational logic circuit that uses the n-input lines to generate
2n output lines. Here, the output of this device might be below 2 n lines. There are
different kinds of binary decoders which include multiple inputs as well as multiple
outputs. Some kinds of decoders include one or more enable inputs along with the data
inputs. Whenever the enable input is disabled then all the outputs will be inactivated.
Based on its function, a binary decoder changes the data from n-input signals to 2n
output signals. In some kinds of decoders, they have below 2n output lines. So in that
situation, a minimum of one output prototype may be repeated for various input
values. There are two kinds of higher-order decoders like 3 Line to 8 Line Decoder & 4
Line to 16 Line Decoder.

What is a Decoder?

A decoder is a combinational circuit that is used to change the code into a set of signals.
It is the reverse process of an encoder. A decoder circuit takes multiple inputs and gives
multiple outputs. A decoder circuit takes binary data of ‘n’ inputs into ‘2^n’ unique

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output. In addition to input pins, the decoder has a enable pin. This enables the pin
when negated, to make the circuit inactive. in this article, we discuss 3 to 8 line Decoder
and demultiplexer.

The below is the truth table for a simple 1 to 2 line decoder where A is the input and D0
and D1 are the outputs.

Why do we need a Decoder?

The main function of a decoder is to change a code into a set of signals because it is
opposite to an encoder, but the designing decoder is simple. The main difference
between a decoder and a demultiplexer is a combinational circuit that is used to allow
only one input as well as direct it into one of the outputs, whereas a decoder allows
several inputs and generates the decoded output.

2 Line to 4 Line Decoder

This 2 line to 4 line decoder includes two inputs like A0 & A1 & 4 outputs like Y0 to Y4.
The block diagram of this decoder is shown below.

2 Line to 4 Line Decoder

When the inputs and enable are 1 then the output will be 1. Here is the truth table of 2
to 4 decoder.

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 E A1 A0 Y3 Y2 Y1 Y0

0 x X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

The Boolean expression for every output is

Y3 = E. A1. A0

Y2 = E. A1. A0′

Y1 = E. A1′. A0

Y0 = E. A1′. A0′

Every output of this decoder includes one product term. So the four product terms can
be implemented through 4 AND gates where each gate includes 3 inputs as well as 2
inverters. The 2 to 4 decoder logic diagram is shown below. Thus, this decoder’s output
is nothing but the minterms of inputs and enable is equivalent to 1. If enable is zero,
afterward all the decoder’s outputs will be equivalent to zero. Likewise, 3 line to 8 line
decoder generates eight minterms for 3 input variables of A0, A1 & A2.

Logic Diagram of 2 to 4 Decoder

3 Line to 8 Line Decoder implementation using two 2 to 4 line decoder

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The implementation of this 3 line to 8 line decoder can be done using two 2 lines to 4
line decoders. 2 to 4 line decoder includes two inputs and four outputs. So, in 3 lines to
8 line decoder, it includes three inputs like A2, A1 & A0 and 8 outputs from Y7 – Y0.

The following formula is used to implementation of higher-order decoders with the

help of low order decoders. The number of lower-order decoders required is m2/m1

Where,

The number of o/ps for the lower-order decoder is ‘m1’

The number of o/ps for higher-order decoder is ‘m2’

For instance, when m1 = 4 & m2 = 8, then substitute these values in the above equation.
We can get the required no. of decoders are 2. So, for implementing a single 3 to 8
decoder, we need two 2 lines to 4 line decoders. Here, the block diagram is shown
below by using two 2 to 4 decoders.

The parallel inputs like A2, A1 & A0 are given to 3 lines to 8 line decoder. Here the
compliment of A3 is given to enable the pin of the decoder to obtain the outputs like Y7
to Y0. These outputs are lower 8 minterms. In the above decoder, the A3 input is
connected to enable the pin to obtain the outputs from Y15 – Y8. So, these outputs are
the higher 8 minterms.

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 A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 0 0 0 0 1

In 3 to 8 line decoder, it includes three inputs and eight outputs. Here the inputs are
represented through A, B & C whereas the outputs are represented through D0, D1,
D2<D7.

The selection of 8 outputs can be done based on the three inputs. So, the truth table of
this 3 line to 8 line decoder is shown below. From the following truth table, we can
observe that simply one of 8 outputs from DO – D7 can be selected depending on 3
select inputs. From the above truth table of 3 lines to 8 line decoder, the logic expression
can be defined as

D0 = A’B’C’
D1= A’B’C
D2 = A’BC’
D3 = A’BC
D4 = AB’C’
D5= AB’C
D6 = ABC’
D7 = ABC

From the above Boolean expressions, the implementation of 3 to 8 decoder circuit can be
done with the help of three NOT gates & 8-three input AND gates. In the above circuit,

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the three inputs can be decoded into 8 outputs, where every output represents one of
the midterms of the three input variables. The 3 inverters in the above logic circuit will
provide the complement of the inputs & each one of the AND gates will generate one of
the midterms.

This kind of decoder mainly used to decode any 3-bit code & generates eight outputs,
equivalent to 8 different combinations for the input code.

This decoder is also known as a binary to octal decoder because the inputs of this
decoder represent three-bit binary numbers whereas the outputs represent the 8 digits
within the octal number system.

Figure: 3 to 8 Decoder Circuit

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  BCD to 7 Segment Decoder

What is 7 segment decoder?

A seven-segment display is a form of electronic display device for

displaying decimal numerals that is an alternative to the more
complex dot matrix displays.

In Binary Coded Decimal (BCD) encoding scheme each of the decimal numbers (0-9) is
represented by its equivalent binary pattern (which is generally of 4-bits).

Whereas, Seven segment display is an electronic device which consists of seven Light
Emitting Diodes (LEDs) arranged in some definite pattern (common cathode or
common anode type), which is used to display Hexadecimal numerals (in this case
decimal numbers, as input is BCD i.e., 0-9).

Two types of seven segments LED display:

1. Common Cathode Type: In this type of display all cathodes of the seven LEDs
are connected together to the ground or –Vcc (hence, common cathode) and LED
displays digits when some ‘HIGH’ signal is supplied to the individual anodes.

2. Common Anode Type: In this type of display all the anodes of the seven LEDs
are connected to battery or +Vcc and LED displays digits when some ‘LOW’
signal is supplied to the individual cathodes.

But, seven segment displays does not work by directly supplying voltage to different
segments of LEDs. First, our decimal number is changed to its BCD equivalent signal
then BCD to seven segment decoder converts
that signals to the form which is fed to seven
segment display.

This BCD to seven segment decoder has four

input lines (A, B, C and D) and 7 output lines
(a, b, c, d, e, f and g), this output is given to
seven segment LED display which displays

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the decimal number depending upon inputs.

Truth Table – For common cathode type BCD to seven segment decoder:

 BCD numbers only range from 0 to 9,thus rest inputs from 10-F are invalid
inputs.

Explanation

For combination where all the inputs (A, B, C and D) are zero (see Truth Table), our
output lines are a = 1, b = 1, c = 1, d = 1, e = 1, f = 1 and g = 0. So 7 segment display shows
‘zero’ as output.

Similarly, for combination where one of the input is one (D = 1) and rest are zero,our
output lines are a = 0, b = 1, c = 1, d = 0, e = 0, f = 0 and g = 0. So only LEDs ‘b’ and ‘c’ (see
diagram above) will glow and 7 segment display shows ‘one’ as output.

K-Maps:

#for a: For b For c For d

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For e For f For g

The applications of seven segments are mostly in digital calculators, electronic meters,
digital clocks, odometers, digital clocks, clock radios, etc. Today most of the 7 segment
applications are using LCDs, because of low current consumption.

Q. Implement a full-adder circuit with a decoder and two OR gates.

Soln: The truth table for full adder: From the truth table

(𝐴,𝐵,𝐶𝑖𝑛)=∑(1,2,4,7)

(𝐴,𝐵,𝐶𝑖𝑛)=∑(3,5,6,7)

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Since there are three inputs and a total of eight minterms. So we need 3-to-8 line decoder. The
decoder generates the eight minterms for 𝐴, & 𝐶𝑖𝑛. The OR gate for output sum (𝑆) forms the
sum of minterms 1, 2, 4 & 7. The OR gate for the output carry (𝐶) forms the sum of minterms 3,
5, 6 & 7.

Q. Using a decoder and external gates, design the combinational circuit defined by the following three
Boolean functions:

𝑭𝟏= 𝒙′𝒚′𝒛 + 𝒙𝒛′

𝑭𝟐= 𝒙′𝒚𝒛′+ 𝒙𝒚′
𝑭𝟑= 𝒙𝒚 𝒛′+ 𝒙𝒚
Soln:

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  Code Converters – BCD to/from Excess-3
Excess-3 binary code is an unweighted self-complementary BCD code. Self-Complementary
property means that the 1’s complement of an excess-3 number is the excess-3 code of the 9’s
complement of the corresponding decimal number. This property is useful since a decimal
number can be nines’ complemented (for subtraction) as easily as a binary number can be
ones’ complemented; just by inverting all bits. For example, the excess-3 code for 3(0011) is
0110, and to find the excess-3 code of the complement of 3, we just need to find the 1’s
complement of 0110 -> 1001, which is also the excess-3 code for the 9’s complement of 3 -> (9-
3) = 6.

Converting BCD to Excess-3

As is clear by the name, a BCD digit can be converted to its corresponding Excess-3
code by simply adding 3 to it. Since we have only 10 digits (0 to 9) in decimal, we
don’t care about the rest and marked them with a cross( X ).
Let A, B, C, D be the bits representing the binary numbers, where D is the LSB and A
is the MSB, and Let w, x, y, z be the bits representing the gray code of the binary
numbers, where z is the LSB and w is the MSB.
The truth table for the conversion is given below. The X’s mark is don’t care condition.

To find the corresponding digital circuit, we will use the

K-Map technique for each of the Excess-3 code bits as
output with all of the bits of the BCD number as input.

w=A+BC+BD

x=B'C+B'D+BC'D'
y=CD+C'D'
z=D'

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Converting Excess-3 to BCD
Excess-3 code can be converted back to BCD in the same manner.
Let A, B, C, D be the bits representing the binary numbers,
where D is the LSB and A is the MSB, and Let w, x, y, z be the
bits representing the gray code of the binary numbers, where z is
the LSB and w is the MSB. The truth table for the conversion is
given below. The X’s mark is don’t care condition.

Corresponding Boolean expressions are,

A=wx+wyz B=x'y'+x'z'+xyz C=y'z+yz' D=z'

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