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Tri-state buffer

The document discusses the tri-state bus buffer, a digital circuit that operates in three states: logic 1, logic 0, and high-impedance. It explains how bus systems can be constructed using tri-state buffers, allowing multiple outputs to connect to a common bus line without interference. The document also highlights the importance of controlling the active state of buffers to prevent loading effects on the bus system.

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10 views

Tri-state buffer

The document discusses the tri-state bus buffer, a digital circuit that operates in three states: logic 1, logic 0, and high-impedance. It explains how bus systems can be constructed using tri-state buffers, allowing multiple outputs to connect to a common bus line without interference. The document also highlights the importance of controlling the active state of buffers to prevent loading effects on the bus system.

Uploaded by

kudesiat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BUS SYSTEM USING TRI-

STATE BUFFER
CONTENTS

 TRI-STATE BUS BUFFER

 BUS SYSTEM USING TRI-STATE BUFFER


TRI-STATE BUS BUFFER
A three-state gate is a digital circuit that exhibits three states. Two of
the states are signals equivalent to logic 1 and 0 as in a conventional
gate.

The third state is a high-impedance state.

The high-impedance state behaves like an open circuit, which means


that the output is disconnected and does not have a logic significance.

 Three-state gates may perform any conventional logic, such as AND


or NAND. However, the one most commonly used in the design of a bus
system is the buffer gate.
TRI-STATE BUS BUFFER
• A bus system that can be constructed with three state buffer gates is
called three-state bus buffer.
• Buffer gate has the property that what we gave input is considered as
output.
• Three-State Gates: A 3 state gate is a digital circuit that shows 3
states.
i) state1 ii) state-0 iii) High impedence
APPLICATION OF TRI-STATE BUS BUFFER

A Bus System can be constructed with tri-states gates instead of


multiplexers.
GRAPHIC SYMBOL OF A TRI-STATE BUFFER
It is distinguished from a normal buffer by having both a normal input and a
control input. The control input determines the output state. When the control
input is equal to 1, the output is enabled and the gate behaves like any
conventional buffer, with the output equal to the normal input.
When the control input is 0, the output is disabled and the gate goes to a high-
impedance state, regardless of the value in the normal input.
SPECIAL FEATURE OF A TRI-STATE BUFFER

The high-impedance state of a tri-state gate provides a special feature not


available in other gates.
Because of this feature, a large number of tri-state gate outputs can be
connected with wires to form a common bus line without endangering
loading effects.
Bus System with Tri-State Buffers
Bus System with Tri-State Buffers

The outputs of four buffers are connected together to form a single bus line.
(It must be realized that this type of connection cannot be done with gates
that don't have three-state outputs.)
The control inputs to the buffers determine which of the four normal inputs
will communicate with the bus line. No more than one buffer may be in the
active state at any given time. The connected buffers must be controlled so
that only one three-state buffer has access to the bus line while all other
buffers are maintained in a high-impedance state.
Bus System with Tri-State Buffers

One way to ensure that no more than one control input is active at any
given time is to use a decoder.
When the enable input of the decoder is 0, all of its four outputs are 0, and
the bus line is in a high-impedance state because all four buffers are
disabled.
When the enable input is active, one of the three-state buffers will be
active, depending on the binary value in the select inputs of the decoder.
Bus System with Tri-State Buffers

To construct a common bus for four registers of n bits each using three-state
buffers, we need n circuits with four buffers in each as shown in last figure .
Each group of four buffers receives one significant bit from the four
registers. Each common output produces one of the lines for the common
bus for a total of n lines. Only one decoder is necessary to select between
the four registers.

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