Embedded System and IOT Design Handwritten Notes-1
Embedded System and IOT Design Handwritten Notes-1
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Embedded Systems and IOT Design
UNIT II
EMBEDDED SYSTEMS
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Embedded Systems and I0T Design
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Embedded Systems and I0T Design
sephidi eoate.(
šiophidi cated syet em fon conlaotiry the wheels
syst emm (AB s) reduces
tay. An nlilock xake
skid.ng ig pempinq the bvakes
utomalic. slability tonol (Asc+)
An
inlervwnes widh the engire during maneuveing
ytem
systems
le inpeve he car ' stability. These
nqune ink fhmm and output to automobile.
ihe As Sensors on ea ch
syslom tu.ses
iydvoulic
Brake pump Brake
ABS
Brake
Brake
Sensor Sensor
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Embedded Systems and I0T Design
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Embedded Systems and I0T Design
First, a desiqn to
ensure that we have
(Architechre
Compon ents
System
Dntegraion
f4:Major levels of abstrachon in the desiqn proies
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Embedded Systems and IOT Design
Requirements:
Requirementt may be functional
funchiona Typicad non funchon al requiremens
incude:
Performance :
1t may be a combinatio
Of Soft performance metrics such as apprima te
time to perjorm a user level funetion and hard
deadlines by whi ch a pauti el ar operati may
be comple ted.
• Cost :
Cost typicatly has kwo major
-
Component manufactving cost an d nonYeurring
engineerinS (NRE) cost
Physical size and weighti The physical
final sgetem Can vay greaty
depending upon the applicahon. A hand held
device typrcaly has tight requiremens on bot
Size and weight than Can Tipple through entiie design
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Embedded Systems and I0T Design
• Power Cons
uphion: Power is important in
This is
siople but helpful. Giving a hame to
to
the project not only simplifies talking about it
er people but can purpose of machinei
b th Cys tallize
|Parpose:
This should be a brief on
bne oY wo line
|descripHon of what the Sgatem s Supported to do.
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Embedded Systems and I0T Design
formance:
mu
The computatios must be pexformed within
a certain time frame. 1 is essenial that the
pexfovmance requirem ents be idenife d ealy
Sìnce they must be care fully me asure d
Manugachuring wost:
This inc ludes primaily the cost of the
handware componens.Cost has a substant'al
in fuence architechure ie) A machine meant
to sell at LO most likely has a very ditferent
interoal struchuve than a
$Loo system
Power:
The nost in portant deision is whether
the machine will be battery powered or- plugged
into 4he all.
Physical size k weight:
Give sorme indicatien
the pbysical Size y
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Embedded Systems and I0T Design
Speciftctions:
The speification should be understandable
someone venfy th at it
encugh So that Can
em req uiremenz and overall
mee syt
expetatos of the ustomer. A speification
severae
of the GPS system would include
:
components
Data received from the GPS satellite
costellatio.
Map data
User Tnterface
tios that must be pe fomed to
Opera
Satis t ustomex regues ts.
> Background ati os regured to keep
, as operating the
the sytem Tunnig such
GPS TeceiveY
Architecture desiqn :
GPS Search Renderet |pikplay
receiveY} engine
User
Databat Dntefa ce
fig: Block diaqam for the moving map
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Embedded Systems and I0T Design
Power
Supply
Console
yrtem setup
Message
Header Addres oromanl £Cc MobnReceiverf
Track
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Embedded Systems and I0T Design
Requisement:
console shall be able to control up io
fe
on a Single track.
trains
The špeed of eca ch
train Shall be contoilable
in
b a thyet tle to atleast 63 different levels
éach diyeiion.
shall be an inertia control at sh all
There
alloe the user to adjust the responsiveneis of train.
The inev tia control wilI provide at leas t
.
eight different levels
.
There shall be an emergency stop button
Ar errOY detecfion scheme. will be used
to tras mit messages
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Embedded Systems and I0T Design
DCC:
The Dgital (Dc) standard
Command Control
time
58 Jus Zlcos
Bit en coinq. in,
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Embedded Systems and IOT Design
Keqular expression:
P is the preamble which is a sequence
of atleast (o I bit.
S is the packet start bit; it is a o
bit
.
in a l to I satio
Command
E stop
Set -speed
valu e:intge set -inertia
value
unsiqned intege
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Embedded Systems and I0T Design
J..n:lommand,
tongole :receiveY
MoloY
Panel Formated Tras mitHey Receivex ontvollex |iateae
*= physica
objet
39A YML class diaqram for the train controller
conmposition of the subsystem
-
Shouing he
The cont rol class des cribes the command's
urit front panel.
in cludes behaviors
• The formatter class .
oan el
that kn ow how to read the
po
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motor.
the • Detector * deleck analog signals on the
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Embedded Systems and IOT Design
.
produeb b 3 to b onths After that you will
never make mon ey For ex ample, calalators are
sold starb After that you
jus t be fore school
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Embedded Systems and IOT Design
5. Design Flows
Avchitec fure
coding.
Testing.
fiq:The Maintenance
ater fall thodel of softwue develapmant
Sgstem feasibikty
Specificaion
Prototype
Dnital system
JEnhanced Syete
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peuigy Speuity
Axchitect Architet
besign Desigh
Build Buid
Test Test
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Embedded Systems and IOT Design
Avchitectre
Hardwave Software
design desigr
Dategakon
Sytam teat
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Embedded Systems and I0T Design
cf Several element
• (ross functional teams include members
jrem vavious disiplines invclved in the Process
design
including ma nufacturing har du.ore &softaye
process activities
Conuvrent produd vealization
are at the heart vf conurYent engineevinq
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vi) Modifiability:
The requirernents do ument should be
structured so that it can be modified to meet
y
ehanging vequirements witheut lesing consisten
vertfiability and So on
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Embedded Systems and IOT Design
7. Specificatons:
State based specificafion fhat tntoduced
Some iinportant con cepts..
(Telephene
State Dnhook
oFf-hook |
Output
Caller gets
Task dial ton
Decision
Dial fone
Save
Language symbols
Grvaphical speaiftcation
tiq: the sDL Speufeation (anguage
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Embedded Systems and IOT Design
Traditiopal
Statethart
Hg: An oR
state in steel statecharts .
sab
Sa Sb
Traditi on al
State chart
ft4: An AND state 'in State chart
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Embedded Systems and IOT Design
.Create so
Some usage ScenaY iOS
Hoor, and qets out when the cay reaches that floor
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Embedded Systems and IOT Design
q. Quality Assuran ce :
The quality of a preduct
Produ ct or seYvfce can be
in ten ded
Juaged by how well t Satsfies itb
junction.
Qualty Assurance (RA) process
s
The
vibal tor the delivery of a satisfactry system.
of
Quality Assurance Technigues:
Organization
The Dnternatonal standards
of quality standards
a set
(Iso) has cre ated
q000 was Created to
Known as SO go00. TSoT
apply to a broad
range of industries ,incuding
em bedded hardwa k software
but not limited to
The follow ing obser vatio ns about quaity
manage ment based .On. DSO q000:
:
) Process is erucial
to
Haphazard develo pnent leads
haphazard product and Low quality Knowing
what steps are
to be followed to-create
higlh quali ty product is essential to ensuring that
are in follewed.
al the necessary steps in fact
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Embedded Systems and I0T Design
:
iy Dournentatior is important
The
Goumentattcr has severa! roles.
creation ct tte doument describing processes
helps these invelved urderstand the proLess junder
-
stand the process and hew they a
re being
implernen ted.
ii) Comm
unication inpertant:
euality uttirnate ly relies on people.
G10o d de unentation is an aid for helping people
understand the total quali ty proces s .
d.Repeatable
This level prorides basie tracking
manage ment to understan d!
mechanisms that atlow
cost, scheduling and goal achievem ent
3- Defined
The management and engine eving
Processes are dourn ented and standardized.
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4.Managed: measuvemens
This detailed
ph ase makes
lopment
development process and produet qualiy
of the deve
5. OpHmizing:
At the bighest level, feed back from
detailed me used to continually
asurements is
ss es.
Im prove the or9anization's proe
Verijying the speufication :
specifica tion are
The req uirement and
the design preces
qenerat vevy'
ed early in
requirernentt & speufiation
Verifying the
simple re asQh th at
very impovtant for the
s
he requiremnt or speaticatien
bug in
expepensive to fi later n.
be extremely
bug, if not foun until after
d
A coding
to mon ey real|
system deploym ent wil cost
reprogram systems among ofher thing
and existing
Time
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Embedded Systems and I0T Design
Design reviews :
The desi gn revieuw is a citical component
f any tess. "The design review is a simple,
QA preo
te catch bugs
kow cost way te early in des ign precss.
bugs early
destqn review is
A is simpy a bmeeting in
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Embedded Systems and IOT Design
choesing a
platform:
The hardware archi tecture of the platfor m
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Embedded Systems and I0T Design
coro ponen
) Support k:
These are critical to makng use of
complex hardware platforms. without proper code
an d deve lopment of operaing systemss the
hardware
itself useless.
is
Intellectual property:
Totellectual Property (IP) is that we can own
.
Development enviYonmens
Sostead of using evaluation board for softuare
development It is done on a PC or uwoykstation
known as host. The hardware on which the
code wil
finally Tun s known as the tarqet. The
host and target are fnally onngcted by
SB ink; Efherhet can also be used in higher speed
Liok.
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Host system
Sertal
port
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Embedded Systems and IOT Design
Debuqging techniques:
AA qood deal of sof tware can be
debuggig
done by compiling and exeuting the code on a PC
or workstation . Embedded systems are usually
less jriendy programming envirenments than Pc.
Tbe UsB port found on, evaluation oard
of the most important debug qing toolk. USB
Can also used for diaqnosing problems in the jiela
jield wp 9rades.o softo are
Another very important de bugging tool is the
break point. The simplest form of a breakpeint is
speut an adAdress
|for the user to speify address at which the
proqranm's exeuution is to break.
Debugging challengesi.
Logical errOrS in software can be hard to
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Embedded Systems and I0T Design
.
teAsume eteteies aeitete+
• emmunicaticn:
Ccmmunicatios may be relatively
to a bost mputer
Sims!e Such as a USB interface
ConsumeY eiectronic devices must meet
non funcional req uiremen ts
Several types cf strict
as well. , theyi
Many devices are battery operated
strict energy budgets
must cperake under
Co su mer electrooics are very inexpensive
sor $io.
A typica primary Processing chip must sell
e. mance .
These devices must also provid high perfor
power up interface
connect
ot Synchronize)
File syster
UseY Host
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Embedded Systems and IOT Design
2lo devices
CPU DSP
Networ
irkerfaue
Storag+
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Embedded Systems and I0T Design
•
read from the memory
• transfer over the bus to the cache
fer from the cache to toe CPU.
tras
CPU
Memory
cache
Data transfer!
Bus
d'g: Plat torm - Level data tous k performance
The time required to transfer from the cache
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Embedded Systems and IOT Design
2 B
(6M
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Embedded Systems and I0T Design
and a & bit wide memory have 8 mitl ion addres ses
The oemory system width may also be
determin ed by the memory mo dules we use
Instead;
of buying memory chips individually , may 'we buy
imernony as SIMMs or DIM Ms
The situation is
ligotly more complex,it
the data types don't fit natuYally into the width
ofthe memorY The total number of access es
Teequi re d to yead E data elemens of w
bit
each out of a memovy of width w is
A [(a).modw+1 .
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Embedded Systems and IOT Design
I. ARM Processor:
ARM does notmanufacture i5 cwn chips j
licenses ik architecture fo corn panies who
rather it
or inteqrate the
either nanu.facture the (PU itse If
ARM pcceSSoY io to a larger system.
The tex tual desevip tion of instruetios
an
oppose d to theiy binary represen tation is called
astem bly anguage
ARM instructions are written one peY line,
the first lumn
Commen beqn
starting after
with a Sermicolon andd continue to the end of the
line. A label which gives Dame to a
ernog
m.
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Embedded Systems and IOT Design
bits keng 3
.fhe standart ARM LweYd is
• (he
vrd may be divided into feur -bit S
byles
ARM1 allows addresses to be a bib
An addvess re
fevs to a byte, not a word. Therefore
the
T6e ARM proce ssor Can be confiqured at
pouer up to address the bytes in a word io either
ittle endian or biq endian mode
Bit 31
Bito
word 4
Byte 2 Byte Byte o
i
Byte 3
word o
Httle endian
Bit 31
Bit o
word 4
te o Byte By tea!
By By te 3 word o
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Embedded Systems and IOT Design
2
Instruction set:
3Aritbo ettc and loqic cperatirns in C are
varíables Varia bles are implemenked
.
in.
performed
ds merncy ictaticr There fore. to be able to
ite insiruciicra te perforr C expressics anda
T4 31
YS CPSR
T6
Y7
NzCV
TIO
YQ
YISCPC
ftg: Basic ARM programmin model.
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Embedded Systems and IOT Design
ta instructi on
The basie form ofa da i
simpie
ADD Add
w
ADC Add ith carY
SUB Su btract
SBC Subtract with carry
RSB Reverse subtract
RSC Reverse subtratt with carry
MUL Multiply
MLA Multiply cnd accurmulate.
:
|Logecal
AND Bitwise an d
ORR Bitwise or
o
EOR Bitwise exclusive
BIC Bit clear
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Embedded Systems and I0T Design
Sr.ft/rstale
Saubt rartier
with the
th crder
wo operans reversed ,sc thaf RSe
and ta sets ro to be ra- YI.
"The bitwise kogical cperaticns perform
dogical AND, OR andXOR Opera hiors
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Embedded Systems and I0T Design
ro, I,Y,Y?
MIA
Seb
o
to the vaue riX Y2 +r3.
sepa rate
Ihe shift oper atiors are not
,
which nay be applied to aritmefc
instructory.
.
tions
and logical instruc
ond Lsk modifies perforn left
*The sSL
CMP Compare
CMN Ne qated compare
TST Bitwlse test
TEQ Bitwise neqated test
MOV Move
MVN Move Neqated
Move Instrucfios- ARM
geneval
The Comparison opevands do not modify
purpase registers but only set the values of the
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Embedded Systems and IOT Design
of4
The instucton MOV Yo,rl sets the value
MVN instruction
Yo to the urrept value l. he
|com plernent the opevand bis during the tmove.
LDR Load
STR stove
LDRH Load half word
STRH Stove half word
LDRSH Load halfword signed
LDRB Load by te
STRB Sore by te
ADR Set register to addvess
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Embedded Systems and IOT Design
PC
Regisler
bank ines
Instrucion
rol
bus
Muti pliex
Deoder Cont
ALU bus
bus
Shift
A
Dnstrucion
Reg
ALU
Thumb to
ARM
wtite Data vegRead
date fransiaor
Teq
D3:o]
Features:
Large unijo m
register file
Load / store archite kure (ony register
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Embedded Systems and IOT Design
3. Assernbly , linking
and loading: 30
Hnker
Exeution Executable
Loader binary
object ode.
The assembler takes care of instructon
ts and does part of
tormats the job of trans lating
labels into addyesses
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Embedded Systems and I0T Design
y The 3-12.
pass scans the code to determine
fist
the address
of each label.
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inking 3- )3
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ApR a B label 3
B label
Varl
/. lo
File I
a
File 2
tiq: Extern
al teference s and en txy point
The linker proceeds in fwo phases.
Cbject code design:
We ne ed to Con tro J
the placement of sevaral
types of data:
.
Interrupt vectos and o
ther informafion
tor Tlo devices must be placed in
specifte
ocatios.
Memog managenent tables nust be set
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Embedded Systems and IOT Design
proqvam
the results of ei ther call. Jy the
changes the value of qlobal variables, it may qive
ohen it is called recursively
.
different asers
program is re locatable if it can be
A
be necessaxy to.
Some ases, it may
use nonrelo catable address Such as when
.
addressing Cn Tlo device
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Asuntly vode
Code Such as C
oand generally produces
as sembly ode
The high level language progam is pavsed
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alo]
ar
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a[o,o]
alo,]
all,o]
ali,]
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Embedded Systems and I0T Design
Compiler optimizatiers:
Baste compilafien te chniques ceute
ineffuent wde
.Compilers usc a
Can
wide ranqe
.
y
algori thmd to optimi Ze the code they oyeneva te
A
simple but useful transformatien is
known as loop unrolling Tt impertant
because it helps expose parallelism that Cn
be used by later stages of the compiler.
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do eithex o r
last but bu we can ddi tion subtractou
first...
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Embedded Systems and I0T Design
|Performan
ce
and once agaun the cache's behavior
on input to
dependa in part the data values the
|Progtam
Cache
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Embedded Systems and I0T Design
bus
c cun
be uSed to me asuYe pexfovmanc e of
executn sectios of code.
analyze* can be connected to
•A Logie he
microprocessor bus to measure the start and
stop times of code Segment
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Embedded Systems and IOT Design
3 -24
This is the typical exeuti on ime
we
wbuld evpect for typical data Clearly. tke
) WorSt cas e :
exeution time
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Embedded Systems and IOT Design
3-5
The sinplest estinate of instructton timing
{s fo that every instucton takes the
as sume that
Same numbe of clock cyele
yeless ie) we need only
count the inatuctons
and multiy by the per
in sHvucion exeution time to obtain Ae proqram's
|total exeu tion time
• Not all the tstructors take the S ame
amount f time.
•
Exeution tmes of isructios are not
independent.
• The
exeution time of Qn instuction may
mag
depend operan d values.
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Embedded Systems and I0T Design
3-,
detaled simul atior f thc prot essor ' intenals i
:
Loep Opimizatios
Loeps are inpov ant target fo
optini zatton
because programs with loops tend to spend a lot
cf ine exeuting these loops
there are three important techniques in
ophimizing oo ps :
code notion
induction variable elimin ati on
strength reduc hion.
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Embedded Systems and IOT Design
3- 8
templaN* M;
KiZNM2 Ltenp
F
T
T
z[iJe aci3+ B01; z Cij=a[i+b(i];
i++) t+)
Before After
fa: Code motion in a loop
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Embedded Systems and IOT Design
=
*Eptr +zbinduct ) * (bptr +zbinduct );
zbin duct ++;
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Embedded Systems and IOT Design
the segment
,
• For scalar data conflicts move the
to Te duce
vaues to di fferent locatios
data
con ficts
• for data
aYYay conflica, consider
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Embedded Systems and IOT Design
3-32
instuctHon
fvom inst uctton to
sequence of instruchons has some
Ihe
inguere location of the
.the opuode and the
matter
operands also
Amneter
Current
CPU
but concecentrating
on the instruction opcodes has
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Embedded Systems and IOT Design
3 -33
irnportant factor
en e8g in
Caches are an
energy coMumpi on
TE 4he cadhe is too small, he proqrams
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Embedded Systems and IOT Design
The memony
ofa prrgram
footpuiod
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Embedded Systems and IOT Design
3-35
when
educing the numbex of instructtos in
,
a Pogvan one toporiant technique is the preper
use of subroutines T{ the program performs
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Embedded Systems and IOT Design
3-36
|9- Proqram Validation and Testing:
ensure
Systes need testing to
Complex
:
intended
|th at they work as they are
We carn use various
Combinatiors
of two
rmajor types of testing
stvategies.
|
Black- box methods qenevate tests witout
) program.
structere of the
Looking at the internal
knowon as wbite box,
i) cleaY-box also
tests based on the Program
methods Jenerate
stuctue.
clear box testing:
low qraph extracted from
The contol /data f
an important hool in
SouYce tode is
program.
clear -box test for the
developing
these
Ihorde to exeute and evaluale
we must be able to control variables in he
tests,
program and observe the resulis of computatiors
ruch as in manufachuring testing Dn general we
heed to modify the program to make it more testable
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Embedded Systems and IOT Design
3-38
[Mec1
A sinple measuTe, yelonatie complexity
all ows us to measure the control complexity of Hhe
n number of nodes
graph
p number of com pon ent in the
a b d e
d
e
Graph
hiden ce mafrix
a b d e
Basis set
ta: Matix esentation
f graph A basis set.
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Embedded Systems and IOT Design
3 -39
3
hb
v
(a) -8-6+3 =4
Compleci ty
Sg: ydomate
Ahother way of ooking at control flouw oviented
branch testing
Frankl and weyuker (Fra 8a) have defined
fo exercise
eriteria for choosi ng which def-use pairs
to sati g well behaved adequay criterion
cwe
there are several Important cas es hat
should ty at a minimum
:
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Embedded Systems and IOT Design
3- 40
•Skipping the loep entiYey
6f loop
iteraions that bs n-) hh +.
a glven
Random values are genevated
with
box test.
distribu kon The expeted values are computed
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