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Embedded System and IOT Design Handwritten Notes-1

The document outlines the design process for embedded systems and IoT, emphasizing the importance of microprocessors in various applications like automobiles and household appliances. It discusses the specifications, requirements, and performance metrics necessary for effective embedded system design, including considerations for manufacturing cost, power consumption, and physical size. Additionally, it provides a design example of a model train controller to illustrate practical applications of these concepts.

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nish1997t
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0% found this document useful (0 votes)
259 views87 pages

Embedded System and IOT Design Handwritten Notes-1

The document outlines the design process for embedded systems and IoT, emphasizing the importance of microprocessors in various applications like automobiles and household appliances. It discusses the specifications, requirements, and performance metrics necessary for effective embedded system design, including considerations for manufacturing cost, power consumption, and physical size. Additionally, it provides a design example of a model train controller to illustrate practical applications of these concepts.

Uploaded by

nish1997t
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Embedded Systems and IOT Design

ET3491 EMBEDDED SYSTEMS AND IOT DESIGN


UNIT II EMBEDDEDSYSTEMS
- -
Embedded System Design Process Model Train Controller - ARM Processor Instruction Set
- - - -
Preliminaries CPU Programming Input and Output Supervisor Mode Exceptions and Trap -
- -
Models for programs Assembly, Linking and Loading- Compilation Techniques Program Level
Performance Analysis.

UNIT II

EMBEDDED SYSTEMS

Complex Syetems and MicroprOces sors:

frnbedded compuir system is defined


ab any device that includes
prograomable
Cornputer but not itsef inlended to be
K

|CA. geneval. puvpose Computer. Thus a PC s not ,

|itsel{ an ernbe dded con puting system although


PCs aYe often used to build embedded
computing systems
This means that enbedded computing syste
desigh s a useful skill for many types of
product design
Automobiles, cell phones and eveh bouse hold
appliances make extensive use of miroprocessors
ComputeY engineevinq like mechanical
design thermodynamics is fundam ental
dis ciplin e that can be applied in defferent
domais. But embedded Cormputing System
desiqn does not stand alone.

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Embedded Systems and I0T Design

Te Est ipertzot and scpbisticated use

t nicTc TCceiss tmcbi!e was to contrc


1n au

engire detevniring wten spak plgs fire,


contvelling the fuel
a aiY mixture and so on.
,
Thene twaS a trend in qereval eleiror ie deviceg
ceuld be uied to Teplae the mechanical distribu to r
The combin atio c4 iou fuel consumpti on
to achieve ;
Very
iuit
to mit thise joals 2utemcble marfacturers
tuined to Sophisticated
Sophis ticated contiel
alqoritnm that
cold be implemerted cni uit micreprriessers
Micrprrcss ovs usually classified by
their woYd size.

•An g- bit micve controlle S designed


tor oe ccst applicateos and ire(udes n board
-
nemey and I|c devices
A tb bit micvocenteller is cften used
Jor sephistented aplieatis that may egure
either lcnger wca lengih
•A 32-bit RIsC micvoprcceSSor
fevs
very high pexfovmance ge
e mputakon - intensive
pplicati ons
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Embedded Systems and I0T Design

RMW Nnoi nake nd staalily contvol system:

sephidi eoate.(
šiophidi cated syet em fon conlaotiry the wheels
syst emm (AB s) reduces
tay. An nlilock xake
skid.ng ig pempinq the bvakes
utomalic. slability tonol (Asc+)
An
inlervwnes widh the engire during maneuveing
ytem
systems
le inpeve he car ' stability. These
nqune ink fhmm and output to automobile.
ihe As Sensors on ea ch
syslom tu.ses

theel to neasuve the. speed of the wheel


>
to
prevent the wheels fvom skidding
Sensor Sensor

iydvoulic
Brake pump Brake

ABS
Brake
Brake

Sensor Sensor

Anti-lock brake system

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Embedded Systems and I0T Design

The engine and contaol man agenent unit


include
,
the eleetonically .onlrolled throttle digita
engine management and electronic Iransmis sion
contaol.
b Funckionaliy mportant
i in both geneval

|Purpose computing and enbedded computing.


* Compiex algoritms
mtero -
The operafios performed by the
PAocessor may be very sophisticated. For example,
|the microproces soY that conteots an autombbile
engine must perform conpli cated flkering funcond
Such as minimizing polution & fuel utilizahon .
* User.Inter face:
Micropo ceSsors are
totvol complex user interfaces that may inctude
|mul tiple menus k,many optons eg) GPS.
iTo make thing more difflalt , embedded
computingtems have to meet deadlines :
:
* Real time
Many embedded compuking ystems
have to perform in real time Dn some cases,
the
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Embedded Systems and IOT Design

erdan2ar ves tter sAes; ereate urhatt


CustonerS ee) tan res!* SararpiEd. pagea
x
Multiyate :
Net en
ust eperaiena ée enç'eted iy
dead lin es but many embedded computng yters

hare severai veai hine actvites gcirq on at


Same tme. Thcy may simtt an ecusly cntol
oper aibrs that Tur at slow rakes ard.
others at iah Tate e-g) mult rncáia applicaters
iiy Cost cf varibus Sorts ane also very
inportant:
Manutacring cost :
The total cost of building the system
.
s very innporfant 1t is determined by iccuding
the type of micro processer used ,anount of
memovy vequired and types of IJo devices .
* Poue and nergy:
Power congumpton divectly affecb the cost
of hardusare ie) lange power suppy
needed
Energg cors unpton
ffec o battery life
which is important in deskfop appli
cations
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Embedded Systems and I0T Design

2. Embedded Sys tem Desiqn Process:

First, a desiqn to
ensure that we have

done evergthing we need to do Such as aplirizig


perfovmance or pexforming funchonal tests.
Seond, it allows us to develop computer
aided design toos
a design methodo logy makes it
Third,
a design tecom to
much easierfor members ot
Communicate
from the top-down conctudes
Design
with concrete details the altev native is c
bottom -up view in which we
start wih component,
to build System
Requirement , Bottom -up
Top- dowh
design
design (Speiftcation

(Architechre

Compon ents
System
Dntegraion
f4:Major levels of abstrachon in the desiqn proies
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Embedded Systems and IOT Design

To comsider the major qocal: of the desiqn:


Manufacting cost
Perfoman ce
•Power cons umption

Requirements:
Requirementt may be functional
funchiona Typicad non funchon al requiremens
incude:
Performance :
1t may be a combinatio
Of Soft performance metrics such as apprima te
time to perjorm a user level funetion and hard
deadlines by whi ch a pauti el ar operati may
be comple ted.
• Cost :
Cost typicatly has kwo major
-
Component manufactving cost an d nonYeurring
engineerinS (NRE) cost
Physical size and weighti The physical
final sgetem Can vay greaty
depending upon the applicahon. A hand held
device typrcaly has tight requiremens on bot
Size and weight than Can Tipple through entiie design
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Embedded Systems and I0T Design

• Power Cons
uphion: Power is important in

bottery powered sytes and other applicaions


-
as well
Name
Paxpose
apub
Outputs
Func hons
Performance
Manufacting tost
Power
Physical size & weigbt
Sample equivemen t form
Name :

This is
siople but helpful. Giving a hame to
to
the project not only simplifies talking about it
er people but can purpose of machinei
b th Cys tallize
|Parpose:
This should be a brief on
bne oY wo line
|descripHon of what the Sgatem s Supported to do.

Inputs and out puts


TA descrt bes
the buttons, analog /digital
cobverters video displays.

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Embedded Systems and I0T Design

formance:
mu
The computatios must be pexformed within
a certain time frame. 1 is essenial that the
pexfovmance requirem ents be idenife d ealy
Sìnce they must be care fully me asure d

Manugachuring wost:
This inc ludes primaily the cost of the
handware componens.Cost has a substant'al
in fuence architechure ie) A machine meant
to sell at LO most likely has a very ditferent
interoal struchuve than a
$Loo system
Power:
The nost in portant deision is whether
the machine will be battery powered or- plugged
into 4he all.
Physical size k weight:
Give sorme indicatien
the pbysical Size y

of the Sgtem to help guide certain architecural


deisions. A desk to p machine has much more
,
|Hlexibi liby the componenk wsed than -foy
in

ex ample, a lapel mounted voice


recoder.
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Embedded Systems and I0T Design

Speciftctions:
The speification should be understandable
someone venfy th at it
encugh So that Can
em req uiremenz and overall
mee syt
expetatos of the ustomer. A speification
severae
of the GPS system would include
:
components
Data received from the GPS satellite
costellatio.
Map data
User Tnterface
tios that must be pe fomed to
Opera
Satis t ustomex regues ts.
> Background ati os regured to keep
, as operating the
the sytem Tunnig such
GPS TeceiveY

Architecture desiqn :
GPS Search Renderet |pikplay
receiveY} engine

User
Databat Dntefa ce
fig: Block diaqam for the moving map
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Embedded Systems and IOT Design

handwAe k software Componens:


Designinq
To desigo Some componen ourself.
when ceating enbedded software modules,
of your experti
se ensure that
to
make use
the system propery in Teal time anel
does not take up more menoy spae than
s allowed.
System Integration
is difficut because it
Sgtem Tntegration to
problens.
covers 14 ib often hard
usual by un
detail to
jobserve the system in suffient
wrong with debugg ing
jdetermine enaty what is

fauliti es desktop sytema


:
3. Desiqn Exam ple Model Train Controller

The user sends messages to the train


con
wilh a
trol box attache d to the tyacks.
The contro box may have controls
Such s throttle, emerqehcy stop btton and
So on
Since the trin Teceives its electnical
,
Power from the hwo Yails the track th e
ontrol box Can Send si g nals o the train
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Embedded Systems and I0T Design

Tke control panel serds packet oVer he


tyacks tb the yeceiver On the ty ain.
Each packet includes an addvess so that

the comsole can control


speed of Seveval trais
on same tra ck; t6e packet also ioc ludes an
EY YOY CorrecHon Code CECc) o juond againat
trasmission erro YS
This is a
One ocg com munication

Power
Supply
Console

yrtem setup
Message
Header Addres oromanl £Cc MobnReceiverf

Track

Sgoaling the train


Console

fa: A nodel train control gtem


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Embedded Systems and I0T Design

Requisement:
console shall be able to control up io
fe
on a Single track.
trains
The špeed of eca ch
train Shall be contoilable
in
b a thyet tle to atleast 63 different levels
éach diyeiion.
shall be an inertia control at sh all
There
alloe the user to adjust the responsiveneis of train.
The inev tia control wilI provide at leas t
.
eight different levels
.
There shall be an emergency stop button
Ar errOY detecfion scheme. will be used
to tras mit messages

Name Mdel train ocontrollers


Control Speed upo model trains
Purpose
Thyottlesiner tia setting, Stop butcn,trar a
Tnputs con tvel
Train sienals
Outputs
set engine speed based upon
Functions ,
ir ertia settings respond to
emergeny cthp
Can update train speed totmes setcrd
Performance
Manufacturing cost $50
Power
Getr Console should be ecmfprtabe
Physi cal sixe eweight for hwo hands, approxirnale size
of std. key board ; weig bt 22 pounds
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Embedded Systems and I0T Design

DCC:
The Dgital (Dc) standard
Command Control

(http // www. omYa. org/standaada | Dec/ standayds rps


/Dccstds. html) was created by the National
Model Rairoad ssociation to support digitally
A

ontrolled nodel tris


The DcC standard is given in kuo documens:
• Standayd s-q.,
the Dcc Electrtcal
Standard describes hoc bits are encoded on
the ais foy transmission.
Standard s-q., the Dcc Com munication
,
Standard descvibes the packets that carry
information.
The data sigbal
signal suings
suina between too
|voltages around the pouer suPp'y voltage.
Bib ae encoded in the time between trasitions,
not by vo ttage levels.
PSA (SD) +E

time

58 Jus Zlcos
Bit en coinq. in,
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Embedded Systems and IOT Design

Keqular expression:
P is the preamble which is a sequence
of atleast (o I bit.
S is the packet start bit; it is a o
bit
.

address which is eight bis long.


The addresses 00
Q00b0000, ||WD & |W as2 TeseYved.
s is the data byte start bit ike the
packet start bit is a O.
Di the data byte which includes anybits.
E s a packet end bit which s a Bit.
Conceptual specifiakion:
allows us to
A
conceptual speification
A train
upderstand system a ittle
the better.
control system commands into packek.
turs
and packets may not be gen rated
e
Cotn mands

in a l to I satio
Command

E stop
Set -speed
valu e:intge set -inertia
value
unsiqned intege

class diagr am for the train controlleY messaqe


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Embedded Systems and I0T Design

J..n:lommand,
tongole :receiveY

fgUML catla bov ation diagram foY major subiyst ems


of the train contvolley yotem
Train set
Documeota
only
t
Console Train

MoloY
Panel Formated Tras mitHey Receivex ontvollex |iateae

Knob* Sender* ]Detecor Pulse

*= physica
objet
39A YML class diaqram for the train controller
conmposition of the subsystem
-
Shouing he
The cont rol class des cribes the command's
urit front panel.
in cludes behaviors
• The formatter class .
oan el
that kn ow how to read the
po

• The transmitter class interfaces to


analog electyonis o sen the mesage along tetack
d

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Embedded Systems and I0T Design

• knobs * describes the actual analog knobs,


buttors and levevs on thecontrol panel.
• Sender * deseri bes the analoq electroni s
that send bik along the track
to turn the
the Receiver class knows how
Jovm
analeg signas on the track ino digital
• The motor intey face elas s defines how fo

Jenevate the analeg signads required to control

motor.
the • Detector * deleck analog signals on the

tack and con vey


to
them info digital gorm
• Pulser * turns diqital commands into the
mohor sped
ianalog signals requived to control the
:
4 Desiqn Methodologies
Design methode (ogie s s itaporant beau

without it, we can't rel iably deiver the Product


want to create ·
i)
Tine-to- maYket:
Customers always w ant new features.
The product that out frst Can win the
mauket The profitable market life foY <ome
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Embedded Systems and IOT Design

.
produeb b 3 to b onths After that you will
never make mon ey For ex ample, calalators are
sold starb After that you
jus t be fore school

have to wait for anofher sales season.


iy Desiqn Cost:
Many customer products are verg
cost sensi ive. Tndustrial buyers are also increasingg

concevned about ost. The coss are distinet


frorm manufacturing Cost, enqine
e
's salavies,
Cormpute used in design and so Design
volume
Costscah also be inportant for high
cosumer der'ces when time fo mauket pressures
Cause team to Swell in size
tö) Quality'
CoestomeYS not ony want their
w
ant them to
pro ducts fast and cheap, they also
be right A
that cranks
desin methodology
out shoddy produ cs will Soon be forced out of
the marketplace. Corre ctness, eliability and
|usability must be expliitly addyesse d foom the
beginning of the design job to obtain a higk
|quaity product at the en d
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Embedded Systems and IOT Design

5. Design Flows

A design flow is Sequence of steps


to be folewed duving a design Some of the
a
Steps can be performe d by took such as Compilers
,
OY CAD Systens other steps can be perfrmed
by han d.
Requi rement

Avchitec fure

coding.

Testing.

fiq:The Maintenance
ater fall thodel of softwue develapmant

Sgstem feasibikty
Specificaion
Prototype
Dnital system
JEnhanced Syete

Sysfem life ycle


Requirem en
e ts
Design Test
tuaxe.desiga.
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Embedded Systems and IOT Design

peuigy Speuity
Axchitect Architet
besign Desigh
Build Buid
Test Test

Jg: A successive vefinement development model

Eaxly systemt will be simple meck ups constructed


to aid desiqp ers intuihon and to bui ld expeviene
.
ges the designers
with the system At each level sta wshen habre
thyouqh Oreqiremen cons
eorpletetersiond the
of systers tru ction and testing
phases. At later stages more complex sy tems
,

ane comstru cted ) each phase requres moTe work.


The first cycles at the top of the
spiral are very sroall and short while the final
cycles at the spiral's bottrm dearned from the
earlier yeles of the spival
The spiY al model s more Tealistic th an

the watey fall model beause multiple iterations


needed to complete
e
design
Embe dded computing system involved the
design of hasdwae as well as softwae fron t
end acti vities such as Speification andd
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Embedded Systems and IOT Design

architechYe simultaneously consder hardware


and softwae aspecta
r, back end integration
and testing consider the entire
Requivemens a Jpeugicatien

Avchitectre

Hardwave Software
design desigr

Dategakon

Sytam teat

fg:A sin ple hardusare |softuwave design mettodology

The desiqn floeo gollows the levels of abstraction


at
in the system grom compleke sytem design f lous
nast
most absty act o
to desiqn flows
jor individual componen
the
Requiyemets
speufications Speifiuaton
speification
Avchitechuse
tHarduware architectuve archifechure
|Sojtars
Havduatsoftwe
Aesign desiqn Detaile Anotte Module Anoker
|design design design
yele design cyle
Least
abshrac Least
Dntegrafien abstra
Totegzaton htegyaien
system test
Most
Test
abstacf
Moderately -IModerately abstract
st
abstrat
tig: A
hierarchical design flow for an embedded system
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Embedded Systems and I0T Design

Concuvvent engineering efferk are Compvi sed

cf Several element
• (ross functional teams include members
jrem vavious disiplines invclved in the Process
design
including ma nufacturing har du.ore &softaye
process activities
Conuvrent produd vealization
are at the heart vf conurYent engineevinq

.Incremental in forrm ation sharing and


helps minimi ze the chance that conurYent
wil lead to surprise
product Yealization will
Cross funconal teams are important to the
effedive sharing f informatien in a timey
sashion .

• Tntegrae d projet management ensuYe that


Someone is responsible for the entire project
• Earlier and continual suppler inv olvement
helps make the best use of suppliers capabi lites
Earlier and ontinual ustomex fous helps
ensure that the products best meets
ustomer's eeds

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Embedded Systems and IOT Design

6. Requir ements Analysis:


The over
al goal of cieatng a requirements
document 's etfetive com mun ication between
the
customerS and the desiqners A qood set ot
re quirement should meet several tests :
) Correctness:
The Tequivements should not mistakenly
deseribe what the ustomey wants. Part of
cosTectness is avo iding bv
bver vequiring
:
") Uhambiguoushess

equrement doument should be


The
clea and.have enly pne plain, language, interpretaion;
:
iiy Completeness

A. req irem ents should be inch ded.


iv) Verifiabiliy:
These should be a cost effective ay to
ensure that each vequirernent is sati sfied in
pro duct.
the final
y Consistenty:
One re ui
vement should not ontradict
another requirement .

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Embedded Systems and IOT Design

vi) Modifiability:
The requirernents do ument should be
structured so that it can be modified to meet
y
ehanging vequirements witheut lesing consisten
vertfiability and So on

vii Trace abi lity :

Each equirement should be traceable



backward frem the Yeq uivemen ts to
knew why each requirenent exists.
forward from dounent created
before the requirement.
understand how each
•forard to
:,
requirement is satisfied in the implem entation
• backward from
the implementation
to know which requiremen they were intended
to satisfi
TE the a continuation of sertes,
produet is

then many of the requirements are well


und ers too d.

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Embedded Systems and IOT Design

7. Specificatons:
State based specificafion fhat tntoduced
Some iinportant con cepts..

(Telephene
State Dnhook

Topiut Caller qoes

oFf-hook |
Output
Caller gets
Task dial ton

Decision
Dial fone
Save
Language symbols

Grvaphical speaiftcation
tiq: the sDL Speufeation (anguage

The statechart .notafioh uses an event-drive


model. State charts allows states ;be groupe t
together to show comimen functi on ality. there
are hwo basic qrouptngs and AND. oR

OR state by comparin a traditional state


g

transition diaqram wit a state chart. des cribed


va an oR state
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Embedded Systems and IOT Design

The state machine speiftes the. machine


goes to state s from any of Su S or S; when

input i2. A sinqle transition out of the OR states


S
la3 speifies that the mach ine goes into state Sh
when it receives ta input while in any stateinclude
in S123. There can be
.
mu
tiple ways- to get tnt
|SIa3. SI23

Traditiopal
Statethart
Hg: An oR
state in steel statecharts .

sab
Sa Sb

Traditi on al
State chart
ft4: An AND state 'in State chart
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Embedded Systems and I0T Design

An AND state specifted: in statechart notation

as to mpared to the .equivaleot ip the traditional


State m achine model. Th the traditional model,
there are numerous transifions between the states
and on e entay pornt.
The most imporfant difference be hoeen

the notation and statechayt is that don't cares


represeoted in the table.
Condl bY (cond2 and !ond3)
Expressioh
OR
Cand T
Cond T
cond 3 F
AND (oR table
8. Systern Analysis and,
Arcbi teeture,..Design:
The CRC card methodology
is a weil knewn
and useful way to' help analy ze syshem's stuctuve.
Tt is parti ularlg w ell su ted to objeet-oriented
design since. it encourages the encapsulaien of
data..and funetions
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Embedded Systems and IOT Design

The .acro nym. cRc stands for:


•classes define the logteal grouping
of data and functonality:
Responsibi li ties des eribe what the classes
do.
• CollaboratoYS are the other classes
with which a given class works.
The name CRC cormes from the fact that
the methodolegy is. practiced by having people
write on inde cavds
Tt has space to wwrite down the class
name) me, Yesposibi lities and colta boraors R
is
-
other in form ation
The essence of the cRC cavd methodology
is have people write on these cards talk about
to
caYds Lntil they satisfted|
|them: -and update. the
.
with the Ye sults
The following steps ane used to an ayze
Sytem:
Develop an inittal tist of classes
• Write an initial re sponsibilities
list of. k
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Embedded Systems and IOT Design

.Create so
Some usage ScenaY iOS

• Walk through the Sce nario5

•Refine the classes, Yesponsi bilities and


coll aboYa trs
• Add class relationships
CRC
card Analysts:
A CRC Card analysis of an eleva tor system

Real-wor ld elasses: elevatoy car passenger, floor


control, tar control & Lar Sen soy
Architectuyal classes: car state, floor control reader,
Car control read er, car contYol
Sender and scheduler.
The basic operation of the elevator system
well as Some unusual Scenarios :
. One passen ger request on
a
caY a
floor,
qets in the car when it arrives ,requests anothey.

Hoor, and qets out when the cay reaches that floor

2- Dne pas senger requests å caY on a floor

gets in the caY when it arrives and reques a


the fooY that the currently On.
3. A second passenger eques ta
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Embedded Systems and I0T Design

while another passenger is riding in the


elevator.
4. Two people push floor buttons on different
floors at the Same tirne.
5. Two people push car control bu ttos
in di ffevent cayS
cars at the Same time .

class Responsibilities Collaborators


:Elevator cart Moves up & down Car control, caY Sensor
car control sender
Pass enqer * Pushes flooy control k
ploor control, caY
caY Control bu ttos control
|Floor ontro| * |Trasmi bk floor requst Passenqer, Hoor conte
reader
Car lontro|*
Transmi b car reques to Passengex, car
contd reader
Car Sensor* Senses car position
positionscheduler
Car state Recovds urrent Scheduler, car sensor
pos
iton 0f car.
Floor ontol reader Tnterface bluw
toor Flocr control,
|control k vest of system sehe duler
Car control readeDnterface 6w car CaY control,
Lontrol Yest of syste 's cheduler.
Cat control senderTnterface blw'schedulet
an d, car .
scheduler, elevator
Car
Scheduler Sends ommands tocarsFloor ontvol reader, car
based upon vequesb |Controeader, Cay cote
Lobholsender,
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Embedded Systems and IOT Design

q. Quality Assuran ce :
The quality of a preduct
Produ ct or seYvfce can be
in ten ded
Juaged by how well t Satsfies itb

junction.
Qualty Assurance (RA) process
s
The
vibal tor the delivery of a satisfactry system.
of
Quality Assurance Technigues:
Organization
The Dnternatonal standards
of quality standards
a set
(Iso) has cre ated
q000 was Created to
Known as SO go00. TSoT

apply to a broad
range of industries ,incuding
em bedded hardwa k software
but not limited to
The follow ing obser vatio ns about quaity
manage ment based .On. DSO q000:
:
) Process is erucial
to
Haphazard develo pnent leads
haphazard product and Low quality Knowing
what steps are
to be followed to-create
higlh quali ty product is essential to ensuring that
are in follewed.
al the necessary steps in fact
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Embedded Systems and I0T Design

:
iy Dournentatior is important
The
Goumentattcr has severa! roles.
creation ct tte doument describing processes
helps these invelved urderstand the proLess junder
-
stand the process and hew they a
re being
implernen ted.
ii) Comm
unication inpertant:
euality uttirnate ly relies on people.
G10o d de unentation is an aid for helping people
understand the total quali ty proces s .

The jollowing five levels cf maturity:


(. Tnital:
A poorly erganized process wifh ver
feus well defined
processes. Success of a Project
depends on the effor of individuals
:

d.Repeatable
This level prorides basie tracking
manage ment to understan d!
mechanisms that atlow
cost, scheduling and goal achievem ent
3- Defined
The management and engine eving
Processes are dourn ented and standardized.

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Embedded Systems and IOT Design

4.Managed: measuvemens
This detailed
ph ase makes
lopment
development process and produet qualiy
of the deve
5. OpHmizing:
At the bighest level, feed back from
detailed me used to continually
asurements is
ss es.
Im prove the or9anization's proe
Verijying the speufication :
specifica tion are
The req uirement and
the design preces
qenerat vevy'
ed early in
requirernentt & speufiation
Verifying the
simple re asQh th at
very impovtant for the
s
he requiremnt or speaticatien
bug in
expepensive to fi later n.
be extremely
bug, if not foun until after
d
A coding
to mon ey real|
system deploym ent wil cost
reprogram systems among ofher thing
and existing

tig: Lonq lived


fix
bugs Qre more
to rement expensive to fon
Cost
Coding bug

Time
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Embedded Systems and I0T Design

Design reviews :
The desi gn revieuw is a citical component
f any tess. "The design review is a simple,
QA preo

te catch bugs
kow cost way te early in des ign precss.
bugs early

destqn review is
A is simpy a bmeeting in

which team members dis Cuss a design,evi ewoing


bow a Lom ponent of the system works.
A
design raieu team has the jellewing
mem bers:
DesigneS of the component
• Review
lea der
•Review Scribe
• Review audience
The desiqn team prepares
a set of doument
that wil! use d
descvibe the component. These
douument are Jiven fo other members in advance
of the meeting
The hotes tak en by the seribe are wsed
meeting follous p Thesign team shoutd
de

correct bg and address concerns ralsed at


the meetirg The desiqn review leader coordinatej
with the design team both to make Sure that
the changes are made and distribute the
chanqe results to the audience
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Embedded Systems and IOT Design

10. Desigoing with computing platforms :

The design complexity of the hardware platform


tends o
a highly us tomize d design A platform
may cos
ish of anywhere rom one to dozen of
chips
The Beaqle Board is the resutt of an open
Source project to develop low cost platfornm
The pYO CessoY 6 an ARM covtexTA&. The
board itself includes m
any connectors
and support
for variety of Tlo:
Chip vendoss
often provide their oun evaluation
Iboards br evaluation modules
for their chips . Tf the
evaluation bocrd does not meet your needs, you Can
medity the design using the nettist and boand layout
with out starting from scratch.

choesing a
platform:
The hardware archi tecture of the platfor m

is the more obvious nanifestafton of the archi tecfure


because you can touch it and feel it . The various
components may all play a factor in the suitabiliy
of the platform
i) Bus:
The cho (ce of a bus is closely tie d to
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Embedded Systems and IOT Design

that of a cpUy becuse, bus s an integral pant


of the nicroprocess or. But in applicafions, bus may
be moore of a limiting factor than the
cPu.

The ratio of ROM to RAM an d


seleetio of DRAM versus SRAM can have
bave a šiqnificant
influence on the ost of the system. The speed
of
|the memoy will play a large paat in determining
gten perfermance
i) Thput and output denices:
Platforms based on highly integraked
|chips enly cone with cer tain com bination of Tlo
devices. The ombination of t/o devlces avai lable
oa
|may be prime factor in platform selection.
There ae kwo cormponents available in the
|softwane platform - run time compon en ts and
|Support component
Run time componer

These are the critical pat of the


patform An operating system is used to control
the cpu and i muttiple proesses. A file system
is used in embedded syst em to orqanize d
ata.
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Embedded Systems and I0T Design

coro ponen
) Support k:
These are critical to makng use of
complex hardware platforms. without proper code
an d deve lopment of operaing systemss the
hardware
itself useless.
is

Intellectual property:
Totellectual Property (IP) is that we can own
.

but oot touch eq) software netlist


Examples of wide anqe of DP that we are
using in em bedded ystem design:
• run
time software libraries

5oftware development enviro nment
• Schematics, netlists and otheY
barduware
desigh infovma ton

Development enviYonmens
Sostead of using evaluation board for softuare
development It is done on a PC or uwoykstation
known as host. The hardware on which the
code wil
finally Tun s known as the tarqet. The
host and target are fnally onngcted by
SB ink; Efherhet can also be used in higher speed
Liok.
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Embedded Systems and I0T Design

The tarqet must inclu de a srrall amount of


software to talk to the host System. The host
should be able to do the
felleuing:

\oad pre qrams into the tavget
• start
and stop proqram exeutien on the
tarqet and
roemoy e cpU registers

A CVOSS cornpiler is a ompiler that runs on


on e type of machine but qenerates cde for ano ther.
, is
After Compilation the exeutab le code typrealy
downloaded to the embedded system by USB.

Host system

Sertal
port

CPU Target system

tg: Connec ting a host and tarqet system

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Embedded Systems and IOT Design

Debuqging techniques:
AA qood deal of sof tware can be
debuggig
done by compiling and exeuting the code on a PC
or workstation . Embedded systems are usually
less jriendy programming envirenments than Pc.
Tbe UsB port found on, evaluation oard
of the most important debug qing toolk. USB
Can also used for diaqnosing problems in the jiela
jield wp 9rades.o softo are
Another very important de bugging tool is the
break point. The simplest form of a breakpeint is
speut an adAdress
|for the user to speify address at which the
proqranm's exeuution is to break.
Debugging challengesi.
Logical errOrS in software can be hard to

track doun ,but errors in Yeal time. code ian Creat


even harder to diaqnose
problems that are Real

ttmeproqrams are requred to finish their work


within a certain amounf of time j they can
ore ate very un expected behavior.

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Embedded Systems and IOT Design

||. Consumer electronics architectuYe:


Consumer electronics devi ces has converqed
OVer te past decade around a set of Common
features that are Supported by lo mmon architectural!
features
Theve is no single plakform jor consumeY
electronícs devtces but the archi tecture in use ave
orgaun ized araund some comm on
themes.
This onv rergence is possible because
these devices implement a few baic types ot
functions in various combinations : mutime dia and
communi cations. These vequires basic aYchitectural
templates.
• Multimedia:
The media may be audio, image
video. These are generally stored and in compressed
|form and must be un compressed to be played.
The standards for audio is MP3 ,Dol by Diq i TM
sEG1 and for video, is
jor images s MPE Gi-2, MPEG+4 H-Q64 ; fkes s
• :
Data storage and management
Becuse people want to seleet what
multimedia objecs fhey Save or play data storage
goes hand -in- hand wit muttimnedia capture and
display Many devices provide PC compatible file
sgotems So that data can be shaved easily .

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Embedded Systems and I0T Design

.
teAsume eteteies aeitete+
• emmunicaticn:
Ccmmunicatios may be relatively
to a bost mputer
Sims!e Such as a USB interface
ConsumeY eiectronic devices must meet
non funcional req uiremen ts
Several types cf strict
as well. , theyi
Many devices are battery operated
strict energy budgets
must cperake under
Co su mer electrooics are very inexpensive
sor $io.
A typica primary Processing chip must sell
e. mance .
These devices must also provid high perfor
power up interface

otK select pirectorg


USer play
Deode
Jig: Use case for playing muttimedia

connect
ot Synchronize)
File syster
UseY Host

tq Use case of synchvonizing wih a host system


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Embedded Systems and IOT Design

2lo devices

CPU DSP

Networ
irkerfaue
Storag+

ftq Hadwae architec hure of qeneric consumer


eleetronics device
The figure shows to
multiprocessor architechure.
mcYe computaion is required, more DSPs and

CPUs may be added.

The RISC CPU runs the operating system, Tuns

the Usey Tnterface, maintais the file system; The


DSP perfovms signal processing
:
File Systens
DOS File
Allocation Table (FAT) file systems
Yefer to the file system devel oped by .Microscft
for eary versions of the DOS
Opexaing System (Micoo).
FAT can be implemented on flas h storage
devices as well as
.maqnete disks
.

Wear levelinq algori


fhm can be implemented
withouk distuybing the file system:
FAT Can be implemeoted in, Small amount gfcodey
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Embedded Systems and IOT Design

CosurneY electYonic devtees use fladh


Many
mery is
memorg for mass storage Plash rne
type of semionductoy memovy provide s pexmanent
sturage Values ae stored in glash merory cell.
this cell does bot yequire an extenal power supply
The limitation of slash emory is' writing m

memory cell causes mechaícal' styets


|a flash
.
that eventually wears out the cel|
system (Ban45)
A wear leveling glash file
se of flash memory locafions
manages the use fo
shile
equalize wedr while maintai ning compatibility
with existing file systes.

|2. Platform. levesl perform an ce analysis :


Bus based systems add another layer of
complicati on to pexforman ce analyis. Platfovm level
perfornance inyolves much more than the cpU. Most
,
Precds ely cPU prorides an upper bound on performance
but any. other part of the system can, slow down
the cPU. Merely counting instruction exe cution:
tme is not enough
To moe datafrom nemory to the cpU,
wemn st ;
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Embedded Systems and I0T Design


read from the memory
• transfer over the bus to the cache
fer from the cache to toe CPU.
tras
CPU
Memory
cache

Data transfer!
Bus
d'g: Plat torm - Level data tous k performance
The time required to transfer from the cache

to the CPU ineuded io the instruction exeution time


The mnost basic measure
bandwidth (the rate at which the data tan be moved)!
Te simplest way to measure perfomance is in unit
of clock ycles -

Ta units of bus cycles T, convert bus ycle


Counb to real tim t using bus clock period P.
t TP
A basie bus transfer transfers
itself.: takes D
set of bytes. .The data trasfer
clock yles
Addresses, hands haking and other actvitied
constitute overhead that may occur before O, or
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Embedded Systems and IOT Design

after Oa For Sigplici ty, O= 0, +O


This gives a to tal transfer time in clock
yeles of
-
Tsasle CN)= (D+0)_A

2 B

: Times k datu volumes g: Times k data volu mes


in basic bus transfer in a burst bus tansfer
A
burst traxacti on
perfovms B trasfers
of w bytes each, which Yequi ves D clock cyeles The
'bus also iotroduces o clock ycles of overhead per
iburst This gives ,
Tburst CN) = (BD +o) N B

The widfh of a. memory determines the


number of bis read trom the memory in ycle. I

(6M

Tbit 4bits 8bit


ig: Memory aspect ratios
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Embedded Systems and I0T Design

"Tbe flq ure Shows memories of sarne


sire
can bave different aspet rattos. For e9) a b4 Mbit
memoy have b4 million addresses, the same size
memory ina 4 bit wide format have l6 million
add res

and a & bit wide memory have 8 mitl ion addres ses
The oemory system width may also be
determin ed by the memory mo dules we use
Instead;
of buying memory chips individually , may 'we buy
imernony as SIMMs or DIM Ms

The situation is
ligotly more complex,it
the data types don't fit natuYally into the width
ofthe memorY The total number of access es
Teequi re d to yead E data elemens of w
bit
each out of a memovy of width w is
A [(a).modw+1 .

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Embedded Systems and IOT Design

ARM processor & peripherals

I. ARM Processor:
ARM does notmanufacture i5 cwn chips j
licenses ik architecture fo corn panies who
rather it
or inteqrate the
either nanu.facture the (PU itse If
ARM pcceSSoY io to a larger system.
The tex tual desevip tion of instruetios
an
oppose d to theiy binary represen tation is called
astem bly anguage
ARM instructions are written one peY line,
the first lumn
Commen beqn
starting after
with a Sermicolon andd continue to the end of the
line. A label which gives Dame to a
ernog
m.

iocah on com es at the beginning of the line


starting in the first column.
, a
LDR Yo [Yg]; omment
ADD A,Yo, YIW.
ver.
Different versions of the ARM architeture
are identifed by number. ARMT iS non Neumanh

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Embedded Systems and IOT Design

wile ARM9 tnsiruc ttens


, cwever, this
lises vhlcure
tiffovenie i inisi ble to the assembly anquaqe
pe.m cxcpt fe possible pexfeymante dijferenie

lhe ARM tvchiechrc supper t ho kypes of

bits keng 3
.fhe standart ARM LweYd is
• (he
vrd may be divided into feur -bit S

byles
ARM1 allows addresses to be a bib
An addvess re
fevs to a byte, not a word. Therefore

the wovd O in the ARM addyess spae is at location O,

the woYd d s at 8 and so


woY d I s at 4;
on .

the
T6e ARM proce ssor Can be confiqured at
pouer up to address the bytes in a word io either
ittle endian or biq endian mode
Bit 31
Bito
word 4
Byte 2 Byte Byte o
i

Byte 3
word o
Httle endian
Bit 31
Bit o
word 4
te o Byte By tea!
By By te 3 word o

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Embedded Systems and IOT Design
2
Instruction set:
3Aritbo ettc and loqic cperatirns in C are
varíables Varia bles are implemenked
.
in.
performed
ds merncy ictaticr There fore. to be able to
ite insiruciicra te perforr C expressics anda

asstantnenta , rotut (on sider bcth arithmetc


and loqicaí instur ticnt s well as instructicns
fer veading and writing rnemor
In the ARM poceSSor arithmetic and legi cal
operaticns cannot be perfermed directly Cn
meme hocatios
load- steYe architecture ydata
ARM is a
into the CPU and
operands must first be loaded
to memog fo Save results.
then stored back main
Yo

T4 31
YS CPSR
T6
Y7
NzCV

TIO

YQ

YISCPC
ftg: Basic ARM programmin model.
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Embedded Systems and IOT Design

ARMqeneal prpose egisters Ta


hes l6
YIS, 4hey dye identical
threugh Ts. Except is,
any opeva fons that can be done on one of themn
Can be done on the others and,A F
has program
LounteY.
The the
other important basic reqisteY in

pregramming model is the urrent pyoqram status


registex ccpsR). <this reqi ster set au tomati ealy
duvin g every arithmetie ,logtcal or shifting pevaion
3}

The top four bi h of cpSR hold the fo llowtng


useful informaten about the results of that
arithmeti c | logical operafion :

• The neqative (N) bit is set when the vesu


it i
hegative in hoo 's complemen t arithmetic .

• The xero (z) bit is set when every bit of


the esult s LerO
.

• The Cary cc) bit is set. when there is a


carry out of the opevation
sthe over flow (v)
bit is set when an avitfmefid
oper afion resuIts in an over flow
These bi to can be used .to easily check the
Yesults of an arithmetic operatton
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Embedded Systems and IOT Design

ta instructi on
The basie form ofa da i
simpie

This instruction sets reqis ter To to the


S um of the values stored in I and ra. These

instruction may also provde im mediate operands


e-4) ADD ro ,TI, #2.
Sets ro to rI t+2.
ARM data instyuctions:
Arithmeti c :

ADD Add
w
ADC Add ith carY
SUB Su btract
SBC Subtract with carry
RSB Reverse subtract
RSC Reverse subtratt with carry
MUL Multiply
MLA Multiply cnd accurmulate.
:
|Logecal

AND Bitwise an d
ORR Bitwise or
o
EOR Bitwise exclusive
BIC Bit clear

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Embedded Systems and I0T Design

Sr.ft/rstale

A: Avihreetis hit eit

c(aaticni pererrm additior


verit.s e'sde

Saubt rartier
with the
th crder
wo operans reversed ,sc thaf RSe
and ta sets ro to be ra- YI.
"The bitwise kogical cperaticns perform
dogical AND, OR andXOR Opera hiors

BIC inst nuction stands for bit ciear;


eIC ro, Y!,rA ses Yo to and oot y.
TFe MLA ishucfion pejos mulipy
mulate epevation, pavHculavly useful in matvin

operatios and signal proc es sing

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Embedded Systems and I0T Design

ro, I,Y,Y?
MIA
Seb
o
to the vaue riX Y2 +r3.
sepa rate
Ihe shift oper atiors are not
,
which nay be applied to aritmefc
instructory.
.
tions
and logical instruc
ond Lsk modifies perforn left
*The sSL

logical shifis filling the le ast sigoificant


Iand rigst
zeros .

bik of the operand with

CMP Compare
CMN Ne qated compare
TST Bitwlse test
TEQ Bitwise neqated test

J3: ARM Compare instructions

MOV Move
MVN Move Neqated
Move Instrucfios- ARM

geneval
The Comparison opevands do not modify
purpase registers but only set the values of the

NZC bits CPSR Tegisterg


of the
CMP Yo, rl putes ro - rl, sets the status bit
Com

and thTOws away the result of subtraction


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Embedded Systems and IOT Design

of4
The instucton MOV Yo,rl sets the value
MVN instruction
Yo to the urrept value l. he
|com plernent the opevand bis during the tmove.

LDR Load
STR stove
LDRH Load half word
STRH Stove half word
LDRSH Load halfword signed
LDRB Load by te
STRB Sore by te
ADR Set register to addvess

ta: ARM Load- store Instructions

Vatues ar transferse d bekoen vegictes

and memorg using the load -store instructions.


load and store bytes ather than
DRB and sTRB
,
hole words while LDRH and STRH operates on
extends the Sgh bit on
half pr ds and
LDRSH

|loading An ARM address may be 32 bib dong

the 3a bit address wou ld not fit info an istuchon


so
that included an opeode an d operands. Instead,
the ARM uses egistex indirect addvessing
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Embedded Systems and IOT Design

3. ARM Architecture: d.09

Typical ARM7 Avchitecture:


A(31:0T

|Addess Reqister Addvess


Incrernegt
bu
f

PC

Regisler
bank ines

Instrucion
rol
bus
Muti pliex
Deoder Cont

ALU bus
bus

Shift
A

Dnstrucion
Reg
ALU

Thumb to
ARM
wtite Data vegRead
date fransiaor
Teq

D3:o]

Features:
Large unijo m
register file
Load / store archite kure (ony register

Cont en t not memory


Simple addvess ing modes (Registex
Instruetion 4elds).
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Embedded Systems and I0T Design

Uniform and fixed lenqts instuction


to simplify instruction decode.
ftelas,
-
architeture provi des tonlvol
The ARM

metic Joqic Unit (ALU) and


vey botk the Ait ons
in most data proces sing instructi
shifter
decve men t
Auto inre ment and auto
opfimize pregram loops.
addresing modes to

Load and store utiple reqisters to

naximize data throughput


CondiHonal exeution of almost a lt instuctio
to tmaximze exeution tiroughput
Continue with pNO: d-o3 & 2-04

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Embedded Systems and IOT Design

3. Assernbly , linking
and loading: 30

A ssernbly ond Linking are the (ast sfeps in

¡the compilahion proces. Loading actually puts


the program in mernoYg So that it can be exeuuted

High leve N (Assems Object


compiler Code Asserlert code
language
code

Hnker

Exeution Executable
Loader binary

fig: Program generation fem tompilakon


throug Loadirg

.he compilati on process is


often hidden from
ws by, compilation comman ds that do' everything

requived to qeneYate an exeutable progr ans.


Theassembler's: job, is o traslate
synbo lic " as sembly Lnguage. stateen t ibfo bit -
as
level 'representaton ef instrucfions known
.

object ode.
The assembler takes care of instructon
ts and does part of
tormats the job of trans lating
labels into addyesses
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Embedded Systems and IOT Design

program that brings the program 3-|1


The
a loader.
int memory for exeution is called
assumes
The simplest form of the assembler
at te starting addvess of the ass embly
karguge program has be en specified by the
Þorammer. The addresses ib such a ptegram
ake koown absolute addess es
as
Most assembles allows us. to use relative
addresses by speifying at the start fof the file
that the crigin ef the assembly
Language medule
is te be computed later
Assemblevs:
when translaking assembly code into object
op od es and
code, tthe assembler must trans late.
format the.bits in each instruction and translate
labels into addresses.
Labels make the assenbly process more
com plex, but. they are the most import ant. abstracion
bu assembler.
Provided the
Label pro
cessin g
requires mak ing koo
passes through the assembly source
code :

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Embedded Systems and I0T Design

y The 3-12.
pass scans the code to determine
fist
the address
of each label.

iThe seond pass ass enbles th e instuctions

|using the label valu es com pute d in.the st pass.


PLC
afd mo,I,Y2
X add Y3,T4, YS
Cmp ro,T3
39 Sub rS, Y6,r7
Symbol table
Assenbly ode

The name of each Spnbol and it addres i


Stoved in a Symbol table that s built during the
first pasS
The symbol table.s buit by scanning. from

the Hrst instruction to the last.

Duing Sinning the current location in


memorg kept in a Program Location Counter
(PLC).
The. PLC.is not used to ekecute proqram
the
to assign memory Locations to :
labels
Assemblers allow labels to. be
added to
the symbol table wiih but oceu pying spae tn pregram m cmo

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Embedded Systems and IOT Design

inking 3- )3

Many asseoby language programs are witt en

as several smaller pieces rather than as a single


-
Breaking a larger program into imaller
large gile
files helps delineate program modularit

A linkeY allows a proqram to bé sitched.


pieces
. The libkey
together out öf several smaller
assembler
operates on the. o bjeut ftles created by the

and mo difies the assembled code to make the


.
inecessay links between files
Some labels wil| be both.defined and used
me
file. other abels
will be defined
in the Same
used else ohere.
in a Single file but

The place in the file where label is

entry point. The place in


jdefned s known as
s is called an
the fle where the label sed
external referehce
The main job o4 the loader to esolve
external veferenees based on available enty
|poins
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Embedded Systems and I0T Design

l ab el l LDR TO,ri] label A DR


Varl
3-14

ApR a B label 3

B label

Varl
/. lo

ExtemalErty External Enfy


reference Poink Yeferences poin
label l Var |
label 2
label 3
var I

File I
a

File 2
tiq: Extern
al teference s and en txy point
The linker proceeds in fwo phases.
Cbject code design:

We ne ed to Con tro J
the placement of sevaral
types of data:
.
Interrupt vectos and o
ther informafion
tor Tlo devices must be placed in
specifte
ocatios.
Memog managenent tables nust be set

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Gtlobal vartables used Jor communication3-l5|


between processes must be put in locations that
iare accessible to al
the users o.f that data
Mang programs Should be desiged to be
Yeentrant. A pregram Yeentrant f it can be
intervupted by the function witho ut
another call to

proqvam
the results of ei ther call. Jy the
changes the value of qlobal variables, it may qive
ohen it is called recursively
.
different asers
program is re locatable if it can be
A

exeuted when loaded info diffevent pauts f


meno
Relocabability vequires some part of
Support from haYdluware that provt deS .address
caleulatio. But it is possi ble to ori te nonrelocatable'
code foT,. nonrelo catable architectures

be necessaxy to.
Some ases, it may
use nonrelo catable address Such as when
.
addressing Cn Tlo device

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4. Compilation Techni ques: 3-16

The Compilation process:


useful lo understand how a high level
language pre gramn is trams lated into instructions:

intervupt hand ting instuchions, placement f daba


and d instru cions
d
in memory ete
We Can Summ ari ze the compi lation process
with aa formula:

Compilation e tramaton + optienizatiou

The high level language program is translaed


into the lowet level fo of istuction: optinizatfond
ty to generate better instruction sequent es that
would be possible if the brute jorce technique
of independ antly trans lating source code stafements
we used.
Optimization technlques focus
the program to ensure that ompilation deisio ns
that ppear to be goo
d for statement are
hot unnecessari y problem atic for other parts
of the pregram.

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|parctng, yol table .gruotinas, sennah. aolyi

nstructicn level optitrtzafi ns


and Cocte qeneation

Asuntly vode

J'g:Ihe oropilation. proess


guage
Conmpilatien begins with bigh level lan

Code Such as C
oand generally produces

as sembly ode
The high level language progam is pavsed

to break it into statemen to and expressins .

addition syonpol table is gene yafed which inc udes

all the hamed objech in fhe program


Sinplging arithmefic ekpressios is one
example o a machine independent opftmizations .

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înstruction level opinizaicrs are


They nay ore oirectty o
at generafing ede:
ructisr jermat
real istructics or oha pseudo- inst
is later mapped onto the irstruetoro et
that
the tarqet cpu.

Basic Compilation methods:


The basie compilatio tmethcds are :

Compiling ari tt netie express'crk


a
• Generating code for cenditiera
• Procedure linkaqe in C.
The compil nust also translate retererces
to data stru ctures ibtoveferences to ra
memories.
n general, this requires address
com putations

Arayt are iotevesting because the addres:

array element must in general ibe computed


an
, index may charge.
at Tun time. becau Se the
aCiJ
e-g)
The layout is given by :

alo]
ar

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The zeroth element s stored as the Jirst'9


element of the arYayi We can Create a peinter
for the array that poins to the .array's head

hamely a $f we call the pointer apt, wwe cn


[oj.
write the veading of al'3 as
* (aptr+).
Tuoo dimension a arrays more challenging
There are multiple possi ble as to Layout a

two dimensional arry in memorg

Let us Consider the Yow - mjor form. Tf the


al] aY
y
s of Size N x M, hen we can tum the
avray acce ss info a one.dimensíonal
fwo dimensional
accesS
,
thus, ali,j]becom es a [i*M +j]
where the maximum value jor. j

a[o,o]
alo,]

all,o]
ali,]

Jg Memeg layout for huo dinension al

The addition(aptr +4) Can usu ally done


at compile time, reqiving only the indirection itself
ving only
to fetch the memoy location during exeution.

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Compiler optimizatiers:
Baste compilafien te chniques ceute
ineffuent wde
.Compilers usc a
Can
wide ranqe
.
y
algori thmd to optimi Ze the code they oyeneva te
A
simple but useful transformatien is
known as loop unrolling Tt impertant
because it helps expose parallelism that Cn
be used by later stages of the compiler.

Loop fus ion combines fwo more loops


,
sinqle loop- For this trams formaton kwo
(onditios must be Satis fied.
. The loops nust iterate oveY the same

values. The loop bodies


must not have

dependenies that would be vio lated they are s


exeuted toqe ther.

Loep d stri bution is the opposite of loep


fusion, that is decomposing a single loop into mutiple
loops
Loop tling breaks up à Loop into a set ef
nested lo ops ach inner loop
with each inner performing tke
operaios Subset of the data.
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Array padding adds dummy data elernenk


a to change the layout of the array
to loop inorder
in the ca che
Dead code is the code that nevey be
n

exeuted. Dead code can be generated by the


Pregrammevs and compilers purpose fuly
Dead code Can be
be identifed by reachabilty
an atysis - jinding the other statemen ts or instructions

Jom which it can be reached


Deado de elimination an alyzes code for
rea reach abili t an d trims away dead code
Register allotation is a Verg inpovtant
phase Tf a seetion
a seetton of code requires
Lompilatow
we tnust spill
more r egistevs than are available
v
alues out to memg tenpoy avi g
Sone of the
we can solve glster allocatons problems
bulding conflict qraph and solving
by

gvaph oloing problen.


CosideY, (a+b) *(e-d) we can do mu ltiplicaki

do eithex o r
last but bu we can ddi tion subtractou
first...
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5. Proqr am level perform ante an alysis : 3-Q

Because ermbedded systems nust perform


real time, we koowbow
fun ctions in of ten need to

fast a program YuS.

inmportant to keep cpu


ît is in mind that
Per foxman e is not judqed in the same
perfornante
The exeution tme of a proqram often
vaxies with the input data values because those
values sel et diffexent executiOn paths in the
Program. for example, loops roay be executed a
Vaying oumber times and diffevent branches
may exeut e blocks og
vargig Lomplexity
The cache has a major effedt On Program

|Performan
ce
and once agaun the cache's behavior
on input to
dependa in part the data values the
|Progtam

Cache

Total exeution tine


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rieline epend et ny on lht isufin but

Sene icvcprocesser rantactress uppy


for their CPVs ihe Simulator Yun on a
simulaors
oY PC, tates as input an cxeal able for
twrrkstation
input date an d
The micYcpvoccsseY along with

Simulates the exeuution 4 the Program

•A time corected to the micvoproteASeY

bus
c cun
be uSed to me asuYe pexfovmanc e of
executn sectios of code.
analyze* can be connected to
•A Logie he
microprocessor bus to measure the start and
stop times of code Segment

There are three diffevent tpes of


:
Perfovmante neusuY es Prorams
i) Aver age case exeutron {ime:

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3 -24
This is the typical exeuti on ime
we
wbuld evpect for typical data Clearly. tke

fst chale nge u defining typical inputs .

) WorSt cas e :
exeution time

The Pon qest time that the program


spen
Can inpul sequenee in dearly
d y

inportant for yst em that must meet deadlines


luy Best case exeution time:
This neasure can be important in
Tate
multi Tate veal time systems

Elements of proqram performante :

The key to evaluatig exeution time s


breaking the per formance problem into part.
Proqrcn exeutlon time (sha s9) tan be seen as:

exeution time proqram pat +


instrueion
timing

The path is the sequences og instructi


ex euted by the program. The instruction iming
deter mined the squence of instrucions.
.based on the

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3-5
The sinplest estinate of instructton timing
{s fo that every instucton takes the
as sume that
Same numbe of clock cyele
yeless ie) we need only
count the inatuctons
and multiy by the per
in sHvucion exeution time to obtain Ae proqram's
|total exeu tion time
• Not all the tstructors take the S ame
amount f time.

Exeution tmes of isructios are not
independent.
• The
exeution time of Qn instuction may
mag
depend operan d values.

Measurement dri ven performan ce analysis :

The most dirett way to deteYmine the


exeutton ime of a Program is by measurng it.
the dr awbacks are toordey to cause the program
to exeute ib worst case executioh path , we
have to provide preper input to it
Most mefhoda
of measuring program
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pevfnce combire the delvrminatin of thr


exction path and the lininq ng thot palk
,
Pregiam cxeutes it choeses
obseve the xeeution ine afer
that t.
concidoing that prrgram
mratuTing progran
"he biggest pseblem in
a set { input
performance iw
jguring out usful
prehlerowit inpat
to give he program-.he7he othee

dala is the Softuwav e Jcafolding

Pofiling in a simple methoá for analyeing

perfotman ce. A pro.filer doer not


Software
cOf
it coun
s the nutnber
jexeution tme- istead
proce dures or basic blocks in the
tines that
Pegvom are exe cuted.

The alternatve to Phgeical mecsuYement


. tin
exe cution time s simulation dno
of
for puipose pev anatyt
f fovmance ,the
Inost impovlant yPe of cpu simalat is the
Cqle -acurate simula for wbich per form a Suýfiienty
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3-,
detaled simul atior f thc prot essor ' intenals i

rat it can deeshure the exact humber


.

dect qcles veqived for execution


A
sirulatbr that functionally simulates
jnstvuchins but does not provide timing information
:
insirucion evel simulator

6. Sojtware Performance optimizatien :

:
Loep Opimizatios
Loeps are inpov ant target fo
optini zatton
because programs with loops tend to spend a lot
cf ine exeuting these loops
there are three important techniques in
ophimizing oo ps :
code notion
induction variable elimin ati on
strength reduc hion.

Code oo tion moves ubnecessary code out


a oop a computatton 's vesult does not
f If
depend on operations performed in the loop body,
then we can safely move it out of the loop.
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Embedded Systems and IOT Design

3- 8

eq) for (iz0; i4 *M;i++)


N
;
z[i]: a[i]+b [iJ

a vaiable ohose value


An induction variable is
's
iteration varable
the loop
5 derive d from
indu ction
vaue. The compilex otten introduces
t loop
|vavi ables to help it implenen the
besked loop is a good example :
A

for (i =o; izN; i+)


for j =0; jz
M
;j++)
=
z[iJj] b(ig cj];

templaN* M;

KiZNM2 Ltenp
F
T
T
z[iJe aci3+ B01; z Cij=a[i+b(i];
i++) t+)

Before After
fa: Code motion in a loop

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for (i =0 ; i 2Nji+) 3-a4


for j =o;j <M; jtt){
zbinduet=itM+j
* (zptr + z binduct ) -
*(bptr+zbinduct);

Tn the above code zptr and bptr a re pointevs


to the heads af the Z and b arrays and zbinduet

is the shared variab le


zbinduct -o;
for ti z0; i ZN; it+){

=
*Eptr +zbinduct ) * (bptr +zbinduct );
zbin duct ++;

This is a form of strength inde Teducion


because we have eliminated the mu ltiplicaton
m

the indution variable computafion.


trenqth reducton helps us to reduce the
cost of loop iteraton.

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Cache optinizations! 3-30

A loop nest is a set of loops one inside the


process arrays
other. Loop hes t ocuY when we
beer developed
A lavge body of
lechniques ha
Dests
loop
for optimizing loop nest. Rewriting a

phanges the order in which array elemen % are


Qccess ed.

Perfrmance Optimization strateqies:


implementa tion are:
few hins on Program
•y to use Ygisters
to efiienty
Make use of paqemode access
. in the
possible
memoxy system uohenever
.

• For instruction conflicts tsy to rewrite


to make it as Small as possible .

the segment
,
• For scalar data conflicts move the
to Te duce
vaues to di fferent locatios
data
con ficts
• for data
aYYay conflica, consider

either moving the arrag chanqing your a YYay

access pattevns to redue tonick


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power analysts 3-3


7. Proqram level energy and and
-Optimization :
Power consunpion is a partaulavly impovknt

desigr metrie for batery poweved systems because


the battery has very limited lifetime
The opportunities JoY saving 1he power aYe:

• We may able to replace the alqorithms

wih others that do things in elever uoay that


consumes less pouer:
component
Momog accesses ar e a major
oy power consumption in man applicati o . By
Bg

memorg acesse we may be able to


opi mizinA
pouwer
Signiicanty reduce
We may able ko turn off pavts of
I• we
sgem.Sueh Subsystema of the cpu, when
tA em inoYder to S ave power.
don' heed
Several factors contribute to the energy
program are
consumption of the
• Ener g4 consumption varies Someuhat.

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3-32
instuctHon
fvom inst uctton to
sequence of instruchons has some
Ihe
inguere location of the
.the opuode and the
matter
operands also
Amneter
Current

Power while (True)


sup'y testcodec);

CPU

consu mpton for a piece of code


fig: Measuig powe

chosing which istructions to use can make


en ergy consumption
Some diffexences in a program's

but concecentrating
on the instruction opcodes has

limited pay otfs in most cPUs

In many appicatiom , the biggest payf


in energy reduehon for a iven anoun t f desigrer

comes from Concentrating on the menog


|effort
system.

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Embedded Systems and IOT Design

3 -33
irnportant factor
en e8g in
Caches are an

ConsumpHon On the ne hand, a cache hit saves


. o

on the o fher, the


memory access and
Cost ly nain
cache itsely is relatvely power hungry beause
SRAM not DRA
It is built from
As the tnstruction cache size jncyeases, the
energy ost the software
on the Cpu decines,
f
com es to dooinate the
but the istrucion cache

energy coMumpi on
TE 4he cadhe is too small, he proqrams

and the system Consu mes lot of


run stog
higa cost of main' memoTy
Power due to the
accesses
improvi ng energy cons umption ,
for
•y to use regest ens efftienty
• For S
calar move the
data conflics,
lo cattorrs to reduce congfbeb.
data values to different
• For array
data confies. consider
eith er movinq the
the arsgs or changing your aray
arag
accesspatterns to neduce confliets
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Analysi s pxogam 334


8.&. and opimization of size :

The memony
ofa prrgram
footpuiod

determined by of its dala and


tie size ot istrucion.
Both must be cosidere d to minimize pongramsi7e :
Data provide an excellent oppor tunity foY
ave most htqhly
mininizing size because the data
|dependent programmieg shyle.

A very low level technique for minimizi ng


veuse values
data th For instance, f seveval
cosiants happen toto have he same value, they can
be mapped to
bo the Same location.

Data buffers can be veused at several


pn
ots
different point in the program.
Minimiz"g the sixe of the is ructon
pregram requi res a
mix of high.level
program trasform atn and careful instuchion
seleetion En capsulating Junclions In subroutin es
Can redu ce proqram size when done carefulty
reduce

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3-35
when
educing the numbex of instructtos in
,
a Pogvan one toporiant technique is the preper
use of subroutines T{ the program performs

id entical operatiens vepeatedys these operatitos


are natural eandi dates for subroutines .

Some mieropwcessor architectures suppovt


dense instruction Sets, spei ally designed instruction
sets that use shorter instution for mata to encode
the istsuci ons.
The ARM thumb
instuction set and the MIPS
6
istructon set for the MtPS architecture are
hwo examples of this bype of instruction set.

Speial com pi lation modes produe the


program interms of the dense instruction Set.

Program size of tourse vavies oith the type of


Program, but' pograms using the dense istetion
Set are often To-8o of the size of the
|stan dard instruction set equi valents .

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3-36
|9- Proqram Validation and Testing:
ensure
Systes need testing to
Complex
:
intended
|th at they work as they are
We carn use various
Combinatiors
of two
rmajor types of testing
stvategies.
|
Black- box methods qenevate tests witout
) program.
structere of the
Looking at the internal
knowon as wbite box,
i) cleaY-box also
tests based on the Program
methods Jenerate
stuctue.
clear box testing:
low qraph extracted from
The contol /data f
an important hool in
SouYce tode is
program.
clear -box test for the
developing
these
Ihorde to exeute and evaluale
we must be able to control variables in he
tests,
program and observe the resulis of computatiors
ruch as in manufachuring testing Dn general we
heed to modify the program to make it more testable
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ave esting we must


3;37
No matter what we
thvee things in a ist:
accomplsh the follouing
program wlth inputs that
•Povide the
we ave interested in.
exerise the test
program to perform the test.
the
Execute
• Examine the outputs to determina
whether

was succe ssful.


the test
the set of
the next task is to determine
tests to be performed we need to pe form manY
we have
types of tests to be lon-fid ent that
|iffevent
idenkijied a large frati on of the existing bugs

Gtraph theory helps us get a quantitafive


Dn an
on the different paths required.
handle
undirected graph, we can fom any pah througk
.
Jrom tombinations of basic patts
Ithe graph
The graph is repres enfed as an
ibi dence
E ach row and olumn epresents a node.
matix. to
we can use standavd linea algebra techniques
identt f the dasis set of the graph

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[Mec1
A sinple measuTe, yelonatie complexity
all ows us to measure the control complexity of Hhe

Program. given bg'


The yelonaie complexity i
M :e-n+p
where, e number of edges in the floo grap h

n number of nodes
graph
p number of com pon ent in the

a b d e

d
e
Graph
hiden ce mafrix
a b d e

Basis set
ta: Matix esentation
f graph A basis set.

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3 -39
3

hb

v
(a) -8-6+3 =4

Compleci ty
Sg: ydomate
Ahother way of ooking at control flouw oviented

testtng in to analye the conditions that control the


conditionak statements.
if Cca= =b) || (c>=d)(-. .)
A simple condition testing strategy s known

branch testing
Frankl and weyuker (Fra 8a) have defined
fo exercise
eriteria for choosi ng which def-use pairs
to sati g well behaved adequay criterion
cwe
there are several Important cas es hat
should ty at a minimum
:

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•Skipping the loep entiYey

•One loop iteraton


• Two loop itera fions
n on the oum bey
s an upper bound
• T{ there
iteraiors a value that sis sigoifi canty below
loop
of
iteratioMs
maximum num ber
that number
upper boun d on the
+
Test hear the

6f loop
iteraions that bs n-) hh +.

Black box testing:


box tes ts Ye generated witheut
are
Blak
being tested
|knowledge of the code
category of black
Randorm tests tom One

a glven
Random values are genevated
with
box test.
distribu kon The expeted values are computed

|independenty of the system and then the inputs are


to gen erate.
«pplied. These tests are easy
Reqressien testi form an extremey inporfant

tategory of tesk. when tests are Created du ving


or joY previous
eanlier stages In he system design
versons of the System, those tests save d

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