EEPROM:
In the design of all microprocessors-based systems, semiconductor memories are used as
primary storage for code and data. Semiconductor memories are connected directly to the
CPU and they are the memory that the CPU first asks for information (code and data).
For this reason, semiconductor memories are sometimes referred to as primary memory.
Important Terminology common to all Semiconductor Memories:
Memory capacity:
The number of bits that a semiconductor memory chip can store is called chip capacity. It
can be in units of Kilobits, Megabits and so on. This must be distinguished from the
storage capacity of computer system. While the memory capacity of a memory IC chip is
always given in bits, the memory capacity of a computer system is given in bytes.
Memory organization:
Memory chips are organized into a number of locations within the IC. Each location can
hold 1 bit, 4 bits, 8 bits or even 16 bits, depending on how it is designed internally. The
number of bits that each location within the memory chip can hold is always equal to the
number of data pins on the chip. i.e., the total number of bits that a memory chip can
store is equal to the number of locations times the number of data bits per location.
Speed:
One of the most important characteristics of a memory chip is the speed at which its data
can be accessed. The speed of the memory chip is commonly referred to as its access
time. The access time of memory chip varies from a few nanoseconds to hundreds of
nanoseconds, depending on the IC technology used in the design and fabrication process.
The different types of memories are RAM, ROM, EPROM and EEPROM.
RAM and ROM are inbuilt in the microprocessor.
The data, which is an important factor, has to be stored in such a location where it cannot
be erased when power fails and also the data should be allowed to make changes in it
without the system interface i.e., there should be a provision in such a way that the data
should be accessed (or modified) while it is in system board but not external erasure and
programming. The flash memory inbuilt in the microcontroller can erase the entire
contents in less than a second and the erasure method is electrical. But the major
drawback of Flash memory is that when flash memory’s contents are erased, the entire
device will be erased but not a desired section or byte.
For this purpose, we prefer EEPROM in our project.
EEPROM (Electrically Erasable Programmable Read only memory)
EEPROM has several advantages over other memory devices, such as the fact that its
method of erasure is electrical and therefore instant. In addition, in EEPROM one can
select which byte to be erased, in contrast to flash, in which the entire contents of ROM
are erased. The main advantage of EEPROM is that one can program and erase its
contents while it is in system board. It does not require physical removal of the memory
chip from its socket. In general, the cost per bit for EEPROM is much higher when
compared to other devices.
The EEPROM used in this project is 24C04 type.
Features of 24C04 EEPROM:
1 million erase/write cycles with 40 years data retention.
Single supply voltage:
3v to 5.5v for st24x04 versions
2.5v to 5.5v for st25x04 versions
Hardware write control versions:
st24w04 and st25w04
Programmable write protection.
Two wire serial interface, fully i2c bus compatible.
Byte and multi byte write (up to 4 bytes).
Page write (up to 8 bytes).
Byte, random and sequential read modes
Self timed programming cycle
Automatic address incrementing
Enhanced ESD/Latch up performances
Description
The 24C04 is a 4K bit electrically erasable programmable memory (EEPROM),
organized as 2 blocks of 256 x8 bits. They are manufactured in ST Microelectronics’ Hi-
Endurance Advanced CMOS technology which guarantees an endurance of one million
erase/write cycles with data retention of 40 years. Both Plastic Dual-in-Line and Plastic
Small Outline packages are available.
The memories are compatible with the I2C standard, two wire serial interface which uses
a bi-directional data bus and serial clock. The memories carry a built-in 4 bit, unique
device identification code (1010) corresponding to the I2C bus definition. This is used
together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices may be attached
to the I2C bus and selected individually.
The memories behave as a slave device in the I2C protocol with all memory operations
synchronized by the serial clock. Read and write operations are initiated by a START
condition generated by the bus master. The START condition is followed by a stream of
7 bits (identification code 1010), plus one read/write bit and terminated by an
acknowledge bit.
When writing data to the memory it responds to the 8 bits received by asserting an
acknowledge bit during the 9th bit time. When data is read by the bus master, it
acknowledges the receipt of the data bytes in the same way. Data transfers are terminated
with a STOP condition.
Power on Reset: VCC lock out write protect
In order to prevent data corruption and inadvertent write operations during power up, a
Power on Reset (POR) circuit is implemented. Until the VCC voltage has reached the
POR threshold value, the internal reset is active, all operations are disabled and the
device will not respond to any command. In the same way, when VCC drops down from
the operating voltage to below the POR threshold value, all operations are disabled and
the device will not respond to any command. A stable VCC must be applied before
applying any logic signal.
Signal descriptions
Serial Clock (SCL)
The SCL input pin is used to synchronize all data in and out of the memory. A resistor
can be connected from the SCL line to VCC to act as a pull up.
Serial Data (SDA)
The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is
an open drain output that may be wire-OR’ed with other open drain or open collector
signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as
pull up.
Chip Enable (E1 - E2)
These chip enable inputs are used to set the 2 least significant bits (b2, b3) of the 7 bit
device select code. These inputs may be driven dynamically or tied to VCC or VSS to
establish the device select code.
Protect Enable (PRE)
The PRE input pin, in addition to the status of the Block Address Pointer bit (b2, location
1FFh as in below figure), sets the PRE write protection active.
Mode (MODE)
The MODE input is available on pin 7 and may be driven dynamically. It must be at VIL
or VIH for the Byte Write mode, VIH for Multibyte Write mode or VIL for Page Write
mode. When unconnected, the MODE input is internally read as VIH (Multibyte Write
mode).
Write Control (WC)
An hardware Write Control feature (WC) is offered only for ST24W04 and ST25W04
versions on pin 7. This feature is useful to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or
disable (WC =VIL) the internal write protection. When unconnected, the WC input is
internally read as VIL and the memory area is not write protected.
Device operation
I2C Bus Background
The ST24/25x04 supports the I2C protocol. This protocol defines any device that sends
data onto the bus as a transmitter and any device that reads the data as a receiver. The
device that controls the data transfer is known as the master and the other as the slave.
The master will always initiate a data transfer and will provide the serial clock for
synchronization.
The ST24/25x04 is always slave devices in all communications.
Start Condition
START is identified by a high to low transition of the SDA line while the clock SCL is
stable in the high state. A START condition must precede any command for data transfer.
Except during a programming cycle, the ST24/25x04 continuously monitor the SDA and
SCL signals for a START condition and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition terminates communication between the
ST24/25x04 and the bus master. A STOP condition at the end of a Read command, after
and only after a No Acknowledge, forces the standby state. A STOP condition at the end
of a Write command triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful data transfer. The bus transmitter,
either master or slave, will release the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of
the 8 bits of data.
Data Input
During data input, the ST24/25x04 samples the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation the SDA signal must be stable during
the clock low to high transition and the data must change ONLY when the SCL line is
low.
Memory Addressing
To start communication between the bus master and the slave ST24/25x04, the master
must initiate a START condition. Following this, the master sends onto the SDA bus line
8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or
WRITE bit. The 4 most significant bits of the device select code are the device type
identifier, corresponding to the I2C bus definition. For these memories the 4 bits are fixed
as 1010b. The following 2 bits identify the specific memory on the bus. They are
matched to the chip enable signals E2, E1.
Thus up to 4 x 4K memories can be connected on the same bus giving a memory capacity
total of 16 Kilobits. After a START condition any memory on the bus will identify the
device code and compare the following 2 bits to its chip enable inputs E2, E1. The 7th
bit sent is the block number (one block = 256 bytes). The 8th bit sent is the read or write
bit (RW), this bit is set to ’1’ for read and ’0’ for write operations. If a match is found, the
corresponding memory will acknowledge the identification on the SDA bus during the
9th bit time.
Write Operations
The Multibyte Write mode (only available on the ST24/25C04 versions) is selected when
the MODE pin is at VIH and the Page Write mode when MODE pin is at VIL. The
MODE pin may be driven dynamically with CMOS input levels. Following a START
condition the master sends a device select code with the RW bit reset to ’0’. The memory
acknowledges this and waits for a byte address. The byte address of 8 bits provides
access to one block of 256 bytes of the memory. After receipt of the byte address, the
device again responds with an acknowledge. For the ST24/25W04 versions, any write
command with WC = 1 will not modify the memory content.
Byte Write
In the Byte Write mode the master sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer by generating a STOP condition. The
Write mode is independent of the state of the MODE pin which could be left floating if
only this mode was to be used. However it is not a recommended operating mode, as this
pin has to be connected to either VIH or VIL, to minimize the stand-by current.
Multibyte Write
For the Multibyte Write mode, the MODE pin must be at VIH. The Multibyte Write
mode can be started from any address in the memory. The master sends from one up to 4
bytes of data, which are each acknowledged by the memory. The transfer is terminated by
the master generating a STOP condition. The duration of the write cycle is Tw = 10ms
maximum except when bytes are accessed on 2 rows (that is have different values for the
6 most significant address bits A7-A2), the programming time is then doubled to a
maximum of 20ms. Writing more than 4 bytes in the Multibyte Write mode may modify
data bytes in an adjacent row (one row is 8 bytes long). However, the Multibyte Write
can properly write up to 8 consecutive bytes as soon as the first address of these 8 bytes is
the first address of the row, the 7 following bytes being written in the 7 following bytes
of this same row.
Page Write
For the Page Write mode, the MODE pin must be at VIL. The Page Write mode allows
up to 8 bytes to be written in a single write cycle, provided that they are all located in the
same ’row’ in the memory: that is the 5 most significant memory address bits (A7-A3)
are the same inside one block. The master sends from one up to 8 bytes of data, which are
each acknowledged by the memory. After each byte is transferred, the internal byte
address counter (3 least significant bits only) is incremented. The transfer is terminated
by the master generating a STOP condition. Care must be taken to avoid address counter
’roll-over’ which could result in data being overwritten. Note that, for any write mode,
the generation by the master of the STOP condition starts the internal memory program
cycle. All inputs are disabled until the completion of this cycle and the memory will not
respond to any request.
Minimizing System Delays by Polling on ACK
During the internal write cycle, the memory disconnects itself from the bus in order to
copy the data from the internal latches to the memory cells. The maximum value of the
write time (Tw) is given from the AC Characteristics, since the typical time is shorter, the
time seen by the system may be reduced by an ACK polling sequence issued by the
master.
Data in the upper block of 256 bytes of the memory may be write protected. The memory
is write protected between a boundary address and the top of memory (address 1FFh)
when the PRE input pin is taken high and when the Protect Flag (bit b2 in location 1FFh)
is set to ’0’. The boundary address is user defined by writing it in the Block Address
Pointer. The Block Address Pointer is an 8 bit EEPROM register located at the address
1FFh. It is composed by 5 MSBs Address Pointer, which defines the bottom boundary
address and 3 LSBs which must be programmed at ’0’. This Address Pointer can
therefore address a boundary in steps of 8 bytes.
The sequence to use the Write Protected feature is:
– write the data to be protected into the top of the memory, up to, but not including,
location 1FFh;
– set the protection by writing the correct bottom boundary address in the Address
Pointer (5 MSBs of location 1FFh) with bit b2 (Protect flag) set to ’0’. Note that for a
correct functionality of the memory, all the 3 LSBs of the Block Address Pointer must
also be programmed at ’0’. The area will now be protected when the PRE input pin is
taken High. While the PRE input pin is read at ’0’ by the memory, the location 1FFh can
be used as a normal EEPROM byte.
Read Operations
Read operations are independent of the state of the MODE pin. On delivery, the memory
content is set at all "1’s" (or FFh).
Current Address Read
The memory has an internal byte address counter. Each time a byte is read, this counter is
incremented. For the Current Address Read mode, following a START condition, the
master sends a memory address with the RW bit set to ’1’. The memory acknowledges
this and outputs the byte addressed by the internal byte address counter. This counter is
then incremented. The master does NOT acknowledge the byte output, but terminates the
transfer with a STOP condition.
Random Address Read
A dummy write is performed to load the address into the address counter. This is
followed by another START condition from the master and the byte address is repeated
with the RW bit set to ’1’. The memory acknowledges this and outputs the byte
addressed. The master has to NOT acknowledge the byte output, but terminates the
transfer with a STOP condition.
Sequential Read
This mode can be initiated with either a Current Address Read or a Random Address
Read. However, in this case the master DOES acknowledge the data byte output and the
memory continues to output the next byte in sequence. To terminate the stream of bytes,
the master must NOT acknowledge the last byte output, but MUST generate a STOP
condition. The output data is from consecutive byte addresses, with the internal byte
address counter automatically incremented after each byte output. After a count of the
last memory address, the address counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode
In all read modes the ST24/25x04 wait for an acknowledge during the 9th bit time. If the
master does not pull the SDA line low during this time, the ST24/25x04 terminate the
data transfer and switches to a standby state.
